xref: /haiku/src/add-ons/kernel/busses/usb/uhci.h (revision f23596149e0d173463f70629581aa10cc305d32e)
1 /*
2  * Copyright 2004-2006, Haiku Inc. All rights reserved.
3  * Distributed under the terms of the MIT License.
4  *
5  * Authors:
6  *		Michael Lotz <mmlr@mlotz.ch>
7  *		Niels S. Reedijk
8  */
9 
10 #ifndef UHCI_H
11 #define UHCI_H
12 
13 #include "usb_p.h"
14 #include "uhci_hardware.h"
15 #include <lock.h>
16 
17 struct pci_info;
18 struct pci_module_info;
19 class UHCIRootHub;
20 
21 
22 class Queue {
23 public:
24 									Queue(Stack *stack);
25 									~Queue();
26 
27 		bool						Lock();
28 		void						Unlock();
29 
30 		status_t					InitCheck();
31 
32 		status_t					LinkTo(Queue *other);
33 		status_t					TerminateByStrayDescriptor();
34 
35 		status_t					AppendDescriptorChain(uhci_td *descriptor);
36 		status_t					RemoveDescriptorChain(
37 										uhci_td *firstDescriptor,
38 										uhci_td *lastDescriptor);
39 
40 		addr_t						PhysicalAddress();
41 
42 		void						PrintToStream();
43 
44 private:
45 		status_t					fStatus;
46 		Stack						*fStack;
47 		uhci_qh						*fQueueHead;
48 		uhci_td						*fStrayDescriptor;
49 		uhci_td						*fQueueTop;
50 		benaphore					fLock;
51 };
52 
53 
54 typedef struct transfer_data_s {
55 	Transfer		*transfer;
56 	Queue			*queue;
57 	uhci_td			*first_descriptor;
58 	uhci_td			*data_descriptor;
59 	uhci_td			*last_descriptor;
60 	area_id			user_area;
61 	bool			incoming;
62 	transfer_data_s	*link;
63 } transfer_data;
64 
65 
66 class UHCI : public BusManager {
67 public:
68 									UHCI(pci_info *info, Stack *stack);
69 									~UHCI();
70 
71 		status_t					Start();
72 virtual	status_t					SubmitTransfer(Transfer *transfer);
73 		status_t					SubmitRequest(Transfer *transfer);
74 
75 static	status_t					AddTo(Stack *stack);
76 
77 		// Port operations
78 		status_t					GetPortStatus(uint8 index, usb_port_status *status);
79 		status_t					SetPortFeature(uint8 index, uint16 feature);
80 		status_t					ClearPortFeature(uint8 index, uint16 feature);
81 
82 		status_t					ResetPort(uint8 index);
83 
84 private:
85 		// Controller resets
86 		void						GlobalReset();
87 		status_t					ControllerReset();
88 
89 		// Interrupt functions
90 static	int32						InterruptHandler(void *data);
91 		int32						Interrupt();
92 
93 		// Transfer functions
94 		status_t					AddPendingTransfer(Transfer *transfer,
95 										Queue *queue,
96 										uhci_td *firstDescriptor,
97 										uhci_td *dataDescriptor,
98 										uhci_td *lastDescriptor,
99 										bool directionIn);
100 static	int32						FinishThread(void *data);
101 		void						FinishTransfers();
102 
103 		// Descriptor functions
104 		uhci_td						*CreateDescriptor(Pipe *pipe,
105 										uint8 direction,
106 										size_t bufferSizeToAllocate);
107 		status_t					CreateDescriptorChain(Pipe *pipe,
108 										uhci_td **firstDescriptor,
109 										uhci_td **lastDescriptor,
110 										uint8 direction,
111 										size_t bufferSizeToAllocate);
112 
113 		void						FreeDescriptor(uhci_td *descriptor);
114 		void						FreeDescriptorChain(uhci_td *topDescriptor);
115 
116 		void						LinkDescriptors(uhci_td *first,
117 										uhci_td *second);
118 
119 		size_t						WriteDescriptorChain(uhci_td *topDescriptor,
120 										iovec *vector, size_t vectorCount);
121 		size_t						ReadDescriptorChain(uhci_td *topDescriptor,
122 										iovec *vector, size_t vectorCount,
123 										uint8 *lastDataToggle);
124 		size_t						ReadActualLength(uhci_td *topDescriptor,
125 										uint8 *lastDataToggle);
126 
127 		// Register functions
128 inline	void						WriteReg8(uint32 reg, uint8 value);
129 inline	void						WriteReg16(uint32 reg, uint16 value);
130 inline	void						WriteReg32(uint32 reg, uint32 value);
131 inline	uint8						ReadReg8(uint32 reg);
132 inline	uint16						ReadReg16(uint32 reg);
133 inline	uint32						ReadReg32(uint32 reg);
134 
135 static	pci_module_info				*sPCIModule;
136 
137 		uint32						fRegisterBase;
138 		pci_info					*fPCIInfo;
139 		Stack						*fStack;
140 
141 		// Frame list memory
142 		area_id						fFrameArea;
143 		addr_t						*fFrameList;
144 
145 		// Queues
146 		int32						fQueueCount;
147 		Queue						**fQueues;
148 
149 		// Maintain a linked list of transfers
150 		transfer_data				*fFirstTransfer;
151 		transfer_data				*fLastTransfer;
152 		sem_id						fFinishTransfersSem;
153 		thread_id					fFinishThread;
154 		bool						fStopFinishThread;
155 
156 		// Root hub
157 		UHCIRootHub					*fRootHub;
158 		uint8						fRootHubAddress;
159 		uint8						fPortResetChange;
160 };
161 
162 
163 class UHCIRootHub : public Hub {
164 public:
165 									UHCIRootHub(Object *rootObject,
166 										int8 deviceAddress);
167 
168 static	status_t					ProcessTransfer(UHCI *uhci,
169 										Transfer *transfer);
170 };
171 
172 
173 #endif
174