1 /* 2 * Copyright 2005-2008, Haiku Inc. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Jan-Rixt Van Hoye 7 * Salvatore Benedetto <salvatore.benedetto@gmail.com> 8 */ 9 10 #ifndef OHCI_HARD_H 11 #define OHCI_HARD_H 12 13 // -------------------------------- 14 // The OHCI registers 15 // -------------------------------- 16 17 // -------------------------------- 18 // Revision register (section 7.1.1) 19 // -------------------------------- 20 21 #define OHCI_REVISION 0x00 22 #define OHCI_REVISION_LOW(rev) ((rev) & 0x0f) 23 #define OHCI_REVISION_HIGH(rev) (((rev) >> 4) & 0x03) 24 #define OHCI_REVISION_LEGACY(rev) ((rev) & 0x10) 25 26 // -------------------------------- 27 // Control register (section 7.1.2) 28 // -------------------------------- 29 30 #define OHCI_CONTROL 0x04 31 #define OHCI_CONTROL_BULK_SERVICE_RATIO_MASK 0x00000003 32 #define OHCI_CONTROL_BULK_RATIO_1_1 0x00000000 33 #define OHCI_CONTROL_BULK_RATIO_1_2 0x00000001 34 #define OHCI_CONTROL_BULK_RATIO_1_3 0x00000002 35 #define OHCI_CONTROL_BULK_RATIO_1_4 0x00000003 36 #define OHCI_PERIODIC_LIST_ENABLE 0x00000004 37 #define OHCI_ISOCHRONOUS_ENABLE 0x00000008 38 #define OHCI_CONTROL_LIST_ENABLE 0x00000010 39 #define OHCI_BULK_LIST_ENABLE 0x00000020 40 #define OHCI_HC_FUNCTIONAL_STATE_MASK 0x000000c0 41 #define OHCI_HC_FUNCTIONAL_STATE_RESET 0x00000000 42 #define OHCI_HC_FUNCTIONAL_STATE_RESUME 0x00000040 43 #define OHCI_HC_FUNCTIONAL_STATE_OPERATIONAL 0x00000080 44 #define OHCI_HC_FUNCTIONAL_STATE_SUSPEND 0x000000c0 45 #define OHCI_INTERRUPT_ROUTING 0x00000100 46 #define OHCI_REMOTE_WAKEUP_CONNECTED 0x00000200 47 #define OHCI_REMORE_WAKEUP_ENABLED 0x00000400 48 49 // -------------------------------- 50 // Command status register (section 7.1.3) 51 // -------------------------------- 52 53 #define OHCI_COMMAND_STATUS 0x08 54 #define OHCI_HOST_CONTROLLER_RESET 0x00000001 55 #define OHCI_CONTROL_LIST_FILLED 0x00000002 56 #define OHCI_BULK_LIST_FILLED 0x00000004 57 #define OHCI_OWNERSHIP_CHANGE_REQUEST 0x00000008 58 #define OHCI_SCHEDULING_OVERRUN_COUNT_MASK 0x00030000 59 60 // -------------------------------- 61 // Interrupt status register (section 7.1.4) 62 // -------------------------------- 63 64 #define OHCI_INTERRUPT_STATUS 0x0c 65 #define OHCI_SCHEDULING_OVERRUN 0x00000001 66 #define OHCI_WRITEBACK_DONE_HEAD 0x00000002 67 #define OHCI_START_OF_FRAME 0x00000004 68 #define OHCI_RESUME_DETECTED 0x00000008 69 #define OHCI_UNRECOVERABLE_ERROR 0x00000010 70 #define OHCI_FRAME_NUMBER_OVERFLOW 0x00000020 71 #define OHCI_ROOT_HUB_STATUS_CHANGE 0x00000040 72 #define OHCI_OWNERSHIP_CHANGE 0x40000000 73 #define OHCI_MASTER_INTERRUPT_ENABLE 0x80000000 74 75 // -------------------------------- 76 // Interupt enable register (section 7.1.5) 77 // -------------------------------- 78 79 #define OHCI_INTERRUPT_ENABLE 0x10 80 81 // -------------------------------- 82 // Interupt disable register (section 7.1.6) 83 // -------------------------------- 84 85 #define OHCI_INTERRUPT_DISABLE 0x14 86 87 // ------------------------------------- 88 // Memory Pointer Partition (section 7.2) 89 // ------------------------------------- 90 91 // -------------------------------- 92 // HCCA register (section 7.2.1) 93 // -------------------------------- 94 95 #define OHCI_HCCA 0x18 96 97 // -------------------------------- 98 // Period current ED register (section 7.2.2) 99 // -------------------------------- 100 101 #define OHCI_PERIOD_CURRENT_ED 0x1c 102 103 // -------------------------------- 104 // Control head ED register (section 7.2.3) 105 // -------------------------------- 106 107 #define OHCI_CONTROL_HEAD_ED 0x20 108 109 // -------------------------------- 110 // Current control ED register (section 7.2.4) 111 // -------------------------------- 112 113 #define OHCI_CONTROL_CURRENT_ED 0x24 114 115 // -------------------------------- 116 // Bulk head ED register (section 7.2.5) 117 // -------------------------------- 118 119 #define OHCI_BULK_HEAD_ED 0x28 120 121 // -------------------------------- 122 // Current bulk ED register (section 7.2.6) 123 // -------------------------------- 124 125 #define OHCI_BULK_CURRENT_ED 0x2c 126 127 // -------------------------------- 128 // Done head register (section 7.2.7) 129 // -------------------------------- 130 131 #define OHCI_DONE_HEAD 0x30 132 133 // -------------------------------- 134 // Frame Counter partition (section 7.3) 135 // -------------------------------- 136 137 // -------------------------------- 138 // Frame interval register (section 7.3.1) 139 // -------------------------------- 140 141 #define OHCI_FRAME_INTERVAL 0x34 142 #define OHCI_GET_INTERVAL_VALUE(s) ((s) & 0x3fff) 143 #define OHCI_GET_FS_LARGEST_DATA_PACKET(s) (((s) >> 16) & 0x7fff) 144 #define OHCI_FRAME_INTERVAL_TOGGLE 0x80000000 145 146 // -------------------------------- 147 // Frame remaining register (section 7.3.2) 148 // -------------------------------- 149 150 #define OHCI_FRAME_REMAINING 0x38 151 152 // -------------------------------- 153 // Frame number register (section 7.3.3) 154 // -------------------------------- 155 156 #define OHCI_FRAME_NUMBER 0x3c 157 158 // -------------------------------- 159 // Periodic start register (section 7.3.4) 160 // -------------------------------- 161 162 #define OHCI_PERIODIC_START 0x40 163 164 // -------------------------------- 165 // Low Speed (LS) treshold register (section 7.3.5) 166 // -------------------------------- 167 168 #define OHCI_LOW_SPEED_THRESHOLD 0x44 169 170 // -------------------------------- 171 // Root Hub Partition (section 7.4) 172 // -------------------------------- 173 174 // -------------------------------- 175 // Root Hub Descriptor A register (section 7.4.1) 176 // -------------------------------- 177 178 #define OHCI_RH_DESCRIPTOR_A 0x48 179 #define OHCI_RH_GET_PORT_COUNT(s) ((s) & 0xff) 180 #define OHCI_RH_POWER_SWITCHING_MODE 0x0100 181 #define OHCI_RH_NO_POWER_SWITCHING 0x0200 182 #define OHCI_RH_DEVICE_TYPE 0x0400 183 #define OHCI_RH_OVER_CURRENT_PROTECTION_MODE 0x0800 184 #define OHCI_RH_NO_OVER_CURRENT_PROTECTION 0x1000 185 #define OHCI_RH_GET_POWER_ON_TO_POWER_GOOD_TIME(s) ((s) >> 24) 186 187 // -------------------------------- 188 // Root Hub Descriptor B register (section 7.4.2) 189 // -------------------------------- 190 191 #define OHCI_RH_DESCRIPTOR_B 0x4c 192 193 // -------------------------------- 194 // Root Hub status register (section 7.4.3) 195 // -------------------------------- 196 197 #define OHCI_RH_STATUS 0x50 198 #define OHCI_RH_LOCAL_POWER_STATUS 0x00000001 199 #define OHCI_RH_OVER_CURRENT_INDICATOR 0x00000002 200 #define OHCI_RH_DEVICE_REMOTE_WAKEUP_ENABLE 0x00008000 201 #define OHCI_RH_LOCAL_POWER_STATUS_CHANGE 0x00010000 202 #define OHCI_RH_OVER_CURRENT_INDICATOR_CHANGE 0x00020000 203 #define OHCI_RH_CLEAR_REMOTE_WAKEUP_ENABLE 0x80000000 204 205 // -------------------------------- 206 // Root Hub port status (n) register (section 7.4.4) 207 // -------------------------------- 208 209 #define OHCI_RH_PORT_STATUS(n) (0x50 + (n) * 4) // 1 based indexing 210 #define OHCI_RH_PORTSTATUS_CCS 0x00000001 // Current Connection Status 211 #define OHCI_RH_PORTSTATUS_PES 0x00000002 // Port Enable Status 212 #define OHCI_RH_PORTSTATUS_PSS 0x00000004 // Port Suspend Status 213 #define OHCI_RH_PORTSTATUS_POCI 0x00000008 // Port Overcurrent Indicator 214 #define OHCI_RH_PORTSTATUS_PRS 0x00000010 // Port Reset Status 215 #define OHCI_RH_PORTSTATUS_PPS 0x00000100 // Port Power Status 216 #define OHCI_RH_PORTSTATUS_LSDA 0x00000200 // Low Speed Device Attached 217 #define OHCI_RH_PORTSTATUS_CSC 0x00010000 // Connection Status Change 218 #define OHCI_RH_PORTSTATUS_PESC 0x00020000 // Port Enable Status Change 219 #define OHCI_RH_PORTSTATUS_PSSC 0x00040000 // Port Suspend Status change 220 #define OHCI_RH_PORTSTATUS_OCIC 0x00080000 // Port Overcurrent Change 221 #define OHCI_RH_PORTSTATUS_PRSC 0x00100000 // Port Reset Status Change 222 223 // -------------------------------- 224 // Enable List 225 // -------------------------------- 226 227 #define OHCI_ENABLE_LIST (OHCI_PERIODIC_LIST_ENABLE \ 228 | OHCI_ISOCHRONOUS_ENABLE \ 229 | OHCI_CONTROL_LIST_ENABLE \ 230 | OHCI_BULK_LIST_ENABLE) 231 232 // -------------------------------- 233 // All interupts 234 // -------------------------------- 235 236 #define OHCI_ALL_INTERRUPTS (OHCI_SCHEDULING_OVERRUN \ 237 | OHCI_WRITEBACK_DONE_HEAD \ 238 | OHCI_START_OF_FRAME \ 239 | OHCI_RESUME_DETECTED \ 240 | OHCI_UNRECOVERABLE_ERROR \ 241 | OHCI_FRAME_NUMBER_OVERFLOW \ 242 | OHCI_ROOT_HUB_STATUS_CHANGE \ 243 | OHCI_OWNERSHIP_CHANGE) 244 245 // -------------------------------- 246 // All normal interupts 247 // -------------------------------- 248 249 #define OHCI_NORMAL_INTERRUPTS (OHCI_SCHEDULING_OVERRUN \ 250 | OHCI_WRITEBACK_DONE_HEAD \ 251 | OHCI_RESUME_DETECTED \ 252 | OHCI_UNRECOVERABLE_ERROR \ 253 | OHCI_ROOT_HUB_STATUS_CHANGE) 254 255 // -------------------------------- 256 // FSMPS 257 // -------------------------------- 258 259 #define OHCI_FSMPS(i) (((i - 210) * 6 / 7) << 16) 260 261 // -------------------------------- 262 // Periodic 263 // -------------------------------- 264 265 #define OHCI_PERIODIC(i) ((i) * 9 / 10) 266 267 // -------------------------------- 268 // OHCI physical address 269 // -------------------------------- 270 271 typedef uint32 ohci_physaddr_t; 272 273 // -------------------------------- 274 // HCCA structure (section 4.4) 275 // -------------------------------- 276 277 #define OHCI_NUMBER_OF_INTERRUPTS 32 278 279 typedef struct ohci_hcca 280 { 281 uint32 hcca_interrupt_table[OHCI_NUMBER_OF_INTERRUPTS]; 282 uint16 hcca_frame_number; 283 uint32 hcca_done_head; 284 uint8 hcca_reserved_for_hc[116]; 285 }; 286 287 #define OHCI_DONE_INTRS 1 288 #define OHCI_HCCA_SIZE 256 289 #define OHCI_HCCA_ALIGN 256 290 #define OHCI_PAGE_SIZE 0x1000 291 #define OHCI_PAGE(x) ((x) &~ 0xfff) 292 #define OHCI_PAGE_OFFSET(x) ((x) & 0xfff) 293 294 // -------------------------------- 295 // Endpoint descriptor structure (section 4.2) 296 // -------------------------------- 297 298 typedef struct ohci_endpoint_descriptor 299 { 300 uint32 flags; 301 uint32 tail_pointer; // Queue tail pointer 302 uint32 head_pointer; // Queue head pointer 303 uint32 next_endpoint; // Next endpoint in the list 304 }; 305 306 #define OHCI_ENDPOINT_ADDRESS_MASK 0x0000007f 307 #define OHCI_ENDPOINT_GET_DEVICE_ADDRESS(s) ((s) & 0x7f) 308 #define OHCI_ENDPOINT_SET_DEVICE_ADDRESS(s) (s) 309 #define OHCI_ENDPOINT_GET_ENDPOINT_NUMBER(s) (((s) >> 7) & 0xf) 310 #define OHCI_ENDPOINT_SET_ENDPOINT_NUMBER(s) ((s) << 7) 311 #define OHCI_ENDPOINT_DIRECTION_MASK 0x00001800 312 #define OHCI_ENDPOINT_DIRECTION_DESCRIPTOR 0x00000000 313 #define OHCI_ENDPOINT_DIRECTION_OUT 0x00000800 314 #define OHCI_ENDPOINT_DIRECTION_IN 0x00001000 315 #define OHCI_ENDPOINT_SPEED 0x00002000 316 #define OHCI_ENDPOINT_SKIP 0x00004000 317 #define OHCI_ENDPOINT_GENERAL_FORMAT 0x00000000 318 #define OHCI_ENDPOINT_ISOCHRONOUS_FORMAT 0x00008000 319 #define OHCI_ENDPOINT_MAX_PACKET_SIZE_MASK (0x7ff << 16) 320 #define OHCI_ENDPOINT_GET_MAX_PACKET_SIZE(s) (((s) >> 16) & 0x07ff) 321 #define OHCI_ENDPOINT_SET_MAX_PACKET_SIZE(s) ((s) << 16) 322 #define OHCI_ENDPOINT_HALTED 0x00000001 323 #define OHCI_ENDPOINT_TOGGLE_CARRY 0x00000002 324 #define OHCI_ENDPOINT_HEAD_MASK 0xfffffffc 325 326 327 // -------------------------------- 328 // General transfer descriptor structure (section 4.3.1) 329 // -------------------------------- 330 331 typedef struct ohci_general_transfer_descriptor 332 { 333 uint32 flags; 334 uint32 buffer_phy; // Physical buffer pointer 335 uint32 next_descriptor; // Next transfer descriptor 336 uint32 last_byte_address; // Physical buffer end 337 }; 338 339 #define OHCI_BUFFER_ROUNDING 0x00040000 340 #define OHCI_TD_DIRECTION_PID_MASK 0x00180000 341 #define OHCI_TD_DIRECTION_PID_SETUP 0x00000000 342 #define OHCI_TD_DIRECTION_PID_OUT 0x00080000 343 #define OHCI_TD_DIRECTION_PID_IN 0x00100000 344 #define OHCI_TD_GET_DELAY_INTERRUPT(x) (((x) >> 21) & 7) 345 #define OHCI_TD_SET_DELAY_INTERRUPT(x) ((x) << 21) 346 #define OHCI_TD_NO_INTERRUPT 0x00e00000 347 #define OHCI_TD_INTERRUPT_MASK 0x00e00000 348 #define OHCI_TD_TOGGLE_CARRY 0x00000000 349 #define OHCI_TD_TOGGLE_0 0x02000000 350 #define OHCI_TD_TOGGLE_1 0x03000000 351 #define OHCI_TD_TOGGLE_MASK 0x03000000 352 #define OHCI_TD_GET_ERROR_COUNT(x) (((x) >> 26) & 3) 353 #define OHCI_TD_GET_CONDITION_CODE(x) ((x) >> 28) 354 #define OHCI_TD_NO_CONDITION_CODE 0xf0000000 355 356 #define OHCI_GENERAL_TD_ALIGN 16 357 358 // -------------------------------- 359 // Isonchronous transfer descriptor structure (section 4.3.2) 360 // -------------------------------- 361 362 #define OHCI_ITD_NOFFSET 8 363 typedef struct ohci_isochronous_transfer_descriptor 364 { 365 uint32 flags; 366 uint32 buffer_page_byte_0; // Physical page number of byte 0 367 uint32 next_descriptor; // Next isochronous transfer descriptor 368 uint32 last_byte_address; // Physical buffer end 369 uint16 offset[OHCI_ITD_NOFFSET]; // Buffer offsets 370 }; 371 372 #define OHCI_ITD_GET_STARTING_FRAME(x) ((x) & 0x0000ffff) 373 #define OHCI_ITD_SET_STARTING_FRAME(x) ((x) & 0xffff) 374 #define OHCI_ITD_GET_DELAY_INTERRUPT(x) (((x) >> 21) & 7) 375 #define OHCI_ITD_SET_DELAY_INTERRUPT(x) ((x) << 21) 376 #define OHCI_ITD_NO_INTERRUPT 0x00e00000 377 #define OHCI_ITD_GET_FRAME_COUNT(x) ((((x) >> 24) & 7) + 1) 378 #define OHCI_ITD_SET_FRAME_COUNT(x) (((x) - 1) << 24) 379 #define OHCI_ITD_GET_CONDITION_CODE(x) ((x) >> 28) 380 #define OHCI_ITD_NO_CONDITION_CODE 0xf0000000 381 382 // TO FIX 383 #define itd_pswn itd_offset // Packet Status Word 384 #define OHCI_ITD_PAGE_SELECT 0x00001000 385 #define OHCI_ITD_MK_OFFS(len) (0xe000 | ((len) & 0x1fff)) 386 #define OHCI_ITD_GET_BUFFER_LENGTH(x) ((x) & 0xfff) 387 #define OHCI_ITD_GET_BUFFER_CONDITION_CODE(x) ((x) >> 12) 388 389 #define OHCI_ISOCHRONOUS_TD_ALIGN 32 390 391 // -------------------------------- 392 // Completion Codes (section 4.3.3) 393 // -------------------------------- 394 395 #define OHCI_NO_ERROR 0 396 #define OHCI_CRC 1 397 #define OHCI_BIT_STUFFING 2 398 #define OHCI_DATA_TOGGLE_MISMATCH 3 399 #define OHCI_STALL 4 400 #define OHCI_DEVICE_NOT_RESPONDING 5 401 #define OHCI_PID_CHECK_FAILURE 6 402 #define OHCI_UNEXPECTED_PID 7 403 #define OHCI_DATA_OVERRUN 8 404 #define OHCI_DATA_UNDERRUN 9 405 #define OHCI_BUFFER_OVERRUN 12 406 #define OHCI_BUFFER_UNDERRUN 13 407 #define OHCI_NOT_ACCESSED 15 408 409 // -------------------------------- 410 // Some delay needed when changing 411 // certain registers. 412 // -------------------------------- 413 414 #define OHCI_ENABLE_POWER_DELAY 5000 415 #define OHCI_READ_DESC_DELAY 5000 416 417 #endif // OHCI_HARD_H 418