1 //------------------------------------------------------------------------------ 2 // Copyright (c) 2005, Jan-Rixt Van Hoye 3 // 4 // Permission is hereby granted, free of charge, to any person obtaining a 5 // copy of this software and associated documentation files (the "Software"), 6 // to deal in the Software without restriction, including without limitation 7 // the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 // and/or sell copies of the Software, and to permit persons to whom the 9 // Software is furnished to do so, subject to the following conditions: 10 // 11 // The above copyright notice and this permission notice shall be included in 12 // all copies or substantial portions of the Software. 13 // 14 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17 // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19 // FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20 // DEALINGS IN THE SOFTWARE. 21 //------------------------------------------------------------------------------ 22 23 #ifndef OHCI_HARD_H 24 #define OHCI_HARD_H 25 26 // -------------------------------- 27 // The OHCI registers 28 // -------------------------------- 29 30 // -------------------------------- 31 // Revision register (section 7.1.1) 32 // -------------------------------- 33 34 #define OHCI_REVISION 0x00 // OHCI revision 35 #define OHCI_REV_LO(rev) ((rev)&0x0f) 36 #define OHCI_REV_HI(rev) (((rev)>>4)&0x03) 37 #define OHCI_REV_LEGACY(rev) ((rev) & 0x10) 38 39 // -------------------------------- 40 // Control register (section 7.1.2) 41 // -------------------------------- 42 43 #define OHCI_CONTROL 0x04 44 #define OHCI_CBSR_MASK 0x00000003 // Control-Bulk Service Ratio 45 #define OHCI_RATIO_1_1 0x00000000 46 #define OHCI_RATIO_1_2 0x00000001 47 #define OHCI_RATIO_1_3 0x00000002 48 #define OHCI_RATIO_1_4 0x00000003 49 #define OHCI_PLE 0x00000004 // Periodic List Enable 50 #define OHCI_IE 0x00000008 // Isochronous Enable 51 #define OHCI_CLE 0x00000010 // Control List Enable 52 #define OHCI_BLE 0x00000020 // Bulk List Enable 53 #define OHCI_HCFS_MASK 0x000000c0 // HostControllerFunctionalState 54 #define OHCI_HCFS_RESET 0x00000000 55 #define OHCI_HCFS_RESUME 0x00000040 56 #define OHCI_HCFS_OPERATIONAL 0x00000080 57 #define OHCI_HCFS_SUSPEND 0x000000c0 58 #define OHCI_IR 0x00000100 // Interrupt Routing 59 #define OHCI_RWC 0x00000200 // Remote Wakeup Connected 60 #define OHCI_RWE 0x00000400 // Remote Wakeup Enabled 61 62 // -------------------------------- 63 // Command status register (section 7.1.3) 64 // -------------------------------- 65 66 #define OHCI_COMMAND_STATUS 0x08 67 #define OHCI_HCR 0x00000001 // Host Controller Reset 68 #define OHCI_CLF 0x00000002 // Control List Filled 69 #define OHCI_BLF 0x00000004 // Bulk List Filled 70 #define OHCI_OCR 0x00000008 // Ownership Change Request 71 #define OHCI_SOC_MASK 0x00030000 // Scheduling Overrun Count 72 73 // -------------------------------- 74 // Interupt status register (section 7.1.4) 75 // -------------------------------- 76 77 #define OHCI_INTERRUPT_STATUS 0x0c 78 #define OHCI_SO 0x00000001 // Scheduling Overrun 79 #define OHCI_WDH 0x00000002 // Writeback Done Head 80 #define OHCI_SF 0x00000004 // Start of Frame 81 #define OHCI_RD 0x00000008 // Resume Detected 82 #define OHCI_UE 0x00000010 // Unrecoverable Error 83 #define OHCI_FNO 0x00000020 // Frame Number Overflow 84 #define OHCI_RHSC 0x00000040 // Root Hub Status Change 85 #define OHCI_OC 0x40000000 // Ownership Change 86 #define OHCI_MIE 0x80000000 // Master Interrupt Enable 87 88 // -------------------------------- 89 // Interupt enable register (section 7.1.5) 90 // -------------------------------- 91 92 #define OHCI_INTERRUPT_ENABLE 0x10 93 94 // -------------------------------- 95 // Interupt disable register (section 7.1.6) 96 // -------------------------------- 97 98 #define OHCI_INTERRUPT_DISABLE 0x14 99 100 // ------------------------------------- 101 // Memory Pointer Partition (section 7.2) 102 // ------------------------------------- 103 104 // -------------------------------- 105 // HCCA register (section 7.2.1) 106 // -------------------------------- 107 108 #define OHCI_HCCA 0x18 109 110 // -------------------------------- 111 // Period current ED register (section 7.2.2) 112 // -------------------------------- 113 114 #define OHCI_PERIOD_CURRENT_ED 0x1c 115 116 // -------------------------------- 117 // Control head ED register (section 7.2.3) 118 // -------------------------------- 119 120 #define OHCI_CONTROL_HEAD_ED 0x20 121 122 // -------------------------------- 123 // Current control ED register (section 7.2.4) 124 // -------------------------------- 125 126 #define OHCI_CONTROL_CURRENT_ED 0x24 127 128 // -------------------------------- 129 // Bulk head ED register (section 7.2.5) 130 // -------------------------------- 131 132 #define OHCI_BULK_HEAD_ED 0x28 133 134 // -------------------------------- 135 // Current bulk ED register (section 7.2.6) 136 // -------------------------------- 137 138 #define OHCI_BULK_CURRENT_ED 0x2c 139 140 // -------------------------------- 141 // Done head register (section 7.2.7) 142 // -------------------------------- 143 144 #define OHCI_DONE_HEAD 0x30 145 146 // -------------------------------- 147 // Frame Counter partition (section 7.3) 148 // -------------------------------- 149 150 // -------------------------------- 151 // Frame interval register (section 7.3.1) 152 // -------------------------------- 153 154 #define OHCI_FM_INTERVAL 0x34 155 #define OHCI_GET_IVAL(s) ((s) & 0x3fff) 156 #define OHCI_GET_FSMPS(s) (((s) >> 16) & 0x7fff) 157 #define OHCI_FIT 0x80000000 158 159 // -------------------------------- 160 // Frame remaining register (section 7.3.2) 161 // -------------------------------- 162 163 #define OHCI_FM_REMAINING 0x38 164 165 // -------------------------------- 166 // Frame number register (section 7.3.3) 167 // -------------------------------- 168 169 #define OHCI_FM_NUMBER 0x3c 170 171 // -------------------------------- 172 // Periodic start register (section 7.3.4) 173 // -------------------------------- 174 175 #define OHCI_PERIODIC_START 0x40 176 177 // -------------------------------- 178 // LS treshold register (section 7.3.5) 179 // -------------------------------- 180 181 #define OHCI_LS_THRESHOLD 0x44 182 183 // -------------------------------- 184 // Root Hub Partition (section 7.4) 185 // -------------------------------- 186 187 // -------------------------------- 188 // Root Hub Descriptor A register (section 7.4.1) 189 // -------------------------------- 190 191 #define OHCI_RH_DESCRIPTOR_A 0x48 192 #define OHCI_GET_PORT_COUNT(s) ((s) & 0xff) 193 #define OHCI_PSM 0x0100 // Power Switching Mode 194 #define OHCI_NPS 0x0200 // No Power Switching 195 #define OHCI_DT 0x0400 // Device Type 196 #define OHCI_OCPM 0x0800 // Overcurrent Protection Mode 197 #define OHCI_NOCP 0x1000 // No Overcurrent Protection 198 #define OHCI_GET_POTPGT(s) ((s) >> 24) 199 200 // -------------------------------- 201 // Root Hub Descriptor B register (section 7.4.2) 202 // -------------------------------- 203 204 #define OHCI_RH_DESCRIPTOR_B 0x4c 205 206 // -------------------------------- 207 // Root Hub status register (section 7.4.3) 208 // -------------------------------- 209 210 #define OHCI_RH_STATUS 0x50 211 #define OHCI_LPS 0x00000001 // Local Power Status 212 #define OHCI_OCI 0x00000002 // OverCurrent Indicator 213 #define OHCI_DRWE 0x00008000 // Device Remote Wakeup Enable 214 #define OHCI_LPSC 0x00010000 // Local Power Status Change 215 #define OHCI_CCIC 0x00020000 // OverCurrent Indicator Change 216 #define OHCI_CRWE 0x80000000 // Clear Remote Wakeup Enable 217 218 // -------------------------------- 219 // Root Hub port status (n) register (section 7.4.4) 220 // -------------------------------- 221 222 #define OHCI_RH_PORT_STATUS(n) (0x50 + (n)*4) // 1 based indexing 223 #define OHCI_PORTSTATUS_CCS 0x00000001 // Current Connection Status 224 #define OHCI_PORTSTATUS_PES 0x00000002 // Port Enable Status 225 #define OHCI_PORTSTATUS_PSS 0x00000004 // Port Suspend Status 226 #define OHCI_PORTSTATUS_POCI 0x00000008 // Port Overcurrent Indicator 227 #define OHCI_PORTSTATUS_PRS 0x00000010 // Port Reset Status 228 #define OHCI_PORTSTATUS_PPS 0x00000100 // Port Power Status 229 #define OHCI_PORTSTATUS_LSDA 0x00000200 // Low Speed Device Attached 230 #define OHCI_PORTSTATUS_CSC 0x00010000 // Connection Status Change 231 #define OHCI_PORTSTATUS_PESC 0x00020000 // Port Enable Status Change 232 #define OHCI_PORTSTATUS_PSSC 0x00040000 // Port Suspend Status change 233 #define OHCI_PORTSTATUS_OCIC 0x00080000 // Port Overcurrent Change 234 #define OHCI_PORTSTATUS_PRSC 0x00100000 // Port Reset Status Change 235 236 // -------------------------------- 237 // ???? 238 // -------------------------------- 239 240 #define OHCI_LES (OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE) 241 242 // -------------------------------- 243 // All interupts 244 // -------------------------------- 245 246 #define OHCI_ALL_INTRS (OHCI_SO | OHCI_WDH | OHCI_SF | OHCI_RD | OHCI_UE | OHCI_FNO | OHCI_RHSC | OHCI_OC) 247 248 // -------------------------------- 249 // All normal interupts 250 // -------------------------------- 251 252 #define OHCI_NORMAL_INTRS (OHCI_SO | OHCI_WDH | OHCI_RD | OHCI_UE | OHCI_RHSC) 253 254 // -------------------------------- 255 // FSMPS 256 // -------------------------------- 257 258 #define OHCI_FSMPS(i) (((i-210)*6/7) << 16) 259 260 // -------------------------------- 261 // Periodic 262 // -------------------------------- 263 264 #define OHCI_PERIODIC(i) ((i)*9/10) 265 266 // -------------------------------- 267 // OHCI physical address 268 // -------------------------------- 269 270 typedef uint32 ohci_physaddr_t; 271 272 // -------------------------------- 273 // HCCA structure (section 4.4) 274 // -------------------------------- 275 276 #define OHCI_NO_INTRS 32 277 278 struct ohci_hcca 279 { 280 addr_t hcca_interrupt_table[OHCI_NO_INTRS]; 281 uint32 hcca_frame_number; 282 addr_t hcca_done_head; 283 uint8 hcca_reserved_for_hc[116]; 284 }; 285 286 #define OHCI_DONE_INTRS 1 287 #define OHCI_HCCA_SIZE 256 288 #define OHCI_HCCA_ALIGN 256 289 #define OHCI_PAGE_SIZE 0x1000 290 #define OHCI_PAGE(x) ((x) &~ 0xfff) 291 #define OHCI_PAGE_OFFSET(x) ((x) & 0xfff) 292 293 // -------------------------------- 294 // Endpoint descriptor structure (section 4.2) 295 // -------------------------------- 296 297 typedef struct ohci_endpoint_descriptor 298 { 299 uint32 flags; 300 addr_t tailp; // Queue tail pointer 301 addr_t headp; // Queue head pointer 302 addr_t next_endpoint; // Next endpoint in the list 303 }; 304 305 #define OHCI_ENDPOINT_GET_FA(s) ((s) & 0x7f) 306 #define OHCI_ENDPOINT_ADDRMASK 0x0000007f 307 #define OHCI_ENDPOINT_SET_FA(s) (s) 308 #define OHCI_ENDPOINT_GET_EN(s) (((s) >> 7) & 0xf) 309 #define OHCI_ENDPOINT_SET_EN(s) ((s) << 7) 310 #define OHCI_ENDPOINT_DIR_MASK 0x00001800 311 #define OHCI_ENDPOINT_DIR_TD 0x00000000 312 #define OHCI_ENDPOINT_DIR_OUT 0x00000800 313 #define OHCI_ENDPOINT_DIR_IN 0x00001000 314 #define OHCI_ENDPOINT_SPEED 0x00002000 315 #define OHCI_ENDPOINT_SKIP 0x00004000 316 #define OHCI_ENDPOINT_FORMAT_GEN 0x00000000 317 #define OHCI_ENDPOINT_FORMAT_ISO 0x00008000 318 #define OHCI_ENDPOINT_GET_MAXP(s) (((s) >> 16) & 0x07ff) 319 #define OHCI_ENDPOINT_SET_MAXP(s) ((s) << 16) 320 #define OHCI_ENDPOINT_MAXPMASK (0x7ff << 16) 321 322 #define OHCI_HALTED 0x00000001 323 #define OHCI_TOGGLECARRY 0x00000002 324 #define OHCI_HEADMASK 0xfffffffc 325 326 327 // -------------------------------- 328 // General transfer descriptor structure (section 4.3.1) 329 // -------------------------------- 330 331 typedef struct ohci_transfer_descriptor 332 { 333 uint32 flags; 334 addr_t td_cbp; // Current Buffer Pointer 335 addr_t td_nexttd; // Next Transfer Descriptor 336 addr_t td_be; // Buffer End 337 } ; 338 339 #define OHCI_TD_R 0x00040000 // Buffer Rounding 340 #define OHCI_TD_DP_MASK 0x00180000 // Direction / PID 341 #define OHCI_TD_SETUP 0x00000000 342 #define OHCI_TD_OUT 0x00080000 343 #define OHCI_TD_IN 0x00100000 344 #define OHCI_TD_GET_DI(x) (((x) >> 21) & 7) // Delay Interrupt 345 #define OHCI_TD_SET_DI(x) ((x) << 21) 346 #define OHCI_TD_NOINTR 0x00e00000 347 #define OHCI_TD_INTR_MASK 0x00e00000 348 #define OHCI_TD_TOGGLE_CARRY 0x00000000 349 #define OHCI_TD_TOGGLE_0 0x02000000 350 #define OHCI_TD_TOGGLE_1 0x03000000 351 #define OHCI_TD_TOGGLE_MASK 0x03000000 352 #define OHCI_TD_GET_EC(x) (((x) >> 26) & 3) // Error Count 353 #define OHCI_TD_GET_CC(x) ((x) >> 28) // Condition Code 354 #define OHCI_TD_NOCC 0xf0000000 355 356 #define OHCI_TD_ALIGN 16 357 358 // -------------------------------- 359 // Isonchronous transfer descriptor structure (section 4.3.2) 360 // -------------------------------- 361 362 #define OHCI_ITD_NOFFSET 8 363 typedef struct hc_itransfer_descriptor 364 { 365 uint32 itd_flags; 366 addr_t itd_bp0; // Buffer Page 0 367 addr_t itd_nextitd; // Next Isochronous Transfer Descriptor 368 addr_t itd_be; // Buffer End 369 uint16 itd_offset[OHCI_ITD_NOFFSET]; // Buffer offsets 370 371 }; 372 373 #define OHCI_ITD_GET_SF(x) ((x) & 0x0000ffff) 374 #define OHCI_ITD_SET_SF(x) ((x) & 0xffff) 375 #define OHCI_ITD_GET_DI(x) (((x) >> 21) & 7) // Delay Interrupt 376 #define OHCI_ITD_SET_DI(x) ((x) << 21) 377 #define OHCI_ITD_NOINTR 0x00e00000 378 #define OHCI_ITD_GET_FC(x) ((((x) >> 24) & 7)+1) // Frame Count 379 #define OHCI_ITD_SET_FC(x) (((x)-1) << 24) 380 #define OHCI_ITD_GET_CC(x) ((x) >> 28) // Condition Code 381 #define OHCI_ITD_NOCC 0xf0000000 382 383 #define itd_pswn itd_offset // Packet Status Word 384 #define OHCI_ITD_PAGE_SELECT 0x00001000 385 #define OHCI_ITD_MK_OFFS(len) (0xe000 | ((len) & 0x1fff)) 386 #define OHCI_ITD_PSW_LENGTH(x) ((x) & 0xfff) // Transfer length 387 #define OHCI_ITD_PSW_GET_CC(x) ((x) >> 12) // Condition Code 388 389 #define OHCI_ITD_ALIGN 32 390 391 // -------------------------------- 392 // Completion Codes (section 4.3.3) 393 // -------------------------------- 394 395 #define OHCI_CC_NO_ERROR 0 396 #define OHCI_CC_CRC 1 397 #define OHCI_CC_BIT_STUFFING 2 398 #define OHCI_CC_DATA_TOGGLE_MISMATCH 3 399 #define OHCI_CC_STALL 4 400 #define OHCI_CC_DEVICE_NOT_RESPONDING 5 401 #define OHCI_CC_PID_CHECK_FAILURE 6 402 #define OHCI_CC_UNEXPECTED_PID 7 403 #define OHCI_CC_DATA_OVERRUN 8 404 #define OHCI_CC_DATA_UNDERRUN 9 405 #define OHCI_CC_BUFFER_OVERRUN 12 406 #define OHCI_CC_BUFFER_UNDERRUN 13 407 #define OHCI_CC_NOT_ACCESSED 15 408 409 // -------------------------------- 410 // Some delay needed when changing 411 // certain registers. 412 // -------------------------------- 413 414 #define OHCI_ENABLE_POWER_DELAY 5 415 #define OHCI_READ_DESC_DELAY 5 416 417 #endif // OHCI_HARD_H 418