1 /* 2 * Copyright 2006, Haiku Inc. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Michael Lotz <mmlr@mlotz.ch> 7 */ 8 9 #ifndef EHCI_HARDWARE_H 10 #define EHCI_HARDWARE_H 11 12 // Host Controller Capability Registers (EHCI Spec 2.2) 13 #define EHCI_CAPLENGTH 0x00 // Capability Register Length 14 #define EHCI_HCIVERSION 0x02 // Interface Version Number 15 #define EHCI_HCSPARAMS 0x04 // Structural Parameters 16 #define EHCI_HCCPARAMS 0x08 // Capability Parameters 17 #define EHCI_HCSP_PORTROUTE 0x0c // Companion Port Route Description 18 19 20 // Host Controller Operational Registers (EHCI Spec 2.3) 21 #define EHCI_USBCMD 0x00 // USB Command 22 #define EHCI_USBSTS 0x04 // USB Status 23 #define EHCI_USBINTR 0x08 // USB Interrupt Enable 24 #define EHCI_FRINDEX 0x0c // USB Frame Index 25 #define EHCI_CTRDSSEGMENT 0x10 // 4GB Segment Selector 26 #define EHCI_PERIODICLISTBASE 0x14 // Frame List Base Address 27 #define EHCI_ASYNCLISTADDR 0x18 // Next Asynchronous List Address 28 #define EHCI_CONFIGFLAG 0x40 // Configured Flag Register 29 #define EHCI_PORTSC 0x44 // Port Status/Control 30 31 32 // USB Command Register (EHCI Spec 2.3.1) 33 #define EHCI_USBCMD_ITC_SHIFT 16 // Interrupt Threshold Control 34 #define EHCI_USBCMD_ITC_MASK 0xff 35 #define EHCI_USBCMD_ASPME (1 << 11) // Async Schedule Park Mode Enable 36 #define EHCI_USBCMD_ASPMC_SHIFT 8 // Async Schedule Park Mode Count 37 #define EHCI_USBCMD_ASPMC_MASK 0x03 38 #define EHCI_USBCMD_LHCRESET (1 << 7) // Light Host Controller Reset 39 #define EHCI_USBCMD_INTONAAD (1 << 6) // Interrupt on Async Advance Dorbell 40 #define EHCI_USBCMD_ASENABLE (1 << 5) // Asynchronous Schedule Enable 41 #define EHCI_USBCMD_PSENABLE (1 << 4) // Periodic Schedule Enable 42 #define EHCI_USBCMD_FLS_SHIFT 2 // Frame List Size 43 #define EHCI_USBCMD_FLS_MASK 0x03 44 #define EHCI_USBCMD_HCRESET (1 << 1) // Host Controller Reset 45 #define EHCI_USBCMD_RUNSTOP (1 << 0) // Run/Stop 46 47 48 // USB Status Register (EHCI Spec 2.3.2) 49 #define EHCI_USBSTS_ASSTATUS (1 << 15) // Asynchronous Schedule Status 50 #define EHCI_USBSTS_PSSTATUS (1 << 14) // Periodic Schedule Status 51 #define EHCI_USBSTS_RECLAMATION (1 << 13) // Reclamation 52 #define EHCI_USBSTS_HCHALTED (1 << 12) // Host Controller Halted 53 #define EHCI_USBSTS_INTONAA (1 << 5) // Interrupt on Async Advance 54 #define EHCI_USBSTS_HOSTSYSERR (1 << 4) // Host System Error 55 #define EHCI_USBSTS_FLROLLOVER (1 << 3) // Frame List Rollover 56 #define EHCI_USBSTS_PORTCHANGE (1 << 2) // Port Change Detected 57 #define EHCI_USBSTS_USBERRINT (1 << 1) // USB Error Interrupt 58 #define EHCI_USBSTS_USBINT (1 << 0) // USB Interrupt 59 #define EHCI_USBSTS_INTMASK 0x3f 60 61 62 // USB Interrupt Enable Register (EHCI Spec 2.3.3) 63 #define EHCI_USBINTR_INTONAA (1 << 5) // Interrupt on Async Advance Enable 64 #define EHCI_USBINTR_HOSTSYSERR (1 << 4) // Host System Error Enable 65 #define EHCI_USBINTR_FLROLLOVER (1 << 3) // Frame List Rollover Enable 66 #define EHCI_USBINTR_PORTCHANGE (1 << 2) // Port Change Interrupt Enable 67 #define EHCI_USBINTR_USBERRINT (1 << 1) // USB Error Interrupt Enable 68 #define EHCI_USBINTR_USBINT (1 << 0) // USB Interrupt Enable 69 70 71 // Configure Flag Register (EHCI Spec 2.3.8) 72 #define EHCI_CONFIGFLAG_FLAG (1 << 0) // Configure Flag 73 74 75 // Port Status and Control (EHCI Spec 2.3.9) 76 #define EHCI_PORTSC_WAKEOVERCUR (1 << 22) // Wake on Over-Current Enable 77 #define EHCI_PORTSC_WAKEDISCON (1 << 21) // Wake on Disconnect Enable 78 #define EHCI_PORTSC_WAKECONNECT (1 << 20) // Wake on Connect Enable 79 #define EHCI_PORTSC_PTC_SHIFT 16 // Port Test Control 80 #define EHCI_PORTSC_PTC_MASK 0x07 81 #define EHCI_PORTSC_PIC_SHIFT 14 // Port Indicator Control 82 #define EHCI_PORTSC_PIC_MASK 0x03 83 #define EHCI_PORTSC_PORTOWNER (1 << 13) // Port Owner 84 #define EHCI_PORTSC_PORTPOWER (1 << 12) // Port Power 85 #define EHCI_PORTSC_DPLUS (1 << 11) // Logical Level of D+ 86 #define EHCI_PORTSC_DMINUS (1 << 10) // Logical Level of D- 87 #define EHCI_PORTSC_PORTRESET (1 << 8) // Port Reset 88 #define EHCI_PORTSC_SUSPEND (1 << 7) // Suspend 89 #define EHCI_PORTSC_FORCERESUME (1 << 6) // Force Port Resume 90 #define EHCI_PORTSC_OCCHANGE (1 << 5) // Over-Current Change 91 #define EHCI_PORTSC_OCACTIVE (1 << 4) // Over-Current Active 92 #define EHCI_PORTSC_ENABLECHANGE (1 << 3) // Port Enable/Disable Change 93 #define EHCI_PORTSC_ENABLE (1 << 2) // Port Enabled/Disabled 94 #define EHCI_PORTSC_CONNCHANGE (1 << 1) // Connect Status Change 95 #define EHCI_PORTSC_CONNSTATUS (1 << 0) // Current Connect Status 96 97 #define EHCI_PORTSC_DATAMASK 0xffffffd5 98 99 100 // Extended Capabilities 101 #define EHCI_ECP_SHIFT 8 // Extended Capability Pointer 102 #define EHCI_ECP_MASK 0xff 103 #define EHCI_LEGSUP_CAPID_MASK 0xff 104 #define EHCI_LEGSUP_CAPID 0x01 105 #define EHCI_LEGSUP_OSOWNED (1 << 24) // OS Owned Semaphore 106 #define EHCI_LEGSUP_BIOSOWNED (1 << 16) // BIOS Owned Semaphore 107 108 109 // Data Structures (EHCI Spec 3) 110 111 // Periodic Frame List Element Flags (EHCI Spec 3.1) 112 #define EHCI_PFRAMELIST_TERM (1 << 0) // Terminate 113 #define EHCI_PFRAMELIST_ITD (0 << 1) // Isochronous Transfer Descriptor 114 #define EHCI_PFRAMELIST_QH (1 << 1) // Queue Head 115 #define EHCI_PFRAMELIST_SITD (2 << 1) // Split Transaction Isochronous TD 116 #define EHCI_PFRAMELIST_FSTN (3 << 1) // Frame Span Traversal Node 117 118 119 // ToDo: Isochronous (High-Speed) Transfer Descriptors (iTD, EHCI Spec 3.2) 120 // ToDo: Split Transaction Isochronous Transfer Descriptors (siTD, EHCI Spec 3.3) 121 122 // Queue Element Transfer Descriptors (qTD, EHCI Spec 3.5) 123 typedef struct { 124 // Hardware Part 125 addr_t next_phy; 126 addr_t alt_next_phy; 127 uint32 token; 128 addr_t buffer_phy[5]; 129 addr_t ext_buffer_phy[5]; 130 131 // Software Part 132 addr_t this_phy; 133 void *next_log; 134 void *alt_next_log; 135 size_t buffer_size; 136 void *buffer_log; 137 } ehci_qtd; 138 139 140 #define EHCI_QTD_TERMINATE (1 << 0) 141 #define EHCI_QTD_DATA_TOGGLE (1 << 31) 142 #define EHCI_QTD_BYTES_SHIFT 16 143 #define EHCI_QTD_BYTES_MASK 0x7fff 144 #define EHCI_QTD_IOC (1 << 15) 145 #define EHCI_QTD_CPAGE_SHIFT 12 146 #define EHCI_QTD_CPAGE_MASK 0x07 147 #define EHCI_QTD_ERRCOUNT_SHIFT 10 148 #define EHCI_QTD_ERRCOUNT_MASK 0x03 149 #define EHCI_QTD_PID_SHIFT 8 150 #define EHCI_QTD_PID_MASK 0x03 151 #define EHCI_QTD_PID_OUT 0x00 152 #define EHCI_QTD_PID_IN 0x01 153 #define EHCI_QTD_PID_SETUP 0x02 154 #define EHCI_QTD_STATUS_SHIFT 0 155 #define EHCI_QTD_STATUS_MASK 0x7f 156 #define EHCI_QTD_STATUS_ERRMASK 0x50 157 #define EHCI_QTD_STATUS_ACTIVE (1 << 7) // Active 158 #define EHCI_QTD_STATUS_HALTED (1 << 6) // Halted 159 #define EHCI_QTD_STATUS_BUFFER (1 << 5) // Data Buffer Error 160 #define EHCI_QTD_STATUS_BABBLE (1 << 4) // Babble Detected 161 #define EHCI_QTD_STATUS_TERROR (1 << 3) // Transaction Error 162 #define EHCI_QTD_STATUS_MISSED (1 << 2) // Missed Micro-Frame 163 #define EHCI_QTD_STATUS_SPLIT (1 << 1) // Split Transaction State 164 #define EHCI_QTD_STATUS_PING (1 << 0) // Ping State 165 #define EHCI_QTD_PAGE_MASK 0xfffff000 166 167 168 // Queue Head (QH, EHCI Spec 3.6) 169 typedef struct { 170 // Hardware Part 171 addr_t next_phy; 172 uint32 endpoint_chars; 173 uint32 endpoint_caps; 174 addr_t current_qtd_phy; 175 176 struct { 177 addr_t next_phy; 178 addr_t alt_next_phy; 179 uint32 token; 180 addr_t buffer_phy[5]; 181 addr_t ext_buffer_phy[5]; 182 } overlay; 183 184 // Software Part 185 addr_t this_phy; 186 void *next_log; 187 void *prev_log; 188 void *stray_log; 189 void *element_log; 190 } ehci_qh; 191 192 193 typedef struct { 194 ehci_qh queue_head; 195 uint32 padding[2]; 196 } interrupt_entry; 197 198 199 // Applies to ehci_qh.link_phy 200 #define EHCI_QH_TYPE_ITD (0 << 1) 201 #define EHCI_QH_TYPE_QH (1 << 1) 202 #define EHCI_QH_TYPE_SITD (2 << 1) 203 #define EHCI_QH_TYPE_FSTN (3 << 1) 204 #define EHCI_QH_TERMINATE (1 << 0) 205 206 // Applies to ehci_qh.endpoint_chars 207 #define EHCI_QH_CHARS_RL_SHIFT 28 // NAK Count Reload 208 #define EHCI_QH_CHARS_RL_MASK 0x07 209 #define EHCI_QH_CHARS_CONTROL (1 << 27) // Control Endpoint Flag 210 #define EHCI_QH_CHARS_MPL_SHIFT 16 // Max Packet Length 211 #define EHCI_QH_CHARS_MPL_MASK 0x03ff 212 #define EHCI_QH_CHARS_RECHEAD (1 << 15) // Head of Reclamation List Flag 213 #define EHCI_QH_CHARS_TOGGLE (1 << 14) // Data Toggle Control 214 #define EHCI_QH_CHARS_EPS_FULL (0 << 12) // Endpoint is Full-Speed 215 #define EHCI_QH_CHARS_EPS_LOW (1 << 12) // Endpoint is Low-Speed 216 #define EHCI_QH_CHARS_EPS_HIGH (2 << 12) // Endpoint is High-Speed 217 #define EHCI_QH_CHARS_EPT_SHIFT 8 // Endpoint Number 218 #define EHCI_QH_CHARS_EPT_MASK 0x0f 219 #define EHCI_QH_CHARS_INACTIVE (1 << 7) // Inactive on Next Transaction 220 #define EHCI_QH_CHARS_DEV_SHIFT 0 // Device Address 221 #define EHCI_QH_CHARS_DEV_MASK 0x7f 222 223 224 // Applies to ehci_qh.endpoint_caps 225 #define EHCI_QH_CAPS_MULT_SHIFT 30 // Transactions per Micro-Frame 226 #define EHCI_QH_CAPS_MULT_MASK 0x03 227 #define EHCI_QH_CAPS_PORT_SHIFT 23 // Hub Port (Split-Transaction) 228 #define EHCI_QH_CAPS_PORT_MASK 0x7f 229 #define EHCI_QH_CAPS_HUB_SHIFT 16 // Hub Address (Split-Transaction) 230 #define EHCI_QH_CAPS_HUB_MASK 0x7f 231 #define EHCI_QH_CAPS_SCM_SHIFT 8 // Split Completion Mask 232 #define EHCI_QH_CAPS_SCM_MASK 0xff 233 #define EHCI_QH_CAPS_ISM_SHIFT 0 // Interrupt Schedule Mask 234 #define EHCI_QH_CAPS_ISM_MASK 0xff 235 236 237 // Applies to ehci_qh.overlay[EHCI_QH_OL_*_INDEX] 238 #define EHCI_QH_OL_NAK_INDEX 1 // NAK Counter 239 #define EHCI_QH_OL_NAK_SHIFT 1 240 #define EHCI_QH_OL_NAK_MASK 0x0f 241 #define EHCI_QH_OL_TOGGLE_INDEX 2 // Data Toggle 242 #define EHCI_QH_OL_TOGGLE (1 << 31) 243 #define EHCI_QH_OL_IOC_INDEX 2 // Interrupt on Complete 244 #define EHCI_QH_OL_IOC (1 << 15) 245 #define EHCI_QH_OL_ERRC_INDEX 2 // Error Counter 246 #define EHCI_QH_OL_ERRC_SHIFT 10 247 #define EHCI_QH_OL_ERRC_MASK 0x03 248 #define EHCI_QH_OL_PING_INDEX 2 // Ping State 249 #define EHCI_QH_OL_PING (1 << 0) 250 #define EHCI_QH_OL_CPROG_INDEX 4 // Split-Transaction Complete-Split Progress 251 #define EHCI_QH_OL_CPROG_SHIFT 0 252 #define EHCI_QH_OL_CPROG_MASK 0xff 253 #define EHCI_QH_OL_FTAG_INDEX 5 // Split-Transaction Frame Tag 254 #define EHCI_QH_OL_FTAG_SHIFT 0 255 #define EHCI_QH_OL_FTAG_MASK 0x0f 256 #define EHCI_QH_OL_BYTES_INDEX 5 // Transfered Bytes 257 #define EHCI_QH_OL_BYTES_SHIFT 5 258 #define EHCI_QH_OL_BYTES_MASK 0x7f 259 260 261 // ToDo: Periodic Frame Span Traversal Node (FSTN, EHCI Spec 3.7) 262 263 264 #endif // !EHCI_HARDWARE_H 265