1 /* 2 * Copyright 2007-2009, Marcus Overhagen. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 */ 5 6 #include "ahci_controller.h" 7 #include "util.h" 8 9 #include <algorithm> 10 #include <KernelExport.h> 11 #include <stdio.h> 12 #include <string.h> 13 #include <new> 14 15 #define TRACE(a...) dprintf("ahci: " a) 16 #define FLOW(a...) dprintf("ahci: " a) 17 18 19 AHCIController::AHCIController(device_node *node, 20 pci_device_module_info *pciModule, pci_device *device) 21 : 22 fNode(node), 23 fPCI(pciModule), 24 fPCIDevice(device), 25 fPCIVendorID(0xffff), 26 fPCIDeviceID(0xffff), 27 fFlags(0), 28 fCommandSlotCount(0), 29 fPortCount(0), 30 fPortImplementedMask(0), 31 fIRQ(0), 32 fUseMSI(false), 33 fInstanceCheck(-1) 34 { 35 memset(fPort, 0, sizeof(fPort)); 36 37 ASSERT(sizeof(ahci_port) == 128); 38 ASSERT(sizeof(ahci_hba) == 4352); 39 ASSERT(sizeof(fis) == 256); 40 ASSERT(sizeof(command_list_entry) == 32); 41 ASSERT(sizeof(command_table) == 128); 42 ASSERT(sizeof(prd) == 16); 43 } 44 45 46 AHCIController::~AHCIController() 47 { 48 } 49 50 51 status_t 52 AHCIController::Init() 53 { 54 pci_info pciInfo; 55 fPCI->get_pci_info(fPCIDevice, &pciInfo); 56 57 fPCIVendorID = pciInfo.vendor_id; 58 fPCIDeviceID = pciInfo.device_id; 59 60 TRACE("AHCIController::Init %u:%u:%u vendor %04x, device %04x\n", 61 pciInfo.bus, pciInfo.device, pciInfo.function, fPCIVendorID, fPCIDeviceID); 62 63 // --- Instance check workaround begin 64 char sName[32]; 65 snprintf(sName, sizeof(sName), "ahci-inst-%u-%u-%u", pciInfo.bus, pciInfo.device, pciInfo.function); 66 if (find_port(sName) >= 0) { 67 dprintf("AHCIController::Init ERROR: an instance for object %u:%u:%u already exists\n", 68 pciInfo.bus, pciInfo.device, pciInfo.function); 69 return B_ERROR; 70 } 71 fInstanceCheck = create_port(1, sName); 72 // --- Instance check workaround end 73 74 get_device_info(fPCIVendorID, fPCIDeviceID, NULL, &fFlags); 75 76 uchar capabilityOffset; 77 status_t res = fPCI->find_pci_capability(fPCIDevice, PCI_cap_id_sata, &capabilityOffset); 78 if (res == B_OK) { 79 uint32 satacr0; 80 uint32 satacr1; 81 TRACE("PCI SATA capability found at offset 0x%x\n", capabilityOffset); 82 satacr0 = fPCI->read_pci_config(fPCIDevice, capabilityOffset, 4); 83 satacr1 = fPCI->read_pci_config(fPCIDevice, capabilityOffset + 4, 4); 84 TRACE("satacr0 = 0x%08" B_PRIx32 ", satacr1 = 0x%08" B_PRIx32 "\n", 85 satacr0, satacr1); 86 } 87 88 uint16 pcicmd = fPCI->read_pci_config(fPCIDevice, PCI_command, 2); 89 TRACE("pcicmd old 0x%04x\n", pcicmd); 90 pcicmd &= ~(PCI_command_io | PCI_command_int_disable); 91 pcicmd |= PCI_command_master | PCI_command_memory; 92 TRACE("pcicmd new 0x%04x\n", pcicmd); 93 fPCI->write_pci_config(fPCIDevice, PCI_command, 2, pcicmd); 94 95 if (fPCIVendorID == PCI_VENDOR_JMICRON) { 96 uint32 ctrl = fPCI->read_pci_config(fPCIDevice, PCI_JMICRON_CONTROLLER_CONTROL_1, 4); 97 TRACE("Jmicron controller control 1 old 0x%08" B_PRIx32 "\n", ctrl); 98 ctrl &= ~((1 << 9) | (1 << 12) | (1 << 14)); // disable SFF 8038i emulation 99 ctrl |= (1 << 8) | (1 << 13) | (1 << 15); // enable AHCI controller 100 TRACE("Jmicron controller control 1 new 0x%08" B_PRIx32 "\n", ctrl); 101 fPCI->write_pci_config(fPCIDevice, PCI_JMICRON_CONTROLLER_CONTROL_1, 4, ctrl); 102 } 103 104 fIRQ = pciInfo.u.h0.interrupt_line; 105 if (fPCI->get_msi_count(fPCIDevice) >= 1) { 106 uint8 vector; 107 if (fPCI->configure_msi(fPCIDevice, 1, &vector) == B_OK 108 && fPCI->enable_msi(fPCIDevice) == B_OK) { 109 TRACE("using MSI vector %u\n", vector); 110 fIRQ = vector; 111 fUseMSI = true; 112 } else { 113 TRACE("couldn't use MSI\n"); 114 } 115 } 116 if (fIRQ == 0 || fIRQ == 0xff) { 117 TRACE("Error: PCI IRQ not assigned\n"); 118 return B_ERROR; 119 } 120 121 phys_addr_t addr = pciInfo.u.h0.base_registers[5]; 122 size_t size = pciInfo.u.h0.base_register_sizes[5]; 123 124 TRACE("registers at %#" B_PRIxPHYSADDR ", size %#" B_PRIxSIZE "\n", addr, 125 size); 126 if (addr == 0) { 127 TRACE("PCI base address register 5 not assigned\n"); 128 return B_ERROR; 129 } 130 131 fRegsArea = map_mem((void **)&fRegs, addr, size, B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, 132 "AHCI HBA regs"); 133 if (fRegsArea < B_OK) { 134 TRACE("mapping registers failed\n"); 135 return B_ERROR; 136 } 137 138 // make sure interrupts are disabled 139 fRegs->ghc &= ~GHC_IE; 140 FlushPostedWrites(); 141 142 if (ResetController() < B_OK) { 143 TRACE("controller reset failed\n"); 144 goto err; 145 } 146 147 fCommandSlotCount = 1 + ((fRegs->cap >> CAP_NCS_SHIFT) & CAP_NCS_MASK); 148 fPortCount = 1 + ((fRegs->cap >> CAP_NP_SHIFT) & CAP_NP_MASK); 149 150 fPortImplementedMask = fRegs->pi; 151 // reported mask of implemented ports is sometimes empty 152 if (fPortImplementedMask == 0) { 153 fPortImplementedMask = 0xffffffff >> (32 - fPortCount); 154 TRACE("ports-implemented mask is zero, using 0x%" B_PRIx32 " instead.\n", 155 fPortImplementedMask); 156 } 157 158 // reported number of ports is sometimes too small 159 int highestPort; 160 highestPort = fls(fPortImplementedMask); // 1-based, 1 to 32 161 if (fPortCount < highestPort) { 162 TRACE("reported number of ports is wrong, using %d instead.\n", highestPort); 163 fPortCount = highestPort; 164 } 165 166 TRACE("cap: Interface Speed Support: generation %" B_PRIu32 "\n", 167 (fRegs->cap >> CAP_ISS_SHIFT) & CAP_ISS_MASK); 168 TRACE("cap: Number of Command Slots: %d (raw %#" B_PRIx32 ")\n", 169 fCommandSlotCount, (fRegs->cap >> CAP_NCS_SHIFT) & CAP_NCS_MASK); 170 TRACE("cap: Number of Ports: %d (raw %#" B_PRIx32 ")\n", fPortCount, 171 (fRegs->cap >> CAP_NP_SHIFT) & CAP_NP_MASK); 172 TRACE("cap: Supports Port Multiplier: %s\n", 173 (fRegs->cap & CAP_SPM) ? "yes" : "no"); 174 TRACE("cap: Supports External SATA: %s\n", 175 (fRegs->cap & CAP_SXS) ? "yes" : "no"); 176 TRACE("cap: Enclosure Management Supported: %s\n", 177 (fRegs->cap & CAP_EMS) ? "yes" : "no"); 178 179 TRACE("cap: FIS-based Switching Control: %s\n", 180 (fRegs->cap & CAP_FBSS) ? "yes" : "no"); 181 182 TRACE("cap: Supports Command List Override: %s\n", 183 (fRegs->cap & CAP_SCLO) ? "yes" : "no"); 184 TRACE("cap: Supports Staggered Spin-up: %s\n", 185 (fRegs->cap & CAP_SSS) ? "yes" : "no"); 186 TRACE("cap: Supports Mechanical Presence Switch: %s\n", 187 (fRegs->cap & CAP_SMPS) ? "yes" : "no"); 188 189 TRACE("cap: Supports 64-bit Addressing: %s\n", 190 (fRegs->cap & CAP_S64A) ? "yes" : "no"); 191 TRACE("cap: Supports Native Command Queuing: %s\n", 192 (fRegs->cap & CAP_SNCQ) ? "yes" : "no"); 193 TRACE("cap: Supports SNotification Register: %s\n", 194 (fRegs->cap & CAP_SSNTF) ? "yes" : "no"); 195 TRACE("cap: Supports Command List Override: %s\n", 196 (fRegs->cap & CAP_SCLO) ? "yes" : "no"); 197 198 TRACE("cap: Supports AHCI mode only: %s\n", (fRegs->cap & CAP_SAM) ? "yes" : "no"); 199 200 if (fRegs->vs >= 0x00010200) { 201 TRACE("cap2: DevSleep Entrance from Slumber Only: %s\n", 202 (fRegs->cap2 & CAP2_DESO) ? "yes" : "no"); 203 TRACE("cap2: Supports Aggressive Device Sleep Management: %s\n", 204 (fRegs->cap2 & CAP2_SADM) ? "yes" : "no"); 205 TRACE("cap2: Supports Device Sleep: %s\n", 206 (fRegs->cap2 & CAP2_SDS) ? "yes" : "no"); 207 TRACE("cap2: Automatic Partial to Slumber Transitions: %s\n", 208 (fRegs->cap2 & CAP2_APST) ? "yes" : "no"); 209 TRACE("cap2: NVMHCI Present: %s\n", 210 (fRegs->cap2 & CAP2_NVMP) ? "yes" : "no"); 211 TRACE("cap2: BIOS/OS Handoff: %s\n", 212 (fRegs->cap2 & CAP2_BOH) ? "yes" : "no"); 213 } 214 TRACE("ghc: AHCI Enable: %s\n", (fRegs->ghc & GHC_AE) ? "yes" : "no"); 215 TRACE("Ports Implemented Mask: %#08" B_PRIx32 " Number of Available Ports:" 216 " %d\n", fPortImplementedMask, count_bits_set(fPortImplementedMask)); 217 TRACE("AHCI Version %02" B_PRIx32 "%02" B_PRIx32 ".%02" B_PRIx32 ".%02" 218 B_PRIx32 " Interrupt %u\n", fRegs->vs >> 24, (fRegs->vs >> 16) & 0xff, 219 (fRegs->vs >> 8) & 0xff, fRegs->vs & 0xff, fIRQ); 220 221 // setup interrupt handler 222 if (install_io_interrupt_handler(fIRQ, Interrupt, this, 0) < B_OK) { 223 TRACE("can't install interrupt handler\n"); 224 goto err; 225 } 226 227 for (int i = 0; i < fPortCount; i++) { 228 if (fPortImplementedMask & (1 << i)) { 229 fPort[i] = new (std::nothrow)AHCIPort(this, i); 230 if (!fPort[i]) { 231 TRACE("out of memory creating port %d\n", i); 232 break; 233 } 234 status_t status = fPort[i]->Init1(); 235 if (status < B_OK) { 236 TRACE("init-1 port %d failed\n", i); 237 delete fPort[i]; 238 fPort[i] = NULL; 239 } 240 } 241 } 242 243 // clear any pending interrupts 244 uint32 interruptsPending; 245 interruptsPending = fRegs->is; 246 fRegs->is = interruptsPending; 247 FlushPostedWrites(); 248 249 // enable interrupts 250 fRegs->ghc |= GHC_IE; 251 FlushPostedWrites(); 252 253 for (int i = 0; i < fPortCount; i++) { 254 if (fPort[i]) { 255 status_t status = fPort[i]->Init2(); 256 if (status < B_OK) { 257 TRACE("init-2 port %d failed\n", i); 258 fPort[i]->Uninit(); 259 delete fPort[i]; 260 fPort[i] = NULL; 261 } 262 } 263 } 264 265 266 return B_OK; 267 268 err: 269 delete_area(fRegsArea); 270 return B_ERROR; 271 } 272 273 274 void 275 AHCIController::Uninit() 276 { 277 TRACE("AHCIController::Uninit\n"); 278 279 for (int i = 0; i < fPortCount; i++) { 280 if (fPort[i]) { 281 fPort[i]->Uninit(); 282 delete fPort[i]; 283 } 284 } 285 286 // disable interrupts 287 fRegs->ghc &= ~GHC_IE; 288 FlushPostedWrites(); 289 290 // clear pending interrupts 291 fRegs->is = 0xffffffff; 292 FlushPostedWrites(); 293 294 // well... 295 remove_io_interrupt_handler(fIRQ, Interrupt, this); 296 297 if (fUseMSI) { 298 fPCI->disable_msi(fPCIDevice); 299 fPCI->unconfigure_msi(fPCIDevice); 300 } 301 302 delete_area(fRegsArea); 303 304 // --- Instance check workaround begin 305 delete_port(fInstanceCheck); 306 // --- Instance check workaround end 307 } 308 309 310 status_t 311 AHCIController::ResetController() 312 { 313 uint32 saveCaps = fRegs->cap & (CAP_SMPS | CAP_SSS | CAP_SPM | CAP_EMS | CAP_SXS); 314 uint32 savePI = fRegs->pi; 315 316 // AHCI 1.3: Software may perform an HBA reset prior to initializing the controller 317 // by setting GHC.AE to ‘1’ and then setting GHC.HR to ‘1’ if desired. 318 fRegs->ghc |= GHC_AE; 319 FlushPostedWrites(); 320 fRegs->ghc |= GHC_HR; 321 FlushPostedWrites(); 322 if (wait_until_clear(&fRegs->ghc, GHC_HR, 1000000) < B_OK) 323 return B_TIMED_OUT; 324 325 fRegs->ghc |= GHC_AE; 326 FlushPostedWrites(); 327 fRegs->cap |= saveCaps; 328 fRegs->pi = savePI; 329 FlushPostedWrites(); 330 331 if (fPCIVendorID == PCI_VENDOR_INTEL) { 332 // Intel PCS—Port Control and Status 333 // SATA port enable bits must be set 334 int portCount = std::max(fls(fRegs->pi), 1 + (int)((fRegs->cap >> CAP_NP_SHIFT) & CAP_NP_MASK)); 335 if (portCount > 8) { 336 // TODO: fix this when specification available 337 TRACE("don't know how to enable SATA ports 9 to %d\n", portCount); 338 portCount = 8; 339 } 340 uint16 pcs = fPCI->read_pci_config(fPCIDevice, 0x92, 2); 341 pcs |= (0xff >> (8 - portCount)); 342 fPCI->write_pci_config(fPCIDevice, 0x92, 2, pcs); 343 } 344 return B_OK; 345 } 346 347 348 int32 349 AHCIController::Interrupt(void *data) 350 { 351 AHCIController *self = (AHCIController *)data; 352 uint32 interruptPending = self->fRegs->is & self->fPortImplementedMask; 353 354 if (interruptPending == 0) 355 return B_UNHANDLED_INTERRUPT; 356 357 for (int i = 0; i < self->fPortCount; i++) { 358 if (interruptPending & (1 << i)) { 359 if (self->fPort[i]) { 360 self->fPort[i]->Interrupt(); 361 } else { 362 FLOW("interrupt on non-existent port %d\n", i); 363 } 364 } 365 } 366 367 // clear pending interrupts 368 self->fRegs->is = interruptPending; 369 370 return B_INVOKE_SCHEDULER; 371 } 372 373 374 void 375 AHCIController::ExecuteRequest(scsi_ccb *request) 376 { 377 if (request->target_lun || !fPort[request->target_id]) { 378 request->subsys_status = SCSI_DEV_NOT_THERE; 379 gSCSI->finished(request, 1); 380 return; 381 } 382 383 fPort[request->target_id]->ScsiExecuteRequest(request); 384 } 385 386 387 uchar 388 AHCIController::AbortRequest(scsi_ccb *request) 389 { 390 if (request->target_lun || !fPort[request->target_id]) 391 return SCSI_DEV_NOT_THERE; 392 393 return fPort[request->target_id]->ScsiAbortRequest(request); 394 } 395 396 397 uchar 398 AHCIController::TerminateRequest(scsi_ccb *request) 399 { 400 if (request->target_lun || !fPort[request->target_id]) 401 return SCSI_DEV_NOT_THERE; 402 403 return fPort[request->target_id]->ScsiTerminateRequest(request); 404 } 405 406 407 uchar 408 AHCIController::ResetDevice(uchar targetID, uchar targetLUN) 409 { 410 if (targetLUN || !fPort[targetID]) 411 return SCSI_DEV_NOT_THERE; 412 413 return fPort[targetID]->ScsiResetDevice(); 414 } 415 416 417 void 418 AHCIController::GetRestrictions(uchar targetID, bool *isATAPI, 419 bool *noAutoSense, uint32 *maxBlocks) 420 { 421 if (!fPort[targetID]) 422 return; 423 424 fPort[targetID]->ScsiGetRestrictions(isATAPI, noAutoSense, maxBlocks); 425 } 426