1 /* 2 * Copyright 2007-2009, Marcus Overhagen. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 */ 5 6 #include "ahci_controller.h" 7 #include "util.h" 8 9 #include <algorithm> 10 #include <KernelExport.h> 11 #include <stdio.h> 12 #include <string.h> 13 #include <new> 14 15 #define TRACE(a...) dprintf("ahci: " a) 16 #define FLOW(a...) dprintf("ahci: " a) 17 18 19 AHCIController::AHCIController(device_node *node, 20 pci_device_module_info *pciModule, pci_device *device) 21 : 22 fNode(node), 23 fPCI(pciModule), 24 fPCIDevice(device), 25 fPCIVendorID(0xffff), 26 fPCIDeviceID(0xffff), 27 fFlags(0), 28 fCommandSlotCount(0), 29 fPortCount(0), 30 fPortImplementedMask(0), 31 fIRQ(0), 32 fUseMSI(false), 33 fInstanceCheck(-1) 34 { 35 memset(fPort, 0, sizeof(fPort)); 36 37 ASSERT(sizeof(ahci_port) == 128); 38 ASSERT(sizeof(ahci_hba) == 4352); 39 ASSERT(sizeof(fis) == 256); 40 ASSERT(sizeof(command_list_entry) == 32); 41 ASSERT(sizeof(command_table) == 128); 42 ASSERT(sizeof(prd) == 16); 43 } 44 45 46 AHCIController::~AHCIController() 47 { 48 } 49 50 51 status_t 52 AHCIController::Init() 53 { 54 pci_info pciInfo; 55 fPCI->get_pci_info(fPCIDevice, &pciInfo); 56 57 fPCIVendorID = pciInfo.vendor_id; 58 fPCIDeviceID = pciInfo.device_id; 59 60 TRACE("AHCIController::Init %u:%u:%u vendor %04x, device %04x\n", 61 pciInfo.bus, pciInfo.device, pciInfo.function, fPCIVendorID, fPCIDeviceID); 62 63 // --- Instance check workaround begin 64 char sName[32]; 65 snprintf(sName, sizeof(sName), "ahci-inst-%u-%u-%u", pciInfo.bus, pciInfo.device, pciInfo.function); 66 if (find_port(sName) >= 0) { 67 dprintf("AHCIController::Init ERROR: an instance for object %u:%u:%u already exists\n", 68 pciInfo.bus, pciInfo.device, pciInfo.function); 69 return B_ERROR; 70 } 71 fInstanceCheck = create_port(1, sName); 72 // --- Instance check workaround end 73 74 get_device_info(fPCIVendorID, fPCIDeviceID, NULL, &fFlags); 75 76 uchar capabilityOffset; 77 status_t res = fPCI->find_pci_capability(fPCIDevice, PCI_cap_id_sata, &capabilityOffset); 78 if (res == B_OK) { 79 uint32 satacr0; 80 uint32 satacr1; 81 TRACE("PCI SATA capability found at offset 0x%x\n", capabilityOffset); 82 satacr0 = fPCI->read_pci_config(fPCIDevice, capabilityOffset, 4); 83 satacr1 = fPCI->read_pci_config(fPCIDevice, capabilityOffset + 4, 4); 84 TRACE("satacr0 = 0x%08" B_PRIx32 ", satacr1 = 0x%08" B_PRIx32 "\n", 85 satacr0, satacr1); 86 } 87 88 uint16 pcicmd = fPCI->read_pci_config(fPCIDevice, PCI_command, 2); 89 TRACE("pcicmd old 0x%04x\n", pcicmd); 90 pcicmd &= ~(PCI_command_io | PCI_command_int_disable); 91 pcicmd |= PCI_command_master | PCI_command_memory; 92 TRACE("pcicmd new 0x%04x\n", pcicmd); 93 fPCI->write_pci_config(fPCIDevice, PCI_command, 2, pcicmd); 94 95 if (fPCIVendorID == PCI_VENDOR_JMICRON) { 96 uint32 ctrl = fPCI->read_pci_config(fPCIDevice, PCI_JMICRON_CONTROLLER_CONTROL_1, 4); 97 TRACE("Jmicron controller control 1 old 0x%08" B_PRIx32 "\n", ctrl); 98 ctrl &= ~((1 << 9) | (1 << 12) | (1 << 14)); // disable SFF 8038i emulation 99 ctrl |= (1 << 8) | (1 << 13) | (1 << 15); // enable AHCI controller 100 TRACE("Jmicron controller control 1 new 0x%08" B_PRIx32 "\n", ctrl); 101 fPCI->write_pci_config(fPCIDevice, PCI_JMICRON_CONTROLLER_CONTROL_1, 4, ctrl); 102 } 103 104 fIRQ = pciInfo.u.h0.interrupt_line; 105 if (gPCIx86Module != NULL && gPCIx86Module->get_msi_count( 106 pciInfo.bus, pciInfo.device, pciInfo.function) >= 1) { 107 uint8 vector; 108 if (gPCIx86Module->configure_msi(pciInfo.bus, pciInfo.device, 109 pciInfo.function, 1, &vector) == B_OK 110 && gPCIx86Module->enable_msi(pciInfo.bus, pciInfo.device, 111 pciInfo.function) == B_OK) { 112 TRACE("using MSI vector %u\n", vector); 113 fIRQ = vector; 114 fUseMSI = true; 115 } else { 116 TRACE("couldn't use MSI\n"); 117 } 118 } 119 if (fIRQ == 0 || fIRQ == 0xff) { 120 TRACE("Error: PCI IRQ not assigned\n"); 121 return B_ERROR; 122 } 123 124 phys_addr_t addr = pciInfo.u.h0.base_registers[5]; 125 size_t size = pciInfo.u.h0.base_register_sizes[5]; 126 127 TRACE("registers at %#" B_PRIxPHYSADDR ", size %#" B_PRIxSIZE "\n", addr, 128 size); 129 if (addr == 0) { 130 TRACE("PCI base address register 5 not assigned\n"); 131 return B_ERROR; 132 } 133 134 fRegsArea = map_mem((void **)&fRegs, addr, size, 0, "AHCI HBA regs"); 135 if (fRegsArea < B_OK) { 136 TRACE("mapping registers failed\n"); 137 return B_ERROR; 138 } 139 140 // make sure interrupts are disabled 141 fRegs->ghc &= ~GHC_IE; 142 FlushPostedWrites(); 143 144 if (ResetController() < B_OK) { 145 TRACE("controller reset failed\n"); 146 goto err; 147 } 148 149 fCommandSlotCount = 1 + ((fRegs->cap >> CAP_NCS_SHIFT) & CAP_NCS_MASK); 150 fPortCount = 1 + ((fRegs->cap >> CAP_NP_SHIFT) & CAP_NP_MASK); 151 152 fPortImplementedMask = fRegs->pi; 153 // reported mask of implemented ports is sometimes empty 154 if (fPortImplementedMask == 0) { 155 fPortImplementedMask = 0xffffffff >> (32 - fPortCount); 156 TRACE("ports-implemented mask is zero, using 0x%" B_PRIx32 " instead.\n", 157 fPortImplementedMask); 158 } 159 160 // reported number of ports is sometimes too small 161 int highestPort; 162 highestPort = fls(fPortImplementedMask); // 1-based, 1 to 32 163 if (fPortCount < highestPort) { 164 TRACE("reported number of ports is wrong, using %d instead.\n", highestPort); 165 fPortCount = highestPort; 166 } 167 168 TRACE("cap: Interface Speed Support: generation %" B_PRIu32 "\n", 169 (fRegs->cap >> CAP_ISS_SHIFT) & CAP_ISS_MASK); 170 TRACE("cap: Number of Command Slots: %d (raw %#" B_PRIx32 ")\n", 171 fCommandSlotCount, (fRegs->cap >> CAP_NCS_SHIFT) & CAP_NCS_MASK); 172 TRACE("cap: Number of Ports: %d (raw %#" B_PRIx32 ")\n", fPortCount, 173 (fRegs->cap >> CAP_NP_SHIFT) & CAP_NP_MASK); 174 TRACE("cap: Supports Port Multiplier: %s\n", 175 (fRegs->cap & CAP_SPM) ? "yes" : "no"); 176 TRACE("cap: Supports External SATA: %s\n", 177 (fRegs->cap & CAP_SXS) ? "yes" : "no"); 178 TRACE("cap: Enclosure Management Supported: %s\n", 179 (fRegs->cap & CAP_EMS) ? "yes" : "no"); 180 181 TRACE("cap: FIS-based Switching Control: %s\n", 182 (fRegs->cap & CAP_FBSS) ? "yes" : "no"); 183 184 TRACE("cap: Supports Command List Override: %s\n", 185 (fRegs->cap & CAP_SCLO) ? "yes" : "no"); 186 TRACE("cap: Supports Staggered Spin-up: %s\n", 187 (fRegs->cap & CAP_SSS) ? "yes" : "no"); 188 TRACE("cap: Supports Mechanical Presence Switch: %s\n", 189 (fRegs->cap & CAP_SMPS) ? "yes" : "no"); 190 191 TRACE("cap: Supports 64-bit Addressing: %s\n", 192 (fRegs->cap & CAP_S64A) ? "yes" : "no"); 193 TRACE("cap: Supports Native Command Queuing: %s\n", 194 (fRegs->cap & CAP_SNCQ) ? "yes" : "no"); 195 TRACE("cap: Supports SNotification Register: %s\n", 196 (fRegs->cap & CAP_SSNTF) ? "yes" : "no"); 197 TRACE("cap: Supports Command List Override: %s\n", 198 (fRegs->cap & CAP_SCLO) ? "yes" : "no"); 199 200 TRACE("cap: Supports AHCI mode only: %s\n", (fRegs->cap & CAP_SAM) ? "yes" : "no"); 201 202 if (fRegs->vs >= 0x00010200) { 203 TRACE("cap2: DevSleep Entrance from Slumber Only: %s\n", 204 (fRegs->cap2 & CAP2_DESO) ? "yes" : "no"); 205 TRACE("cap2: Supports Aggressive Device Sleep Management: %s\n", 206 (fRegs->cap2 & CAP2_SADM) ? "yes" : "no"); 207 TRACE("cap2: Supports Device Sleep: %s\n", 208 (fRegs->cap2 & CAP2_SDS) ? "yes" : "no"); 209 TRACE("cap2: Automatic Partial to Slumber Transitions: %s\n", 210 (fRegs->cap2 & CAP2_APST) ? "yes" : "no"); 211 TRACE("cap2: NVMHCI Present: %s\n", 212 (fRegs->cap2 & CAP2_NVMP) ? "yes" : "no"); 213 TRACE("cap2: BIOS/OS Handoff: %s\n", 214 (fRegs->cap2 & CAP2_BOH) ? "yes" : "no"); 215 } 216 TRACE("ghc: AHCI Enable: %s\n", (fRegs->ghc & GHC_AE) ? "yes" : "no"); 217 TRACE("Ports Implemented Mask: %#08" B_PRIx32 " Number of Available Ports:" 218 " %d\n", fPortImplementedMask, count_bits_set(fPortImplementedMask)); 219 TRACE("AHCI Version %02" B_PRIx32 "%02" B_PRIx32 ".%02" B_PRIx32 ".%02" 220 B_PRIx32 " Interrupt %u\n", fRegs->vs >> 24, (fRegs->vs >> 16) & 0xff, 221 (fRegs->vs >> 8) & 0xff, fRegs->vs & 0xff, fIRQ); 222 223 // setup interrupt handler 224 if (install_io_interrupt_handler(fIRQ, Interrupt, this, 0) < B_OK) { 225 TRACE("can't install interrupt handler\n"); 226 goto err; 227 } 228 229 for (int i = 0; i < fPortCount; i++) { 230 if (fPortImplementedMask & (1 << i)) { 231 fPort[i] = new (std::nothrow)AHCIPort(this, i); 232 if (!fPort[i]) { 233 TRACE("out of memory creating port %d\n", i); 234 break; 235 } 236 status_t status = fPort[i]->Init1(); 237 if (status < B_OK) { 238 TRACE("init-1 port %d failed\n", i); 239 delete fPort[i]; 240 fPort[i] = NULL; 241 } 242 } 243 } 244 245 // clear any pending interrupts 246 uint32 interruptsPending; 247 interruptsPending = fRegs->is; 248 fRegs->is = interruptsPending; 249 FlushPostedWrites(); 250 251 // enable interrupts 252 fRegs->ghc |= GHC_IE; 253 FlushPostedWrites(); 254 255 for (int i = 0; i < fPortCount; i++) { 256 if (fPort[i]) { 257 status_t status = fPort[i]->Init2(); 258 if (status < B_OK) { 259 TRACE("init-2 port %d failed\n", i); 260 fPort[i]->Uninit(); 261 delete fPort[i]; 262 fPort[i] = NULL; 263 } 264 } 265 } 266 267 268 return B_OK; 269 270 err: 271 delete_area(fRegsArea); 272 return B_ERROR; 273 } 274 275 276 void 277 AHCIController::Uninit() 278 { 279 TRACE("AHCIController::Uninit\n"); 280 281 for (int i = 0; i < fPortCount; i++) { 282 if (fPort[i]) { 283 fPort[i]->Uninit(); 284 delete fPort[i]; 285 } 286 } 287 288 // disable interrupts 289 fRegs->ghc &= ~GHC_IE; 290 FlushPostedWrites(); 291 292 // clear pending interrupts 293 fRegs->is = 0xffffffff; 294 FlushPostedWrites(); 295 296 // well... 297 remove_io_interrupt_handler(fIRQ, Interrupt, this); 298 299 if (fUseMSI && gPCIx86Module != NULL) { 300 pci_info pciInfo; 301 fPCI->get_pci_info(fPCIDevice, &pciInfo); 302 gPCIx86Module->disable_msi(pciInfo.bus, 303 pciInfo.device, pciInfo.function); 304 gPCIx86Module->unconfigure_msi(pciInfo.bus, 305 pciInfo.device, pciInfo.function); 306 } 307 308 delete_area(fRegsArea); 309 310 // --- Instance check workaround begin 311 delete_port(fInstanceCheck); 312 // --- Instance check workaround end 313 } 314 315 316 status_t 317 AHCIController::ResetController() 318 { 319 uint32 saveCaps = fRegs->cap & (CAP_SMPS | CAP_SSS | CAP_SPM | CAP_EMS | CAP_SXS); 320 uint32 savePI = fRegs->pi; 321 322 // AHCI 1.3: Software may perform an HBA reset prior to initializing the controller 323 // by setting GHC.AE to ‘1’ and then setting GHC.HR to ‘1’ if desired. 324 fRegs->ghc |= GHC_AE; 325 FlushPostedWrites(); 326 fRegs->ghc |= GHC_HR; 327 FlushPostedWrites(); 328 if (wait_until_clear(&fRegs->ghc, GHC_HR, 1000000) < B_OK) 329 return B_TIMED_OUT; 330 331 fRegs->ghc |= GHC_AE; 332 FlushPostedWrites(); 333 fRegs->cap |= saveCaps; 334 fRegs->pi = savePI; 335 FlushPostedWrites(); 336 337 if (fPCIVendorID == PCI_VENDOR_INTEL) { 338 // Intel PCS—Port Control and Status 339 // SATA port enable bits must be set 340 int portCount = std::max(fls(fRegs->pi), 1 + (int)((fRegs->cap >> CAP_NP_SHIFT) & CAP_NP_MASK)); 341 if (portCount > 8) { 342 // TODO: fix this when specification available 343 TRACE("don't know how to enable SATA ports 9 to %d\n", portCount); 344 portCount = 8; 345 } 346 uint16 pcs = fPCI->read_pci_config(fPCIDevice, 0x92, 2); 347 pcs |= (0xff >> (8 - portCount)); 348 fPCI->write_pci_config(fPCIDevice, 0x92, 2, pcs); 349 } 350 return B_OK; 351 } 352 353 354 int32 355 AHCIController::Interrupt(void *data) 356 { 357 AHCIController *self = (AHCIController *)data; 358 uint32 interruptPending = self->fRegs->is & self->fPortImplementedMask; 359 360 if (interruptPending == 0) 361 return B_UNHANDLED_INTERRUPT; 362 363 for (int i = 0; i < self->fPortCount; i++) { 364 if (interruptPending & (1 << i)) { 365 if (self->fPort[i]) { 366 self->fPort[i]->Interrupt(); 367 } else { 368 FLOW("interrupt on non-existent port %d\n", i); 369 } 370 } 371 } 372 373 // clear pending interrupts 374 self->fRegs->is = interruptPending; 375 376 return B_INVOKE_SCHEDULER; 377 } 378 379 380 void 381 AHCIController::ExecuteRequest(scsi_ccb *request) 382 { 383 if (request->target_lun || !fPort[request->target_id]) { 384 request->subsys_status = SCSI_DEV_NOT_THERE; 385 gSCSI->finished(request, 1); 386 return; 387 } 388 389 fPort[request->target_id]->ScsiExecuteRequest(request); 390 } 391 392 393 uchar 394 AHCIController::AbortRequest(scsi_ccb *request) 395 { 396 if (request->target_lun || !fPort[request->target_id]) 397 return SCSI_DEV_NOT_THERE; 398 399 return fPort[request->target_id]->ScsiAbortRequest(request); 400 } 401 402 403 uchar 404 AHCIController::TerminateRequest(scsi_ccb *request) 405 { 406 if (request->target_lun || !fPort[request->target_id]) 407 return SCSI_DEV_NOT_THERE; 408 409 return fPort[request->target_id]->ScsiTerminateRequest(request); 410 } 411 412 413 uchar 414 AHCIController::ResetDevice(uchar targetID, uchar targetLUN) 415 { 416 if (targetLUN || !fPort[targetID]) 417 return SCSI_DEV_NOT_THERE; 418 419 return fPort[targetID]->ScsiResetDevice(); 420 } 421 422 423 void 424 AHCIController::GetRestrictions(uchar targetID, bool *isATAPI, 425 bool *noAutoSense, uint32 *maxBlocks) 426 { 427 if (!fPort[targetID]) 428 return; 429 430 fPort[targetID]->ScsiGetRestrictions(isATAPI, noAutoSense, maxBlocks); 431 } 432