1 /* 2 * Copyright 2007-2009, Marcus Overhagen. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 */ 5 6 #include "ahci_controller.h" 7 #include "util.h" 8 9 #include <algorithm> 10 #include <KernelExport.h> 11 #include <stdio.h> 12 #include <string.h> 13 #include <new> 14 15 #define TRACE(a...) dprintf("ahci: " a) 16 #define FLOW(a...) dprintf("ahci: " a) 17 18 19 AHCIController::AHCIController(device_node *node, 20 pci_device_module_info *pciModule, pci_device *device) 21 : 22 fNode(node), 23 fPCI(pciModule), 24 fPCIDevice(device), 25 fPCIVendorID(0xffff), 26 fPCIDeviceID(0xffff), 27 fFlags(0), 28 fCommandSlotCount(0), 29 fPortCount(0), 30 fPortImplementedMask(0), 31 fIRQ(0), 32 fUseMSI(false), 33 fInstanceCheck(-1) 34 { 35 memset(fPort, 0, sizeof(fPort)); 36 37 ASSERT(sizeof(ahci_port) == 128); 38 ASSERT(sizeof(ahci_hba) == 4352); 39 ASSERT(sizeof(fis) == 256); 40 ASSERT(sizeof(command_list_entry) == 32); 41 ASSERT(sizeof(command_table) == 128); 42 ASSERT(sizeof(prd) == 16); 43 } 44 45 46 AHCIController::~AHCIController() 47 { 48 } 49 50 51 status_t 52 AHCIController::Init() 53 { 54 pci_info pciInfo; 55 fPCI->get_pci_info(fPCIDevice, &pciInfo); 56 57 fPCIVendorID = pciInfo.vendor_id; 58 fPCIDeviceID = pciInfo.device_id; 59 60 TRACE("AHCIController::Init %u:%u:%u vendor %04x, device %04x\n", 61 pciInfo.bus, pciInfo.device, pciInfo.function, fPCIVendorID, fPCIDeviceID); 62 63 // --- Instance check workaround begin 64 char sName[32]; 65 snprintf(sName, sizeof(sName), "ahci-inst-%u-%u-%u", pciInfo.bus, pciInfo.device, pciInfo.function); 66 if (find_port(sName) >= 0) { 67 dprintf("AHCIController::Init ERROR: an instance for object %u:%u:%u already exists\n", 68 pciInfo.bus, pciInfo.device, pciInfo.function); 69 return B_ERROR; 70 } 71 fInstanceCheck = create_port(1, sName); 72 // --- Instance check workaround end 73 74 get_device_info(fPCIVendorID, fPCIDeviceID, NULL, &fFlags); 75 76 uchar capabilityOffset; 77 status_t res = fPCI->find_pci_capability(fPCIDevice, PCI_cap_id_sata, &capabilityOffset); 78 if (res == B_OK) { 79 uint32 satacr0; 80 uint32 satacr1; 81 TRACE("PCI SATA capability found at offset 0x%x\n", capabilityOffset); 82 satacr0 = fPCI->read_pci_config(fPCIDevice, capabilityOffset, 4); 83 satacr1 = fPCI->read_pci_config(fPCIDevice, capabilityOffset + 4, 4); 84 TRACE("satacr0 = 0x%08" B_PRIx32 ", satacr1 = 0x%08" B_PRIx32 "\n", 85 satacr0, satacr1); 86 } 87 88 uint16 pcicmd = fPCI->read_pci_config(fPCIDevice, PCI_command, 2); 89 TRACE("pcicmd old 0x%04x\n", pcicmd); 90 pcicmd &= ~(PCI_command_io | PCI_command_int_disable); 91 pcicmd |= PCI_command_master | PCI_command_memory; 92 TRACE("pcicmd new 0x%04x\n", pcicmd); 93 fPCI->write_pci_config(fPCIDevice, PCI_command, 2, pcicmd); 94 95 if (fPCIVendorID == PCI_VENDOR_JMICRON) { 96 uint32 ctrl = fPCI->read_pci_config(fPCIDevice, PCI_JMICRON_CONTROLLER_CONTROL_1, 4); 97 TRACE("Jmicron controller control 1 old 0x%08" B_PRIx32 "\n", ctrl); 98 ctrl &= ~((1 << 9) | (1 << 12) | (1 << 14)); // disable SFF 8038i emulation 99 ctrl |= (1 << 8) | (1 << 13) | (1 << 15); // enable AHCI controller 100 TRACE("Jmicron controller control 1 new 0x%08" B_PRIx32 "\n", ctrl); 101 fPCI->write_pci_config(fPCIDevice, PCI_JMICRON_CONTROLLER_CONTROL_1, 4, ctrl); 102 } 103 104 fIRQ = pciInfo.u.h0.interrupt_line; 105 if (gPCIx86Module != NULL && gPCIx86Module->get_msi_count( 106 pciInfo.bus, pciInfo.device, pciInfo.function) >= 1) { 107 uint8 vector; 108 if (gPCIx86Module->configure_msi(pciInfo.bus, pciInfo.device, 109 pciInfo.function, 1, &vector) == B_OK 110 && gPCIx86Module->enable_msi(pciInfo.bus, pciInfo.device, 111 pciInfo.function) == B_OK) { 112 TRACE("using MSI vector %u\n", vector); 113 fIRQ = vector; 114 fUseMSI = true; 115 } else { 116 TRACE("couldn't use MSI\n"); 117 } 118 } 119 if (fIRQ == 0 || fIRQ == 0xff) { 120 TRACE("Error: PCI IRQ not assigned\n"); 121 return B_ERROR; 122 } 123 124 phys_addr_t addr = pciInfo.u.h0.base_registers[5]; 125 size_t size = pciInfo.u.h0.base_register_sizes[5]; 126 127 TRACE("registers at %#" B_PRIxPHYSADDR ", size %#" B_PRIxSIZE "\n", addr, 128 size); 129 if (addr == 0) { 130 TRACE("PCI base address register 5 not assigned\n"); 131 return B_ERROR; 132 } 133 134 fRegsArea = map_mem((void **)&fRegs, addr, size, 0, "AHCI HBA regs"); 135 if (fRegsArea < B_OK) { 136 TRACE("mapping registers failed\n"); 137 return B_ERROR; 138 } 139 140 // make sure interrupts are disabled 141 fRegs->ghc &= ~GHC_IE; 142 FlushPostedWrites(); 143 144 if (ResetController() < B_OK) { 145 TRACE("controller reset failed\n"); 146 goto err; 147 } 148 149 fCommandSlotCount = 1 + ((fRegs->cap >> CAP_NCS_SHIFT) & CAP_NCS_MASK); 150 fPortCount = 1 + ((fRegs->cap >> CAP_NP_SHIFT) & CAP_NP_MASK); 151 152 fPortImplementedMask = fRegs->pi; 153 // reported mask of implemented ports is sometimes empty 154 if (fPortImplementedMask == 0) { 155 fPortImplementedMask = 0xffffffff >> (32 - fPortCount); 156 TRACE("ports-implemented mask is zero, using 0x%" B_PRIx32 " instead.\n", 157 fPortImplementedMask); 158 } 159 160 // reported number of ports is sometimes too small 161 int highestPort; 162 highestPort = fls(fPortImplementedMask); // 1-based, 1 to 32 163 if (fPortCount < highestPort) { 164 TRACE("reported number of ports is wrong, using %d instead.\n", highestPort); 165 fPortCount = highestPort; 166 } 167 168 TRACE("cap: Interface Speed Support: generation %" B_PRIu32 "\n", (fRegs->cap >> CAP_ISS_SHIFT) & CAP_ISS_MASK); 169 TRACE("cap: Number of Command Slots: %d (raw %#" B_PRIx32 ")\n", fCommandSlotCount, (fRegs->cap >> CAP_NCS_SHIFT) & CAP_NCS_MASK); 170 TRACE("cap: Number of Ports: %d (raw %#" B_PRIx32 ")\n", fPortCount, (fRegs->cap >> CAP_NP_SHIFT) & CAP_NP_MASK); 171 TRACE("cap: Supports Port Multiplier: %s\n", (fRegs->cap & CAP_SPM) ? "yes" : "no"); 172 TRACE("cap: Supports External SATA: %s\n", (fRegs->cap & CAP_SXS) ? "yes" : "no"); 173 TRACE("cap: Enclosure Management Supported: %s\n", (fRegs->cap & CAP_EMS) ? "yes" : "no"); 174 175 TRACE("cap: Supports Command List Override: %s\n", (fRegs->cap & CAP_SCLO) ? "yes" : "no"); 176 TRACE("cap: Supports Staggered Spin-up: %s\n", (fRegs->cap & CAP_SSS) ? "yes" : "no"); 177 TRACE("cap: Supports Mechanical Presence Switch: %s\n", (fRegs->cap & CAP_SMPS) ? "yes" : "no"); 178 179 TRACE("cap: Supports 64-bit Addressing: %s\n", (fRegs->cap & CAP_S64A) ? "yes" : "no"); 180 TRACE("cap: Supports Native Command Queuing: %s\n", (fRegs->cap & CAP_SNCQ) ? "yes" : "no"); 181 TRACE("cap: Supports SNotification Register: %s\n", (fRegs->cap & CAP_SSNTF) ? "yes" : "no"); 182 TRACE("cap: Supports Command List Override: %s\n", (fRegs->cap & CAP_SCLO) ? "yes" : "no"); 183 184 185 TRACE("cap: Supports AHCI mode only: %s\n", (fRegs->cap & CAP_SAM) ? "yes" : "no"); 186 TRACE("ghc: AHCI Enable: %s\n", (fRegs->ghc & GHC_AE) ? "yes" : "no"); 187 TRACE("Ports Implemented Mask: %#08" B_PRIx32 "\n", fPortImplementedMask); 188 TRACE("Number of Available Ports: %d\n", count_bits_set(fPortImplementedMask)); 189 TRACE("AHCI Version %" B_PRIu32 ".%" B_PRIu32 "\n", fRegs->vs >> 16, fRegs->vs & 0xff); 190 TRACE("Interrupt %u\n", fIRQ); 191 192 // setup interrupt handler 193 if (install_io_interrupt_handler(fIRQ, Interrupt, this, 0) < B_OK) { 194 TRACE("can't install interrupt handler\n"); 195 goto err; 196 } 197 198 for (int i = 0; i < fPortCount; i++) { 199 if (fPortImplementedMask & (1 << i)) { 200 fPort[i] = new (std::nothrow)AHCIPort(this, i); 201 if (!fPort[i]) { 202 TRACE("out of memory creating port %d\n", i); 203 break; 204 } 205 status_t status = fPort[i]->Init1(); 206 if (status < B_OK) { 207 TRACE("init-1 port %d failed\n", i); 208 delete fPort[i]; 209 fPort[i] = NULL; 210 } 211 } 212 } 213 214 // clear any pending interrupts 215 uint32 interruptsPending; 216 interruptsPending = fRegs->is; 217 fRegs->is = interruptsPending; 218 FlushPostedWrites(); 219 220 // enable interrupts 221 fRegs->ghc |= GHC_IE; 222 FlushPostedWrites(); 223 224 for (int i = 0; i < fPortCount; i++) { 225 if (fPort[i]) { 226 status_t status = fPort[i]->Init2(); 227 if (status < B_OK) { 228 TRACE("init-2 port %d failed\n", i); 229 fPort[i]->Uninit(); 230 delete fPort[i]; 231 fPort[i] = NULL; 232 } 233 } 234 } 235 236 237 return B_OK; 238 239 err: 240 delete_area(fRegsArea); 241 return B_ERROR; 242 } 243 244 245 void 246 AHCIController::Uninit() 247 { 248 TRACE("AHCIController::Uninit\n"); 249 250 for (int i = 0; i < fPortCount; i++) { 251 if (fPort[i]) { 252 fPort[i]->Uninit(); 253 delete fPort[i]; 254 } 255 } 256 257 // disable interrupts 258 fRegs->ghc &= ~GHC_IE; 259 FlushPostedWrites(); 260 261 // clear pending interrupts 262 fRegs->is = 0xffffffff; 263 FlushPostedWrites(); 264 265 // well... 266 remove_io_interrupt_handler(fIRQ, Interrupt, this); 267 268 if (fUseMSI && gPCIx86Module != NULL) { 269 pci_info pciInfo; 270 fPCI->get_pci_info(fPCIDevice, &pciInfo); 271 gPCIx86Module->disable_msi(pciInfo.bus, 272 pciInfo.device, pciInfo.function); 273 gPCIx86Module->unconfigure_msi(pciInfo.bus, 274 pciInfo.device, pciInfo.function); 275 } 276 277 delete_area(fRegsArea); 278 279 // --- Instance check workaround begin 280 delete_port(fInstanceCheck); 281 // --- Instance check workaround end 282 } 283 284 285 status_t 286 AHCIController::ResetController() 287 { 288 uint32 saveCaps = fRegs->cap & (CAP_SMPS | CAP_SSS | CAP_SPM | CAP_EMS | CAP_SXS); 289 uint32 savePI = fRegs->pi; 290 291 // AHCI 1.3: Software may perform an HBA reset prior to initializing the controller 292 // by setting GHC.AE to ‘1’ and then setting GHC.HR to ‘1’ if desired. 293 fRegs->ghc |= GHC_AE; 294 FlushPostedWrites(); 295 fRegs->ghc |= GHC_HR; 296 FlushPostedWrites(); 297 if (wait_until_clear(&fRegs->ghc, GHC_HR, 1000000) < B_OK) 298 return B_TIMED_OUT; 299 300 fRegs->ghc |= GHC_AE; 301 FlushPostedWrites(); 302 fRegs->cap |= saveCaps; 303 fRegs->pi = savePI; 304 FlushPostedWrites(); 305 306 if (fPCIVendorID == PCI_VENDOR_INTEL) { 307 // Intel PCS—Port Control and Status 308 // SATA port enable bits must be set 309 int portCount = std::max(fls(fRegs->pi), 1 + (int)((fRegs->cap >> CAP_NP_SHIFT) & CAP_NP_MASK)); 310 if (portCount > 8) { 311 // TODO: fix this when specification available 312 TRACE("don't know how to enable SATA ports 9 to %d\n", portCount); 313 portCount = 8; 314 } 315 uint16 pcs = fPCI->read_pci_config(fPCIDevice, 0x92, 2); 316 pcs |= (0xff >> (8 - portCount)); 317 fPCI->write_pci_config(fPCIDevice, 0x92, 2, pcs); 318 } 319 return B_OK; 320 } 321 322 323 int32 324 AHCIController::Interrupt(void *data) 325 { 326 AHCIController *self = (AHCIController *)data; 327 uint32 interruptPending = self->fRegs->is & self->fPortImplementedMask; 328 329 if (interruptPending == 0) 330 return B_UNHANDLED_INTERRUPT; 331 332 for (int i = 0; i < self->fPortCount; i++) { 333 if (interruptPending & (1 << i)) { 334 if (self->fPort[i]) { 335 self->fPort[i]->Interrupt(); 336 } else { 337 FLOW("interrupt on non-existent port %d\n", i); 338 } 339 } 340 } 341 342 // clear pending interrupts 343 self->fRegs->is = interruptPending; 344 345 return B_INVOKE_SCHEDULER; 346 } 347 348 349 void 350 AHCIController::ExecuteRequest(scsi_ccb *request) 351 { 352 if (request->target_lun || !fPort[request->target_id]) { 353 request->subsys_status = SCSI_DEV_NOT_THERE; 354 gSCSI->finished(request, 1); 355 return; 356 } 357 358 fPort[request->target_id]->ScsiExecuteRequest(request); 359 } 360 361 362 uchar 363 AHCIController::AbortRequest(scsi_ccb *request) 364 { 365 if (request->target_lun || !fPort[request->target_id]) 366 return SCSI_DEV_NOT_THERE; 367 368 return fPort[request->target_id]->ScsiAbortRequest(request); 369 } 370 371 372 uchar 373 AHCIController::TerminateRequest(scsi_ccb *request) 374 { 375 if (request->target_lun || !fPort[request->target_id]) 376 return SCSI_DEV_NOT_THERE; 377 378 return fPort[request->target_id]->ScsiTerminateRequest(request); 379 } 380 381 382 uchar 383 AHCIController::ResetDevice(uchar targetID, uchar targetLUN) 384 { 385 if (targetLUN || !fPort[targetID]) 386 return SCSI_DEV_NOT_THERE; 387 388 return fPort[targetID]->ScsiResetDevice(); 389 } 390 391 392 void 393 AHCIController::GetRestrictions(uchar targetID, bool *isATAPI, 394 bool *noAutoSense, uint32 *maxBlocks) 395 { 396 if (!fPort[targetID]) 397 return; 398 399 fPort[targetID]->ScsiGetRestrictions(isATAPI, noAutoSense, maxBlocks); 400 } 401