1 /* 2 * Copyright 2007, Marcus Overhagen. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 */ 5 6 #include "ahci_defs.h" 7 8 #include <stdlib.h> 9 #include <string.h> 10 11 12 #define TRACE(a...) dprintf("\33[35mahci:\33[0m " a) 13 #define FLOW(a...) dprintf("ahci: " a) 14 15 #define AHCI_ID_GENERATOR "ahci/id" 16 #define AHCI_ID_ITEM "ahci/id" 17 18 19 const device_info kSupportedDevices[] = { 20 { 0x1002, 0x4380, "ATI SB600" }, 21 { 0x1002, 0x4390, "ATI SB700/800" }, 22 { 0x1002, 0x4391, "ATI IXP700" }, 23 { 0x1002, 0x4392, "ATI SB700/800" }, 24 { 0x1002, 0x4393, "ATI SB700/800" }, 25 { 0x1002, 0x4394, "ATI SB700/800" }, 26 { 0x1002, 0x4395, "ATI SB700/800" }, 27 { 0x1039, 0x1184, "SiS 966" }, 28 { 0x1039, 0x1185, "SiS 966" }, 29 { 0x1039, 0x0186, "SiS 968" }, 30 { 0x10b9, 0x5288, "Acer Labs M5288" }, 31 { 0x10de, 0x044c, "NVIDIA MCP65" }, 32 { 0x10de, 0x044d, "NVIDIA MCP65" }, 33 { 0x10de, 0x044e, "NVIDIA MCP65" }, 34 { 0x10de, 0x044f, "NVIDIA MCP65" }, 35 { 0x10de, 0x045c, "NVIDIA MCP65" }, 36 { 0x10de, 0x045d, "NVIDIA MCP65" }, 37 { 0x10de, 0x045e, "NVIDIA MCP65" }, 38 { 0x10de, 0x045f, "NVIDIA MCP65" }, 39 { 0x10de, 0x0550, "NVIDIA MCP67" }, 40 { 0x10de, 0x0551, "NVIDIA MCP67" }, 41 { 0x10de, 0x0552, "NVIDIA MCP67" }, 42 { 0x10de, 0x0553, "NVIDIA MCP67" }, 43 { 0x10de, 0x0554, "NVIDIA MCP67" }, 44 { 0x10de, 0x0555, "NVIDIA MCP67" }, 45 { 0x10de, 0x0556, "NVIDIA MCP67" }, 46 { 0x10de, 0x0557, "NVIDIA MCP67" }, 47 { 0x10de, 0x0558, "NVIDIA MCP67" }, 48 { 0x10de, 0x0559, "NVIDIA MCP67" }, 49 { 0x10de, 0x055a, "NVIDIA MCP67" }, 50 { 0x10de, 0x055b, "NVIDIA MCP67" }, 51 { 0x10de, 0x07f0, "NVIDIA MCP73" }, 52 { 0x10de, 0x07f1, "NVIDIA MCP73" }, 53 { 0x10de, 0x07f2, "NVIDIA MCP73" }, 54 { 0x10de, 0x07f3, "NVIDIA MCP73" }, 55 { 0x10de, 0x07f4, "NVIDIA MCP73" }, 56 { 0x10de, 0x07f5, "NVIDIA MCP73" }, 57 { 0x10de, 0x07f6, "NVIDIA MCP73" }, 58 { 0x10de, 0x07f7, "NVIDIA MCP73" }, 59 { 0x10de, 0x07f8, "NVIDIA MCP73" }, 60 { 0x10de, 0x07f9, "NVIDIA MCP73" }, 61 { 0x10de, 0x07fa, "NVIDIA MCP73" }, 62 { 0x10de, 0x07fb, "NVIDIA MCP73" }, 63 { 0x10de, 0x0ad0, "NVIDIA MCP77" }, 64 { 0x10de, 0x0ad1, "NVIDIA MCP77" }, 65 { 0x10de, 0x0ad2, "NVIDIA MCP77" }, 66 { 0x10de, 0x0ad3, "NVIDIA MCP77" }, 67 { 0x10de, 0x0ad4, "NVIDIA MCP77" }, 68 { 0x10de, 0x0ad5, "NVIDIA MCP77" }, 69 { 0x10de, 0x0ad6, "NVIDIA MCP77" }, 70 { 0x10de, 0x0ad7, "NVIDIA MCP77" }, 71 { 0x10de, 0x0ad8, "NVIDIA MCP77" }, 72 { 0x10de, 0x0ad9, "NVIDIA MCP77" }, 73 { 0x10de, 0x0ada, "NVIDIA MCP77" }, 74 { 0x10de, 0x0adb, "NVIDIA MCP77" }, 75 { 0x1106, 0x3349, "VIA VT8251" }, 76 { 0x1106, 0x6287, "VIA VT8251" }, 77 { 0x11ab, 0x6145, "Marvell 6145" }, 78 { 0x197b, 0x2360, "JMicron JMB360" }, 79 { 0x197b, 0x2361, "JMicron JMB361" }, 80 { 0x197b, 0x2362, "JMicron JMB362" }, 81 { 0x197b, 0x2363, "JMicron JMB363" }, 82 { 0x197b, 0x2366, "JMicron JMB366" }, 83 { 0x8086, 0x2652, "Intel ICH6R" }, 84 { 0x8086, 0x2653, "Intel ICH6-M" }, 85 { 0x8086, 0x2681, "Intel 63xxESB" }, 86 { 0x8086, 0x2682, "Intel ESB2" }, 87 { 0x8086, 0x2683, "Intel ESB2" }, 88 { 0x8086, 0x27c1, "Intel ICH7R (AHCI mode)" }, 89 { 0x8086, 0x27c3, "Intel ICH7R (RAID mode)" }, 90 { 0x8086, 0x27c5, "Intel ICH7-M (AHCI mode)" }, 91 { 0x8086, 0x27c6, "Intel ICH7-M DH (RAID mode)" }, 92 { 0x8086, 0x2821, "Intel ICH8 (AHCI mode)" }, 93 { 0x8086, 0x2822, "Intel ICH8R / ICH9 (RAID mode)" }, 94 { 0x8086, 0x2824, "Intel ICH8 (AHCI mode)" }, 95 { 0x8086, 0x2829, "Intel ICH8M (AHCI mode)" }, 96 { 0x8086, 0x282a, "Intel ICH8M (RAID mode)" }, 97 { 0x8086, 0x2922, "Intel ICH9 (AHCI mode)" }, 98 { 0x8086, 0x2923, "Intel ICH9 (AHCI mode)" }, 99 { 0x8086, 0x2924, "Intel ICH9" }, 100 { 0x8086, 0x2925, "Intel ICH9" }, 101 { 0x8086, 0x2927, "Intel ICH9" }, 102 { 0x8086, 0x2929, "Intel ICH9M" }, 103 { 0x8086, 0x292a, "Intel ICH9M" }, 104 { 0x8086, 0x292b, "Intel ICH9M" }, 105 { 0x8086, 0x292c, "Intel ICH9M" }, 106 { 0x8086, 0x292f, "Intel ICH9M" }, 107 { 0x8086, 0x294d, "Intel ICH9" }, 108 { 0x8086, 0x294e, "Intel ICH9M" }, 109 {} 110 }; 111 112 113 device_manager_info *gDeviceManager; 114 scsi_for_sim_interface *gSCSI; 115 116 117 status_t 118 get_device_info(uint16 vendorID, uint16 deviceID, const char **name, 119 uint32 *flags) 120 { 121 const device_info *info; 122 for (info = kSupportedDevices; info->vendor; info++) { 123 if (info->vendor == vendorID && info->device == deviceID) { 124 if (name) 125 *name = info->name; 126 if (flags) 127 *flags = info->flags; 128 return B_OK; 129 } 130 } 131 return B_ERROR; 132 } 133 134 135 static status_t 136 register_sim(device_node *parent) 137 { 138 int32 id = gDeviceManager->create_id(AHCI_ID_GENERATOR); 139 if (id < 0) 140 return id; 141 142 { 143 device_attr attrs[] = { 144 { B_DEVICE_FIXED_CHILD, B_STRING_TYPE, 145 { string: SCSI_FOR_SIM_MODULE_NAME }}, 146 147 { SCSI_DESCRIPTION_CONTROLLER_NAME, B_STRING_TYPE, 148 { string: AHCI_DEVICE_MODULE_NAME }}, 149 { B_DMA_MAX_TRANSFER_BLOCKS, B_UINT32_TYPE, { ui32: 255 }}, 150 { AHCI_ID_ITEM, B_UINT32_TYPE, { ui32: id }}, 151 // { PNP_MANAGER_ID_GENERATOR, B_STRING_TYPE, 152 // { string: AHCI_ID_GENERATOR }}, 153 // { PNP_MANAGER_AUTO_ID, B_UINT32_TYPE, { ui32: id }}, 154 155 { NULL } 156 }; 157 158 status_t status = gDeviceManager->register_node(parent, 159 AHCI_SIM_MODULE_NAME, attrs, NULL, NULL); 160 if (status < B_OK) 161 gDeviceManager->free_id(AHCI_ID_GENERATOR, id); 162 163 return status; 164 } 165 } 166 167 168 // #pragma mark - 169 170 171 static float 172 ahci_supports_device(device_node *parent) 173 { 174 uint16 baseClass, subClass, classAPI; 175 uint16 vendorID; 176 uint16 deviceID; 177 const char *name; 178 const char *bus; 179 180 TRACE("ahci_supports_device\n"); 181 182 if (gDeviceManager->get_attr_string(parent, B_DEVICE_BUS, &bus, false) 183 < B_OK) 184 return 0.0f; 185 186 if (strcmp(bus, "pci")) 187 return 0.0f; 188 189 if (gDeviceManager->get_attr_uint16(parent, B_DEVICE_TYPE, &baseClass, 190 false) < B_OK 191 || gDeviceManager->get_attr_uint16(parent, B_DEVICE_SUB_TYPE, &subClass, 192 false) < B_OK 193 || gDeviceManager->get_attr_uint16(parent, B_DEVICE_INTERFACE, 194 &classAPI, false) < B_OK 195 || gDeviceManager->get_attr_uint16(parent, B_DEVICE_VENDOR_ID, 196 &vendorID, false) < B_OK 197 || gDeviceManager->get_attr_uint16(parent, B_DEVICE_ID, &deviceID, 198 false) < B_OK) 199 return 0.0f; 200 201 if (get_device_info(vendorID, deviceID, &name, NULL) < B_OK) { 202 if (baseClass != PCI_mass_storage || subClass != PCI_sata 203 || classAPI != PCI_sata_ahci) 204 return 0.0f; 205 TRACE("generic AHCI controller found! vendor 0x%04x, device 0x%04x\n", vendorID, deviceID); 206 return 0.8f; 207 } 208 209 if (vendorID == PCI_VENDOR_JMICRON) { 210 // JMicron uses the same device ID for SATA and PATA controllers, 211 // check if BAR5 exists to determine if it's a AHCI controller 212 pci_device_module_info *pci; 213 pci_device *device; 214 pci_info info; 215 216 gDeviceManager->get_driver(parent, (driver_module_info **)&pci, 217 (void **)&device); 218 pci->get_pci_info(device, &info); 219 220 if (info.u.h0.base_register_sizes[5] == 0) 221 return 0.0f; 222 } 223 224 TRACE("AHCI controller %s found!\n", name); 225 return 1.0f; 226 } 227 228 229 static status_t 230 ahci_register_device(device_node *parent) 231 { 232 device_attr attrs[] = { 233 { SCSI_DEVICE_MAX_TARGET_COUNT, B_UINT32_TYPE, 234 { ui32: 33 }}, 235 236 // DMA properties 237 // data must be word-aligned; 238 { B_DMA_ALIGNMENT, B_UINT32_TYPE, { ui32: 1 }}, 239 // one S/G block must not cross 64K boundary 240 { B_DMA_BOUNDARY, B_UINT32_TYPE, { ui32: 0xffff }}, 241 // max size of S/G block is 16 bits with zero being 64K 242 { B_DMA_MAX_SEGMENT_BLOCKS, B_UINT32_TYPE, { ui32: 0x10000 }}, 243 { B_DMA_MAX_SEGMENT_COUNT, B_UINT32_TYPE, 244 { ui32: 32 /* whatever... */ }}, 245 { NULL } 246 }; 247 248 TRACE("ahci_register_device\n"); 249 250 return gDeviceManager->register_node(parent, AHCI_DEVICE_MODULE_NAME, 251 attrs, NULL, NULL); 252 } 253 254 255 static status_t 256 ahci_init_driver(device_node *node, void **_cookie) 257 { 258 TRACE("ahci_init_driver\n"); 259 *_cookie = node; 260 return B_OK; 261 } 262 263 264 static void 265 ahci_uninit_driver(void *cookie) 266 { 267 TRACE("ahci_uninit_driver, cookie %p\n", cookie); 268 } 269 270 271 static status_t 272 ahci_register_child_devices(void *cookie) 273 { 274 device_node *node = (device_node *)cookie; 275 276 // TODO: register SIM for every controller we find! 277 return register_sim(node); 278 } 279 280 281 static void 282 ahci_device_removed(void *cookie) 283 { 284 TRACE("ahci_device_removed, cookie %p\n", cookie); 285 } 286 287 288 static status_t 289 std_ops(int32 op, ...) 290 { 291 switch (op) { 292 case B_MODULE_INIT: 293 case B_MODULE_UNINIT: 294 return B_OK; 295 296 default: 297 return B_ERROR; 298 } 299 } 300 301 302 driver_module_info sAHCIDevice = { 303 { 304 AHCI_DEVICE_MODULE_NAME, 305 0, 306 std_ops 307 }, 308 ahci_supports_device, 309 ahci_register_device, 310 ahci_init_driver, 311 ahci_uninit_driver, 312 ahci_register_child_devices, 313 NULL, // rescan 314 ahci_device_removed 315 }; 316 317 318 module_dependency module_dependencies[] = { 319 { B_DEVICE_MANAGER_MODULE_NAME, (module_info **)&gDeviceManager }, 320 { SCSI_FOR_SIM_MODULE_NAME, (module_info **)&gSCSI }, 321 {} 322 }; 323 324 325 module_info *modules[] = { 326 (module_info *)&sAHCIDevice, 327 (module_info *)&gAHCISimInterface, 328 NULL 329 }; 330