xref: /haiku/src/add-ons/kernel/busses/scsi/53c8xx/symbios.h (revision a950a7fffa3c4fad091962bcc7d90c3c2354577e)
1*a950a7ffSIthamar R. Adema /*
2*a950a7ffSIthamar R. Adema 	Copyright 1999, Be Incorporated.   All Rights Reserved.
3*a950a7ffSIthamar R. Adema 	This file may be used under the terms of the Be Sample Code License.
4*a950a7ffSIthamar R. Adema */
5*a950a7ffSIthamar R. Adema 
6*a950a7ffSIthamar R. Adema /*
7*a950a7ffSIthamar R. Adema ** 53c8xx Driver - Data structures and shared constants
8*a950a7ffSIthamar R. Adema */
9*a950a7ffSIthamar R. Adema 
10*a950a7ffSIthamar R. Adema /* status codes signaled from SCRIPTS to driver */
11*a950a7ffSIthamar R. Adema #define status_ready           0x10  // idle loop interrupted by driver
12*a950a7ffSIthamar R. Adema #define status_reselected      0x11  // select or idle interrupted by reselection
13*a950a7ffSIthamar R. Adema #define status_timeout         0x12  // select timed out
14*a950a7ffSIthamar R. Adema #define status_selected        0x13  // select succeeded
15*a950a7ffSIthamar R. Adema #define status_complete        0x14  // transaction completed
16*a950a7ffSIthamar R. Adema #define status_disconnect      0x15  // device disconnected in the middle
17*a950a7ffSIthamar R. Adema #define status_badstatus       0x16  // snafu in the status phase
18*a950a7ffSIthamar R. Adema #define status_overrun         0x17  // data overrun occurred
19*a950a7ffSIthamar R. Adema #define status_underrun        0x18  // data underrun occurred
20*a950a7ffSIthamar R. Adema #define status_badphase        0x19  // weird phase transition occurred
21*a950a7ffSIthamar R. Adema #define status_badmsg          0x1a  // bad msg received
22*a950a7ffSIthamar R. Adema #define status_badextmsg       0x1b  // bad extended msg received
23*a950a7ffSIthamar R. Adema #define status_selftest        0x1c  // used by selftest stub
24*a950a7ffSIthamar R. Adema #define status_iocomplete      0x1d
25*a950a7ffSIthamar R. Adema #define status_syncin          0x1e
26*a950a7ffSIthamar R. Adema #define status_widein          0x1f
27*a950a7ffSIthamar R. Adema #define status_ignore_residue  0x20
28*a950a7ffSIthamar R. Adema 
29*a950a7ffSIthamar R. Adema /* status codes private to driver */
30*a950a7ffSIthamar R. Adema #define status_inactive        0x00  // no request pending
31*a950a7ffSIthamar R. Adema #define status_queued          0x01  // start request is in the startqueue
32*a950a7ffSIthamar R. Adema #define status_selecting       0x02  // attempting to select
33*a950a7ffSIthamar R. Adema #define status_active          0x03  // SCRIPTS is handling it
34*a950a7ffSIthamar R. Adema #define status_waiting         0x04  // Waiting for reselection
35*a950a7ffSIthamar R. Adema 
36*a950a7ffSIthamar R. Adema #define OP_NDATA_IN  0x09000000L
37*a950a7ffSIthamar R. Adema #define OP_NDATA_OUT 0x08000000L
38*a950a7ffSIthamar R. Adema #define OP_WDATA_IN  0x01000000L
39*a950a7ffSIthamar R. Adema #define OP_WDATA_OUT 0x00000000L
40*a950a7ffSIthamar R. Adema 
41*a950a7ffSIthamar R. Adema #define OP_END      0x98080000L
42*a950a7ffSIthamar R. Adema #define ARG_END     (status_iocomplete)
43*a950a7ffSIthamar R. Adema 
44*a950a7ffSIthamar R. Adema typedef struct
45*a950a7ffSIthamar R. Adema {
46*a950a7ffSIthamar R. Adema 	uint32 count;
47*a950a7ffSIthamar R. Adema 	uint32 address;
48*a950a7ffSIthamar R. Adema } SymInd;
49*a950a7ffSIthamar R. Adema 
50*a950a7ffSIthamar R. Adema #define PATCH_DATAIN ((Ent_do_datain/4) + 1)
51*a950a7ffSIthamar R. Adema #define PATCH_DATAOUT ((Ent_do_dataout/4) + 1)
52*a950a7ffSIthamar R. Adema 
53*a950a7ffSIthamar R. Adema 
54*a950a7ffSIthamar R. Adema #define ctxt_device    0
55*a950a7ffSIthamar R. Adema #define ctxt_sendmsg   1
56*a950a7ffSIthamar R. Adema #define ctxt_recvmsg   2
57*a950a7ffSIthamar R. Adema #define ctxt_extdmsg   3
58*a950a7ffSIthamar R. Adema #define ctxt_syncmsg   4
59*a950a7ffSIthamar R. Adema #define ctxt_status    5
60*a950a7ffSIthamar R. Adema #define ctxt_command   6
61*a950a7ffSIthamar R. Adema #define ctxt_widemsg   7
62*a950a7ffSIthamar R. Adema #define ctxt_program   8
63*a950a7ffSIthamar R. Adema 
64*a950a7ffSIthamar R. Adema typedef struct
65*a950a7ffSIthamar R. Adema {
66*a950a7ffSIthamar R. Adema 	uchar _command[12];       /*  0 - 11 */
67*a950a7ffSIthamar R. Adema 	uchar _syncmsg[2];        /* 12 - 13 */
68*a950a7ffSIthamar R. Adema 	uchar _widemsg[2];        /* 14 - 15 */
69*a950a7ffSIthamar R. Adema 	uchar _sendmsg[8];        /* 16 - 23 */
70*a950a7ffSIthamar R. Adema 	uchar _recvmsg[1];        /*      24 */
71*a950a7ffSIthamar R. Adema 	uchar _extdmsg[1];        /*      25 */
72*a950a7ffSIthamar R. Adema 	uchar _status[1];         /*      26 */
73*a950a7ffSIthamar R. Adema 	uchar _padding[1];        /*      27 */
74*a950a7ffSIthamar R. Adema 
75*a950a7ffSIthamar R. Adema 	SymInd device;            /*      28 */
76*a950a7ffSIthamar R. Adema 	SymInd sendmsg;           /*      36 */
77*a950a7ffSIthamar R. Adema 	SymInd recvmsg;           /*      44 */
78*a950a7ffSIthamar R. Adema 	SymInd extdmsg;           /*      52 */
79*a950a7ffSIthamar R. Adema 	SymInd syncmsg;           /*      60 */
80*a950a7ffSIthamar R. Adema 	SymInd status;            /*      68 */
81*a950a7ffSIthamar R. Adema 	SymInd command;           /*      76 */
82*a950a7ffSIthamar R. Adema 	SymInd widemsg;           /*      84 */
83*a950a7ffSIthamar R. Adema 
84*a950a7ffSIthamar R. Adema /* MUST be dword aligned! */
85*a950a7ffSIthamar R. Adema 	SymInd table[131];        /*      92 --- 129 entries, 1 eot, 1 scratch */
86*a950a7ffSIthamar R. Adema } SymPriv;
87*a950a7ffSIthamar R. Adema 
88*a950a7ffSIthamar R. Adema #define ADJUST_PRIV_TO_DSA    28
89*a950a7ffSIthamar R. Adema #define ADJUST_PRIV_TO_TABLE  92
90*a950a7ffSIthamar R. Adema 
91*a950a7ffSIthamar R. Adema typedef struct _SymTarg
92*a950a7ffSIthamar R. Adema {
93*a950a7ffSIthamar R. Adema 	struct _Symbios *adapter;
94*a950a7ffSIthamar R. Adema 	struct _SymTarg *next;
95*a950a7ffSIthamar R. Adema 
96*a950a7ffSIthamar R. Adema 	uchar device[4];     /* symbios register defs for the device */
97*a950a7ffSIthamar R. Adema 	int sem_targ;        /* mutex allowing only one req per target */
98*a950a7ffSIthamar R. Adema 	int sem_done;        /* notification semaphore */
99*a950a7ffSIthamar R. Adema 	CCB_SCSIIO *ccb;     /* ccb for the current request for this target or NULL */
100*a950a7ffSIthamar R. Adema 
101*a950a7ffSIthamar R. Adema 	SymPriv *priv;	     /* priv data area within ccb */
102*a950a7ffSIthamar R. Adema 	uint32 priv_phys;    /* physical address of priv */
103*a950a7ffSIthamar R. Adema 	uint32 table_phys;   /* physical address of sgtable */
104*a950a7ffSIthamar R. Adema 	uint32 datain_phys;
105*a950a7ffSIthamar R. Adema 	uint32 dataout_phys;
106*a950a7ffSIthamar R. Adema 
107*a950a7ffSIthamar R. Adema 	int inbound;         /* read data from device */
108*a950a7ffSIthamar R. Adema 
109*a950a7ffSIthamar R. Adema 	uint32 period;       /* sync period */
110*a950a7ffSIthamar R. Adema 	uint32 offset;       /* sync offset */
111*a950a7ffSIthamar R. Adema 	uint32 wide;
112*a950a7ffSIthamar R. Adema 
113*a950a7ffSIthamar R. Adema 	uint32 flags;
114*a950a7ffSIthamar R. Adema 	uint32 status;
115*a950a7ffSIthamar R. Adema 	uint32 id;
116*a950a7ffSIthamar R. Adema } SymTarg;
117*a950a7ffSIthamar R. Adema 
118*a950a7ffSIthamar R. Adema #define tf_ask_sync   0x0001
119*a950a7ffSIthamar R. Adema #define tf_ask_wide   0x0002
120*a950a7ffSIthamar R. Adema #define tf_is_sync    0x0010
121*a950a7ffSIthamar R. Adema #define tf_is_wide    0x0020
122*a950a7ffSIthamar R. Adema #define tf_ignore     0x0100
123*a950a7ffSIthamar R. Adema 
124*a950a7ffSIthamar R. Adema typedef struct _Symbios
125*a950a7ffSIthamar R. Adema {
126*a950a7ffSIthamar R. Adema 	uint32 num;           /* card number */
127*a950a7ffSIthamar R. Adema 	uint32 iobase;        /* io base address */
128*a950a7ffSIthamar R. Adema 	uint32 irq;           /* assigned irq */
129*a950a7ffSIthamar R. Adema 
130*a950a7ffSIthamar R. Adema 	char *name;           /* device type name */
131*a950a7ffSIthamar R. Adema 	uint32 host_targ_id;
132*a950a7ffSIthamar R. Adema 	uint32 max_targ_id;
133*a950a7ffSIthamar R. Adema 	int reset;
134*a950a7ffSIthamar R. Adema 
135*a950a7ffSIthamar R. Adema 	int registered;
136*a950a7ffSIthamar R. Adema 
137*a950a7ffSIthamar R. Adema 	uint32 *script;       /* 1 page of on/offboard scripts ram */
138*a950a7ffSIthamar R. Adema 	uint32 sram_phys;     /* physical address thereof */
139*a950a7ffSIthamar R. Adema 
140*a950a7ffSIthamar R. Adema 	SymTarg targ[16];     /* one targ descriptor per target */
141*a950a7ffSIthamar R. Adema 	spinlock hwlock;      /* lock protecting register access */
142*a950a7ffSIthamar R. Adema 
143*a950a7ffSIthamar R. Adema 	SymTarg *startqueue;   /* target being started */
144*a950a7ffSIthamar R. Adema 	SymTarg *startqueuetail;
145*a950a7ffSIthamar R. Adema 	SymTarg *active;      /* target currently being interacted with */
146*a950a7ffSIthamar R. Adema 	                      /* null if IDLE, == startqueue if starting */
147*a950a7ffSIthamar R. Adema 
148*a950a7ffSIthamar R. Adema 	enum {
149*a950a7ffSIthamar R. Adema 		OFFLINE, IDLE, START, ACTIVE, TEST
150*a950a7ffSIthamar R. Adema 	} status;
151*a950a7ffSIthamar R. Adema 
152*a950a7ffSIthamar R. Adema 	struct {
153*a950a7ffSIthamar R. Adema 		uint period;    /* negotiated period */
154*a950a7ffSIthamar R. Adema 		uint  period_ns; /* configured period in ns */
155*a950a7ffSIthamar R. Adema 		uchar scntl3;    /* values for scntl3 SCF and CCF bits */
156*a950a7ffSIthamar R. Adema 		uchar sxfer;     /* values for xfer TP2-0 bits */
157*a950a7ffSIthamar R. Adema 	} syncinfo[16];
158*a950a7ffSIthamar R. Adema 	uint32 syncsize;     /* number of syncinfo entries to look at */
159*a950a7ffSIthamar R. Adema 	uint32 idmask;
160*a950a7ffSIthamar R. Adema 
161*a950a7ffSIthamar R. Adema 	uint32 scntl3;
162*a950a7ffSIthamar R. Adema 	uint32 sclk;         /* SCLK in KHz */
163*a950a7ffSIthamar R. Adema 	uint32 maxoffset;
164*a950a7ffSIthamar R. Adema 
165*a950a7ffSIthamar R. Adema 	uint32 op_in;
166*a950a7ffSIthamar R. Adema 	uint32 op_out;
167*a950a7ffSIthamar R. Adema } Symbios;
168