1*8426404fSX512 /* 2*8426404fSX512 * Copyright 2020, Jérôme Duval, jerome.duval@gmail.com. 3*8426404fSX512 * 4*8426404fSX512 * Distributed under the terms of the MIT License. 5*8426404fSX512 */ 6*8426404fSX512 #ifndef _PCH_I2C_H 7*8426404fSX512 #define _PCH_I2C_H 8*8426404fSX512 9*8426404fSX512 10*8426404fSX512 #include "pch_i2c_hardware.h" 11*8426404fSX512 12*8426404fSX512 extern "C" { 13*8426404fSX512 # include "acpi.h" 14*8426404fSX512 } 15*8426404fSX512 16*8426404fSX512 #include <i2c.h> 17*8426404fSX512 #include <lock.h> 18*8426404fSX512 19*8426404fSX512 20*8426404fSX512 //#define TRACE_PCH_I2C 21*8426404fSX512 #ifdef TRACE_PCH_I2C 22*8426404fSX512 # define TRACE(x...) dprintf("\33[33mpch_i2c_pci:\33[0m " x) 23*8426404fSX512 #else 24*8426404fSX512 # define TRACE(x...) ; 25*8426404fSX512 #endif 26*8426404fSX512 #define TRACE_ALWAYS(x...) dprintf("\33[33mpch_i2c_pci:\33[0m " x) 27*8426404fSX512 #define ERROR(x...) dprintf("\33[33mpch_i2c_pci:\33[0m " x) 28*8426404fSX512 #define CALLED(x...) TRACE("CALLED %s\n", __PRETTY_FUNCTION__) 29*8426404fSX512 30*8426404fSX512 31*8426404fSX512 #define PCH_I2C_ACPI_DEVICE_MODULE_NAME "busses/i2c/pch_i2c/acpi/driver_v1" 32*8426404fSX512 #define PCH_I2C_PCI_DEVICE_MODULE_NAME "busses/i2c/pch_i2c/pci/driver_v1" 33*8426404fSX512 #define PCH_I2C_SIM_MODULE_NAME "busses/i2c/pch_i2c/device/v1" 34*8426404fSX512 35*8426404fSX512 36*8426404fSX512 #define write32(address, data) \ 37*8426404fSX512 (*((volatile uint32*)(address)) = (data)) 38*8426404fSX512 #define read32(address) \ 39*8426404fSX512 (*((volatile uint32*)(address))) 40*8426404fSX512 41*8426404fSX512 42*8426404fSX512 43*8426404fSX512 extern device_manager_info* gDeviceManager; 44*8426404fSX512 extern i2c_for_controller_interface* gI2c; 45*8426404fSX512 extern acpi_module_info* gACPI; 46*8426404fSX512 extern driver_module_info gPchI2cAcpiDevice; 47*8426404fSX512 extern driver_module_info gPchI2cPciDevice; 48*8426404fSX512 49*8426404fSX512 50*8426404fSX512 acpi_status pch_i2c_scan_bus_callback(acpi_handle object, uint32 nestingLevel, 51*8426404fSX512 void *context, void** returnValue); 52*8426404fSX512 53*8426404fSX512 54*8426404fSX512 struct pch_i2c_crs { 55*8426404fSX512 uint16 i2c_addr; 56*8426404fSX512 uint8 irq; 57*8426404fSX512 uint8 irq_triggering; 58*8426404fSX512 uint8 irq_polarity; 59*8426404fSX512 uint8 irq_shareable; 60*8426404fSX512 61*8426404fSX512 uint32 addr_bas; 62*8426404fSX512 uint32 addr_len; 63*8426404fSX512 }; 64*8426404fSX512 65*8426404fSX512 66*8426404fSX512 typedef enum { 67*8426404fSX512 PCH_I2C_IRQ_LEGACY, 68*8426404fSX512 PCH_I2C_IRQ_MSI, 69*8426404fSX512 PCH_I2C_IRQ_MSI_X_SHARED 70*8426404fSX512 } pch_i2c_irq_type; 71*8426404fSX512 72*8426404fSX512 73*8426404fSX512 typedef struct { 74*8426404fSX512 phys_addr_t base_addr; 75*8426404fSX512 uint64 map_size; 76*8426404fSX512 uint8 irq; 77*8426404fSX512 i2c_bus sim; 78*8426404fSX512 79*8426404fSX512 device_node* node; 80*8426404fSX512 device_node* driver_node; 81*8426404fSX512 82*8426404fSX512 area_id registersArea; 83*8426404fSX512 addr_t registers; 84*8426404fSX512 uint32 capabilities; 85*8426404fSX512 86*8426404fSX512 uint16 ss_hcnt; 87*8426404fSX512 uint16 ss_lcnt; 88*8426404fSX512 uint16 fs_hcnt; 89*8426404fSX512 uint16 fs_lcnt; 90*8426404fSX512 uint16 hs_hcnt; 91*8426404fSX512 uint16 hs_lcnt; 92*8426404fSX512 uint32 sda_hold_time; 93*8426404fSX512 94*8426404fSX512 uint8 tx_fifo_depth; 95*8426404fSX512 uint8 rx_fifo_depth; 96*8426404fSX512 97*8426404fSX512 uint32 masterConfig; 98*8426404fSX512 99*8426404fSX512 // transfer 100*8426404fSX512 int32 busy; 101*8426404fSX512 bool readwait; 102*8426404fSX512 bool writewait; 103*8426404fSX512 i2c_op op; 104*8426404fSX512 void* buffer; 105*8426404fSX512 size_t length; 106*8426404fSX512 uint32 flags; 107*8426404fSX512 int32 error; 108*8426404fSX512 109*8426404fSX512 mutex lock; 110*8426404fSX512 status_t (*scan_bus)(i2c_bus_cookie cookie); 111*8426404fSX512 } pch_i2c_sim_info; 112*8426404fSX512 113*8426404fSX512 114*8426404fSX512 #endif // _PCH_I2C_H 115