18426404fSX512 /* 28426404fSX512 * Copyright 2020, Jérôme Duval, jerome.duval@gmail.com. 38426404fSX512 * 48426404fSX512 * Distributed under the terms of the MIT License. 58426404fSX512 */ 68426404fSX512 #ifndef _PCH_I2C_H 78426404fSX512 #define _PCH_I2C_H 88426404fSX512 98426404fSX512 108426404fSX512 #include "pch_i2c_hardware.h" 118426404fSX512 128426404fSX512 extern "C" { 138426404fSX512 # include "acpi.h" 148426404fSX512 } 158426404fSX512 168426404fSX512 #include <i2c.h> 178426404fSX512 #include <lock.h> 188426404fSX512 198426404fSX512 208426404fSX512 //#define TRACE_PCH_I2C 218426404fSX512 #ifdef TRACE_PCH_I2C 228426404fSX512 # define TRACE(x...) dprintf("\33[33mpch_i2c_pci:\33[0m " x) 238426404fSX512 #else 248426404fSX512 # define TRACE(x...) ; 258426404fSX512 #endif 268426404fSX512 #define TRACE_ALWAYS(x...) dprintf("\33[33mpch_i2c_pci:\33[0m " x) 278426404fSX512 #define ERROR(x...) dprintf("\33[33mpch_i2c_pci:\33[0m " x) 288426404fSX512 #define CALLED(x...) TRACE("CALLED %s\n", __PRETTY_FUNCTION__) 298426404fSX512 308426404fSX512 318426404fSX512 #define PCH_I2C_ACPI_DEVICE_MODULE_NAME "busses/i2c/pch_i2c/acpi/driver_v1" 328426404fSX512 #define PCH_I2C_PCI_DEVICE_MODULE_NAME "busses/i2c/pch_i2c/pci/driver_v1" 338426404fSX512 #define PCH_I2C_SIM_MODULE_NAME "busses/i2c/pch_i2c/device/v1" 348426404fSX512 358426404fSX512 368426404fSX512 #define write32(address, data) \ 378426404fSX512 (*((volatile uint32*)(address)) = (data)) 388426404fSX512 #define read32(address) \ 398426404fSX512 (*((volatile uint32*)(address))) 408426404fSX512 418426404fSX512 428426404fSX512 438426404fSX512 extern device_manager_info* gDeviceManager; 448426404fSX512 extern i2c_for_controller_interface* gI2c; 458426404fSX512 extern acpi_module_info* gACPI; 468426404fSX512 extern driver_module_info gPchI2cAcpiDevice; 478426404fSX512 extern driver_module_info gPchI2cPciDevice; 488426404fSX512 498426404fSX512 508426404fSX512 acpi_status pch_i2c_scan_bus_callback(acpi_handle object, uint32 nestingLevel, 518426404fSX512 void *context, void** returnValue); 528426404fSX512 538426404fSX512 548426404fSX512 struct pch_i2c_crs { 558426404fSX512 uint16 i2c_addr; 56*629f071bSX512 uint32 irq; 578426404fSX512 uint8 irq_triggering; 588426404fSX512 uint8 irq_polarity; 598426404fSX512 uint8 irq_shareable; 608426404fSX512 618426404fSX512 uint32 addr_bas; 628426404fSX512 uint32 addr_len; 638426404fSX512 }; 648426404fSX512 658426404fSX512 668426404fSX512 typedef enum { 678426404fSX512 PCH_I2C_IRQ_LEGACY, 688426404fSX512 PCH_I2C_IRQ_MSI, 698426404fSX512 PCH_I2C_IRQ_MSI_X_SHARED 708426404fSX512 } pch_i2c_irq_type; 718426404fSX512 728426404fSX512 738426404fSX512 typedef struct { 748426404fSX512 phys_addr_t base_addr; 758426404fSX512 uint64 map_size; 76*629f071bSX512 uint32 irq; 778426404fSX512 i2c_bus sim; 788426404fSX512 798426404fSX512 device_node* node; 808426404fSX512 device_node* driver_node; 818426404fSX512 828426404fSX512 area_id registersArea; 838426404fSX512 addr_t registers; 848426404fSX512 uint32 capabilities; 858426404fSX512 868426404fSX512 uint16 ss_hcnt; 878426404fSX512 uint16 ss_lcnt; 888426404fSX512 uint16 fs_hcnt; 898426404fSX512 uint16 fs_lcnt; 908426404fSX512 uint16 hs_hcnt; 918426404fSX512 uint16 hs_lcnt; 928426404fSX512 uint32 sda_hold_time; 938426404fSX512 948426404fSX512 uint8 tx_fifo_depth; 958426404fSX512 uint8 rx_fifo_depth; 968426404fSX512 978426404fSX512 uint32 masterConfig; 988426404fSX512 998426404fSX512 // transfer 1008426404fSX512 int32 busy; 1018426404fSX512 bool readwait; 1028426404fSX512 bool writewait; 1038426404fSX512 i2c_op op; 1048426404fSX512 void* buffer; 1058426404fSX512 size_t length; 1068426404fSX512 uint32 flags; 1078426404fSX512 int32 error; 1088426404fSX512 1098426404fSX512 mutex lock; 1108426404fSX512 status_t (*scan_bus)(i2c_bus_cookie cookie); 1118426404fSX512 } pch_i2c_sim_info; 1128426404fSX512 1138426404fSX512 1148426404fSX512 #endif // _PCH_I2C_H 115