1 /* 2 * Copyright 2007, Ithamar R. Adema. All rights reserved. 3 * Distributed under the terms of the MIT License. 4 */ 5 6 7 #include <ata_adapter.h> 8 #include <KernelExport.h> 9 #include <PCI_x86.h> 10 11 #include <stdlib.h> 12 #include <string.h> 13 14 15 #define DRIVER_PRETTY_NAME "Legacy SATA" 16 #define CONTROLLER_NAME DRIVER_PRETTY_NAME 17 #define CONTROLLER_MODULE_NAME "busses/ata/legacy_sata/driver_v1" 18 #define CHANNEL_MODULE_NAME "busses/ata/legacy_sata/channel/v1" 19 20 #define TRACE(a...) dprintf(DRIVER_PRETTY_NAME ": " a) 21 #define FLOW(a...) dprintf(DRIVER_PRETTY_NAME ": " a) 22 23 #define PCI_vendor_VIA 0x1106 24 #define PCI_device_VIA6420 0x3149 25 #define PCI_device_VIA6421 0x3249 26 #define PCI_device_VIA8237A 0x0591 27 28 #define PCI_vendor_ALI 0x10b9 29 #define PCI_device_ALI5289 0x5289 30 #define PCI_device_ALI5287 0x5287 31 #define PCI_device_ALI5281 0x5281 32 33 #define PCI_vendor_NVIDIA 0x10de 34 #define PCI_device_NF2PROS1 0x008e 35 #define PCI_device_NF3PROS1 0x00e3 36 #define PCI_device_NF3PROS2 0x00ee 37 #define PCI_device_MCP4S1 0x0036 38 #define PCI_device_MCP4S2 0x003e 39 #define PCI_device_CK804S1 0x0054 40 #define PCI_device_CK804S2 0x0055 41 #define PCI_device_MCP51S1 0x0266 42 #define PCI_device_MCP51S2 0x0267 43 #define PCI_device_MCP55S1 0x037e 44 #define PCI_device_MCP55S2 0x037f 45 #define PCI_device_MCP61S1 0x03e7 46 #define PCI_device_MCP61S2 0x03f6 47 #define PCI_device_MCP61S3 0x03f7 48 49 #define ID(v,d) (((v)<< 16) | (d)) 50 51 52 static const char * const kChannelNames[] = { 53 "Primary Channel", "Secondary Channel", 54 "Tertiary Channel", "Quaternary Channel" 55 }; 56 57 static ata_for_controller_interface* sATA; 58 static ata_adapter_interface* sATAAdapter; 59 static device_manager_info* sDeviceManager; 60 61 62 static float 63 controller_supports(device_node *parent) 64 { 65 uint16 vendor_id; 66 uint16 device_id; 67 status_t res; 68 const char *bus = NULL; 69 70 // get the bus (should be PCI) 71 if (sDeviceManager->get_attr_string(parent, B_DEVICE_BUS, &bus, false) != B_OK) 72 return B_ERROR; 73 if (strcmp(bus, "pci") != 0) { 74 return B_ERROR; 75 } 76 77 // get vendor and device ID 78 if ((res = sDeviceManager->get_attr_uint16(parent, B_DEVICE_VENDOR_ID, &vendor_id, false)) != B_OK 79 || (res = sDeviceManager->get_attr_uint16(parent, B_DEVICE_ID, &device_id, false)) != B_OK) { 80 return res; 81 } 82 83 switch (ID(vendor_id, device_id)) { 84 /* VIA SATA chipsets */ 85 case ID(PCI_vendor_VIA, PCI_device_VIA6420): 86 case ID(PCI_vendor_VIA, PCI_device_VIA6421): 87 case ID(PCI_vendor_VIA, PCI_device_VIA8237A): 88 break; 89 90 /* ALI SATA chipsets */ 91 case ID(PCI_vendor_ALI, PCI_device_ALI5281): 92 case ID(PCI_vendor_ALI, PCI_device_ALI5287): 93 case ID(PCI_vendor_ALI, PCI_device_ALI5289): 94 break; 95 96 /* NVidia NForce chipsets */ 97 case ID(PCI_vendor_NVIDIA, PCI_device_NF2PROS1): 98 case ID(PCI_vendor_NVIDIA, PCI_device_NF3PROS1): 99 case ID(PCI_vendor_NVIDIA, PCI_device_NF3PROS2): 100 case ID(PCI_vendor_NVIDIA, PCI_device_MCP4S1): 101 case ID(PCI_vendor_NVIDIA, PCI_device_MCP4S2): 102 case ID(PCI_vendor_NVIDIA, PCI_device_CK804S1): 103 case ID(PCI_vendor_NVIDIA, PCI_device_CK804S2): 104 case ID(PCI_vendor_NVIDIA, PCI_device_MCP51S1): 105 case ID(PCI_vendor_NVIDIA, PCI_device_MCP51S2): 106 case ID(PCI_vendor_NVIDIA, PCI_device_MCP55S1): 107 case ID(PCI_vendor_NVIDIA, PCI_device_MCP55S2): 108 case ID(PCI_vendor_NVIDIA, PCI_device_MCP61S1): 109 case ID(PCI_vendor_NVIDIA, PCI_device_MCP61S2): 110 case ID(PCI_vendor_NVIDIA, PCI_device_MCP61S3): 111 break; 112 113 default: 114 return 0.0f; 115 } 116 117 TRACE("controller found! vendor 0x%04x, device 0x%04x\n", vendor_id, device_id); 118 119 return 0.8f; 120 } 121 122 123 static status_t 124 controller_probe(device_node *parent) 125 { 126 device_node *controller_node; 127 device_node *channels[4]; 128 uint16 command_block_base[4]; 129 uint16 control_block_base[4]; 130 pci_device_module_info *pci; 131 uint8 num_channels = 2; 132 uint32 bus_master_base; 133 pci_device *device = NULL; 134 uint16 device_id; 135 uint16 vendor_id; 136 uint8 int_num; 137 status_t res; 138 uint8 index; 139 140 TRACE("controller_probe\n"); 141 142 sDeviceManager->get_driver(parent, (driver_module_info **)&pci, (void **)&device); 143 144 device_id = pci->read_pci_config(device, PCI_device_id, 2); 145 vendor_id = pci->read_pci_config(device, PCI_vendor_id, 2); 146 int_num = pci->read_pci_config(device, PCI_interrupt_line, 1); 147 bus_master_base = pci->read_pci_config(device, PCI_base_registers + 16, 4); 148 149 /* Default PCI assigments */ 150 command_block_base[0] = pci->read_pci_config(device, PCI_base_registers + 0, 4); 151 control_block_base[0] = pci->read_pci_config(device, PCI_base_registers + 4, 4); 152 command_block_base[1] = pci->read_pci_config(device, PCI_base_registers + 8, 4); 153 control_block_base[1] = pci->read_pci_config(device, PCI_base_registers + 12, 4); 154 155 /* enable PCI interrupt */ 156 pci->write_pci_config(device, PCI_command, 2, 157 pci->read_pci_config(device, PCI_command, 2) & ~PCI_command_int_disable); 158 159 if (vendor_id == PCI_vendor_NVIDIA) { 160 /* enable control access */ 161 pci->write_pci_config(device, 0x50, 1, 162 pci->read_pci_config(device, 0x50, 1) | 0x04); 163 } 164 165 switch (ID(vendor_id, device_id)) { 166 case ID(PCI_vendor_VIA,PCI_device_VIA6421): 167 /* newer SATA chips has resources in one BAR for each channel */ 168 num_channels = 4; 169 command_block_base[0] = pci->read_pci_config(device, PCI_base_registers + 0, 4); 170 control_block_base[0] = command_block_base[0] + 8; 171 command_block_base[1] = pci->read_pci_config(device, PCI_base_registers + 4, 4); 172 control_block_base[1] = command_block_base[1] + 8; 173 command_block_base[2] = pci->read_pci_config(device, PCI_base_registers + 8, 4); 174 control_block_base[2] = command_block_base[2] + 8; 175 command_block_base[3] = pci->read_pci_config(device, PCI_base_registers + 12, 4); 176 control_block_base[3] = command_block_base[3] + 8; 177 break; 178 179 case ID(PCI_vendor_ALI, PCI_device_ALI5287): 180 num_channels = 4; 181 command_block_base[2] = pci->read_pci_config(device, PCI_base_registers + 0, 4) + 8; 182 control_block_base[2] = pci->read_pci_config(device, PCI_base_registers + 4, 4) + 4; 183 command_block_base[3] = pci->read_pci_config(device, PCI_base_registers + 8, 4) + 8; 184 control_block_base[3] = pci->read_pci_config(device, PCI_base_registers + 12, 4) + 4; 185 break; 186 } 187 188 bus_master_base &= PCI_address_io_mask; 189 for (index = 0; index < num_channels; index++) { 190 command_block_base[index] &= PCI_address_io_mask; 191 control_block_base[index] &= PCI_address_io_mask; 192 } 193 194 res = sATAAdapter->detect_controller(pci, device, parent, bus_master_base, 195 CONTROLLER_MODULE_NAME, "" /* XXX: unused: controller_driver_type*/, CONTROLLER_NAME, true, 196 true, 1, 0xffff, 0x10000, &controller_node); 197 // don't register if controller is already registered! 198 // (happens during rescan; registering new channels would kick out old channels) 199 if (res != B_OK) 200 goto err; 201 if (controller_node == NULL) { 202 res = B_IO_ERROR; 203 goto err; 204 } 205 206 // ignore errors during registration of channels - could be a simple rescan collision 207 208 for (index = 0; index < num_channels; index++) { 209 res = sATAAdapter->detect_channel(pci, device, controller_node, CHANNEL_MODULE_NAME, 210 true, command_block_base[index], control_block_base[index], bus_master_base, 211 int_num, index, kChannelNames[index], &channels[index], false); 212 213 dprintf("%s: %s\n", kChannelNames[index], strerror(res)); 214 } 215 216 217 TRACE("controller_probe success\n"); 218 return B_OK; 219 220 err: 221 TRACE("controller_probe failed (%s)\n", strerror(res)); 222 return res; 223 } 224 225 226 static status_t 227 controller_init(device_node *node, void **controller_cookie) 228 { 229 return sATAAdapter->init_controller( 230 node, (ata_adapter_controller_info**)controller_cookie, 231 sizeof(ata_adapter_controller_info)); 232 } 233 234 235 static void 236 controller_uninit(void *controller_cookie) 237 { 238 sATAAdapter->uninit_controller((ata_adapter_controller_info*)controller_cookie); 239 } 240 241 242 static void 243 controller_removed(void *controller_cookie) 244 { 245 sATAAdapter->controller_removed((ata_adapter_controller_info*)controller_cookie); 246 } 247 248 249 static status_t 250 channel_init(device_node *node, void **channel_cookie) 251 { 252 return sATAAdapter->init_channel(node, 253 (ata_adapter_channel_info**)channel_cookie, 254 sizeof(ata_adapter_channel_info), sATAAdapter->inthand); 255 } 256 257 258 static void 259 channel_uninit(void *channel_cookie) 260 { 261 sATAAdapter->uninit_channel((ata_adapter_channel_info*)channel_cookie); 262 } 263 264 265 static void 266 channel_removed(void *channel_cookie) 267 { 268 sATAAdapter->channel_removed((ata_adapter_channel_info*)channel_cookie); 269 } 270 271 272 static void 273 channel_set(void *channel_cookie, ata_channel channel) 274 { 275 sATAAdapter->set_channel((ata_adapter_channel_info*)channel_cookie, 276 channel); 277 } 278 279 280 static status_t 281 task_file_write(void *channel_cookie, ata_task_file *tf, ata_reg_mask mask) 282 { 283 return sATAAdapter->write_command_block_regs( 284 (ata_adapter_channel_info*)channel_cookie, tf, mask); 285 } 286 287 288 static status_t 289 task_file_read(void *channel_cookie, ata_task_file *tf, ata_reg_mask mask) 290 { 291 return sATAAdapter->read_command_block_regs( 292 (ata_adapter_channel_info*)channel_cookie, tf, mask); 293 } 294 295 296 static uint8 297 altstatus_read(void *channel_cookie) 298 { 299 return sATAAdapter->get_altstatus( 300 (ata_adapter_channel_info*)channel_cookie); 301 } 302 303 304 static status_t 305 device_control_write(void *channel_cookie, uint8 val) 306 { 307 return sATAAdapter->write_device_control( 308 (ata_adapter_channel_info*)channel_cookie, val); 309 } 310 311 312 static status_t 313 pio_write(void *channel_cookie, uint16 *data, int count, bool force_16bit) 314 { 315 return sATAAdapter->write_pio((ata_adapter_channel_info*)channel_cookie, 316 data, count, force_16bit); 317 } 318 319 320 static status_t 321 pio_read(void *channel_cookie, uint16 *data, int count, bool force_16bit) 322 { 323 return sATAAdapter->read_pio((ata_adapter_channel_info*)channel_cookie, 324 data, count, force_16bit); 325 } 326 327 328 static status_t 329 dma_prepare(void *channel_cookie, const physical_entry *sg_list, 330 size_t sg_list_count, bool write) 331 { 332 return sATAAdapter->prepare_dma((ata_adapter_channel_info*)channel_cookie, 333 sg_list, sg_list_count, write); 334 } 335 336 337 static status_t 338 dma_start(void *channel_cookie) 339 { 340 return sATAAdapter->start_dma((ata_adapter_channel_info*)channel_cookie); 341 } 342 343 344 static status_t 345 dma_finish(void *channel_cookie) 346 { 347 return sATAAdapter->finish_dma((ata_adapter_channel_info*)channel_cookie); 348 } 349 350 351 module_dependency module_dependencies[] = { 352 { ATA_FOR_CONTROLLER_MODULE_NAME, (module_info **)&sATA }, 353 { B_DEVICE_MANAGER_MODULE_NAME, (module_info **)&sDeviceManager }, 354 { ATA_ADAPTER_MODULE_NAME, (module_info **)&sATAAdapter }, 355 {} 356 }; 357 358 static ata_controller_interface sChannelInterface = { 359 { 360 { 361 CHANNEL_MODULE_NAME, 362 0, 363 NULL 364 }, 365 366 NULL, 367 NULL, 368 channel_init, 369 channel_uninit, 370 NULL, 371 NULL, 372 channel_removed, 373 }, 374 375 channel_set, 376 377 task_file_write, 378 task_file_read, 379 380 altstatus_read, 381 device_control_write, 382 383 pio_write, 384 pio_read, 385 386 dma_prepare, 387 dma_start, 388 dma_finish, 389 }; 390 391 static driver_module_info sControllerInterface = { 392 { 393 CONTROLLER_MODULE_NAME, 394 0, 395 NULL 396 }, 397 398 controller_supports, 399 controller_probe, 400 controller_init, 401 controller_uninit, 402 NULL, // register child devices 403 NULL, // rescan 404 controller_removed, 405 }; 406 407 module_info *modules[] = { 408 (module_info *)&sControllerInterface, 409 (module_info *)&sChannelInterface, 410 NULL 411 }; 412