1 /* 2 * Copyright 2008-2010, Axel Dörfler, axeld@pinc-software.de. 3 * Copyright 2011-2016, Haiku, Inc. All Rights Reserved. 4 * Distributed under the terms of the MIT License. 5 * 6 * Authors: 7 * Axel Dörfler, axeld@pinc-software.de 8 * Jerome Duval, jerome.duval@gmail.com 9 * Adrien Destugues, pulkomandy@gmail.com 10 * Michael Lotz, mmlr@mlotz.ch 11 * Alexander von Gluck IV, kallisti5@unixzen.com 12 */ 13 14 15 #include <AreaKeeper.h> 16 #include <intel_extreme.h> 17 18 #include <stdlib.h> 19 20 #include <AGP.h> 21 #include <KernelExport.h> 22 #include <PCI.h> 23 24 #include <new> 25 26 27 #define TRACE_INTEL 28 #ifdef TRACE_INTEL 29 # define TRACE(x...) dprintf("intel_gart: " x) 30 #else 31 # define TRACE(x...) ; 32 #endif 33 #define ERROR(x...) dprintf("intel_gart: " x) 34 35 36 /* read and write to PCI config space */ 37 #define get_pci_config(info, offset, size) \ 38 (sPCI->read_pci_config((info).bus, (info).device, (info).function, \ 39 (offset), (size))) 40 #define set_pci_config(info, offset, size, value) \ 41 (sPCI->write_pci_config((info).bus, (info).device, (info).function, \ 42 (offset), (size), (value))) 43 #define write32(address, data) \ 44 (*((volatile uint32*)(address)) = (data)) 45 #define read32(address) \ 46 (*((volatile uint32*)(address))) 47 48 49 // PCI "Host bridge" is most cases :-) 50 const struct supported_device { 51 uint32 bridge_id; 52 uint32 display_id; 53 int32 type; 54 const char *name; 55 } kSupportedDevices[] = { 56 {0x3575, 0x3577, INTEL_GROUP_83x, "i830GM"}, 57 {0x2560, 0x2562, INTEL_GROUP_83x, "i845G"}, 58 {0x3580, 0x3582, INTEL_GROUP_85x, "i855G"}, 59 {0x358c, 0x358e, INTEL_GROUP_85x, "i855G"}, 60 {0x2570, 0x2572, INTEL_GROUP_85x, "i865G"}, 61 62 // {0x2792, INTEL_GROUP_91x, "i910"}, 63 // {0x258a, INTEL_GROUP_91x, "i915"}, 64 {0x2580, 0x2582, INTEL_MODEL_915, "i915G"}, 65 {0x2590, 0x2592, INTEL_MODEL_915M, "i915GM"}, 66 {0x2770, 0x2772, INTEL_MODEL_945, "i945G"}, 67 {0x27a0, 0x27a2, INTEL_MODEL_945M, "i945GM"}, 68 {0x27ac, 0x27ae, INTEL_MODEL_945M, "i945GME"}, 69 70 {0x2970, 0x2972, INTEL_MODEL_965, "i946GZ"}, 71 {0x2980, 0x2982, INTEL_MODEL_965, "G35"}, 72 {0x2990, 0x2992, INTEL_MODEL_965, "i965Q"}, 73 {0x29a0, 0x29a2, INTEL_MODEL_965, "i965G"}, 74 {0x2a00, 0x2a02, INTEL_MODEL_965, "i965GM"}, 75 {0x2a10, 0x2a12, INTEL_MODEL_965, "i965GME"}, 76 77 {0x29b0, 0x29b2, INTEL_MODEL_G33, "G33"}, 78 {0x29c0, 0x29c2, INTEL_MODEL_G33, "Q35"}, 79 {0x29d0, 0x29d2, INTEL_MODEL_G33, "Q33"}, 80 81 {0x2a40, 0x2a42, INTEL_MODEL_GM45, "GM45"}, 82 {0x2e00, 0x2e02, INTEL_MODEL_G45, "IGD"}, 83 {0x2e10, 0x2e12, INTEL_MODEL_G45, "Q45"}, 84 {0x2e20, 0x2e22, INTEL_MODEL_G45, "G45"}, 85 {0x2e30, 0x2e32, INTEL_MODEL_G45, "G41"}, 86 {0x2e40, 0x2e42, INTEL_MODEL_G45, "B43"}, 87 {0x2e90, 0x2e92, INTEL_MODEL_G45, "B43"}, 88 89 {0xa000, 0xa001, INTEL_MODEL_PINE, "Atom D4xx"}, 90 {0xa000, 0xa002, INTEL_MODEL_PINE, "Atom D5xx"}, 91 {0xa010, 0xa011, INTEL_MODEL_PINEM, "Atom N4xx"}, 92 {0xa010, 0xa012, INTEL_MODEL_PINEM, "Atom N5xx"}, 93 94 {0x0040, 0x0042, INTEL_MODEL_ILKG, "IronLake Desktop"}, 95 {0x0044, 0x0046, INTEL_MODEL_ILKGM, "IronLake Mobile"}, 96 {0x0062, 0x0046, INTEL_MODEL_ILKGM, "IronLake Mobile"}, 97 {0x006a, 0x0046, INTEL_MODEL_ILKGM, "IronLake Mobile"}, 98 99 {0x0100, 0x0102, INTEL_MODEL_SNBG, "SandyBridge Desktop GT1"}, 100 {0x0100, 0x0112, INTEL_MODEL_SNBG, "SandyBridge Desktop GT2"}, 101 {0x0100, 0x0122, INTEL_MODEL_SNBG, "SandyBridge Desktop GT2+"}, 102 {0x0104, 0x0106, INTEL_MODEL_SNBGM, "SandyBridge Mobile GT1"}, 103 {0x0104, 0x0116, INTEL_MODEL_SNBGM, "SandyBridge Mobile GT2"}, 104 {0x0104, 0x0126, INTEL_MODEL_SNBGM, "SandyBridge Mobile GT2+"}, 105 {0x0108, 0x010a, INTEL_MODEL_SNBGS, "SandyBridge Server"}, 106 107 {0x0150, 0x0152, INTEL_MODEL_IVBG, "IvyBridge Desktop GT1"}, 108 {0x0150, 0x0162, INTEL_MODEL_IVBG, "IvyBridge Desktop GT2"}, 109 {0x0154, 0x0156, INTEL_MODEL_IVBGM, "IvyBridge Mobile GT1"}, 110 {0x0154, 0x0166, INTEL_MODEL_IVBGM, "IvyBridge Mobile GT2"}, 111 {0x0158, 0x015a, INTEL_MODEL_IVBGS, "IvyBridge Server GT1"}, 112 {0x0158, 0x016a, INTEL_MODEL_IVBGS, "IvyBridge Server GT2"}, 113 114 {0x0c00, 0x0412, INTEL_MODEL_HAS, "Haswell Desktop"}, 115 {0x0c04, 0x0416, INTEL_MODEL_HASM, "Haswell Mobile"}, 116 {0x0d04, 0x0d26, INTEL_MODEL_HASM, "Haswell Mobile"}, 117 {0x0a04, 0x0a16, INTEL_MODEL_HASM, "Haswell Mobile"}, 118 119 #if 0 120 // XXX: 0x0f00 only confirmed on 0x0f30, 0x0f31 121 {0x0f00, 0x0f30, INTEL_MODEL_VLVM, "ValleyView Mobile"}, 122 {0x0f00, 0x0f31, INTEL_MODEL_VLVM, "ValleyView Mobile"}, 123 {0x0f00, 0x0f32, INTEL_MODEL_VLVM, "ValleyView Mobile"}, 124 {0x0f00, 0x0f33, INTEL_MODEL_VLVM, "ValleyView Mobile"}, 125 #endif 126 127 // XXX: 0x1604 only confirmed on 0x1616 128 {0x1604, 0x1606, INTEL_MODEL_BDWM, "Broadwell GT1 ULT"}, 129 {0x1604, 0x160b, INTEL_MODEL_BDWM, "Broadwell GT1 Iris"}, 130 {0x1604, 0x160e, INTEL_MODEL_BDWM, "Broadwell GT1 ULX"}, 131 {0x1604, 0x1602, INTEL_MODEL_BDWM, "Broadwell GT1 ULT"}, 132 {0x1604, 0x160a, INTEL_MODEL_BDWS, "Broadwell GT1 Server"}, 133 {0x1604, 0x160d, INTEL_MODEL_BDW, "Broadwell GT1 Workstation"}, 134 {0x1604, 0x1616, INTEL_MODEL_BDWM, "Broadwell GT2 ULT"}, 135 {0x1604, 0x161b, INTEL_MODEL_BDWM, "Broadwell GT2 ULT"}, 136 {0x1604, 0x161e, INTEL_MODEL_BDWM, "Broadwell GT2 ULX"}, 137 {0x1604, 0x1612, INTEL_MODEL_BDWM, "Broadwell GT2 Halo"}, 138 {0x1604, 0x161a, INTEL_MODEL_BDWS, "Broadwell GT2 Server"}, 139 {0x1604, 0x161d, INTEL_MODEL_BDW, "Broadwell GT2 Workstation"}, 140 {0x1604, 0x1626, INTEL_MODEL_BDWM, "Broadwell GT3 ULT"}, 141 {0x1604, 0x162b, INTEL_MODEL_BDWM, "Broadwell GT3 Iris"}, 142 {0x1604, 0x162e, INTEL_MODEL_BDWM, "Broadwell GT3 ULX"}, 143 {0x1604, 0x1622, INTEL_MODEL_BDWM, "Broadwell GT3 ULT"}, 144 {0x1604, 0x162a, INTEL_MODEL_BDWS, "Broadwell GT3 Server"}, 145 {0x1604, 0x162d, INTEL_MODEL_BDW, "Broadwell GT3 Workstation"}, 146 147 // XXX: 0x1904 only confirmed on 0x1916 148 {0x1904, 0x1902, INTEL_MODEL_SKY, "Skylake GT1"}, 149 {0x1904, 0x1906, INTEL_MODEL_SKYM, "Skylake GT1"}, 150 {0x1904, 0x190a, INTEL_MODEL_SKYS, "Skylake GT1"}, 151 {0x1904, 0x190b, INTEL_MODEL_SKY, "Skylake GT1"}, 152 {0x1904, 0x190e, INTEL_MODEL_SKYM, "Skylake GT1"}, 153 {0x191f, 0x1912, INTEL_MODEL_SKY, "Skylake GT2"}, // confirmed 154 {0x1904, 0x1916, INTEL_MODEL_SKYM, "Skylake GT2"}, 155 {0x1904, 0x191a, INTEL_MODEL_SKYS, "Skylake GT2"}, 156 {0x1904, 0x191b, INTEL_MODEL_SKY, "Skylake GT2"}, 157 {0x1904, 0x191d, INTEL_MODEL_SKY, "Skylake GT2"}, 158 {0x1904, 0x191e, INTEL_MODEL_SKYM, "Skylake GT2"}, 159 {0x1904, 0x1921, INTEL_MODEL_SKYM, "Skylake GT2F"}, 160 {0x1904, 0x1926, INTEL_MODEL_SKYM, "Skylake GT3"}, 161 {0x1904, 0x192a, INTEL_MODEL_SKYS, "Skylake GT3"}, 162 {0x1904, 0x192b, INTEL_MODEL_SKY, "Skylake GT3"}, 163 164 {0x5904, 0x5906, INTEL_MODEL_KBY, "Kabylake ULT GT1"}, 165 {0x590f, 0x5902, INTEL_MODEL_KBY, "Kabylake DT GT1"}, 166 {0x5904, 0x5916, INTEL_MODEL_KBYM, "Kabylake ULT GT2"}, 167 {0x590c, 0x5916, INTEL_MODEL_KBYM, "Kabylake ULT GT2"}, 168 {0x5904, 0x5921, INTEL_MODEL_KBYM, "Kabylake ULT GT2F"}, 169 {0x590c, 0x591c, INTEL_MODEL_KBY, "Kabylake ULX GT2"}, 170 {0x590c, 0x591e, INTEL_MODEL_KBY, "Kabylake ULX GT2"}, 171 {0x591f, 0x5912, INTEL_MODEL_KBY, "Kabylake DT GT2"}, 172 {0x5914, 0x5917, INTEL_MODEL_KBYM, "Kabylake Mobile GT2"}, 173 {0x5910, 0x591b, INTEL_MODEL_KBYM, "Kabylake Halo GT2"}, 174 {0x5918, 0x591d, INTEL_MODEL_KBY, "Kabylake WKS GT2"}, 175 {0x5904, 0x5926, INTEL_MODEL_KBY, "Kabylake ULT GT3"}, 176 {0x5904, 0x5927, INTEL_MODEL_KBY, "Kabylake ULT GT3"}, 177 178 {0x3e0f, 0x3e90, INTEL_MODEL_CFL, "CoffeeLake GT1"}, 179 {0x3e0f, 0x3e93, INTEL_MODEL_CFL, "CoffeeLake GT1"}, 180 {0x3e1f, 0x3e91, INTEL_MODEL_CFL, "CoffeeLake GT2"}, 181 {0x3ec2, 0x3e92, INTEL_MODEL_CFL, "CoffeeLake GT2"}, 182 {0x3e18, 0x3e96, INTEL_MODEL_CFL, "CoffeeLake GT2"}, 183 {0x3e30, 0x3e98, INTEL_MODEL_CFL, "CoffeeLake GT2"}, 184 {0x3e31, 0x3e9a, INTEL_MODEL_CFL, "CoffeeLake GT2"}, 185 {0x3ec4, 0x3e9b, INTEL_MODEL_CFLM, "CoffeeLake Halo GT2"}, 186 {0x3e10, 0x3eab, INTEL_MODEL_CFLM, "CoffeeLake Halo GT2"}, 187 {0x3ec4, 0x3eab, INTEL_MODEL_CFLM, "CoffeeLake Halo GT2"}, 188 {0x3ed0, 0x3ea5, INTEL_MODEL_CFL, "CoffeeLake GT3"}, 189 {0x3ed0, 0x3ea6, INTEL_MODEL_CFL, "CoffeeLake GT3"}, 190 191 {0x4e22, 0x4e55, INTEL_MODEL_JSL, "JasperLake"}, 192 {0x4e24, 0x4e55, INTEL_MODEL_JSL, "JasperLake"}, 193 {0x4e12, 0x4e61, INTEL_MODEL_JSL, "JasperLake"}, 194 {0x4e26, 0x4e71, INTEL_MODEL_JSLM, "JasperLake"}, 195 {0x4e28, 0x4e71, INTEL_MODEL_JSLM, "JasperLake"}, 196 197 {0x9a14, 0x9a49, INTEL_MODEL_TGLM, "TigerLake-LP GT2"}, 198 }; 199 200 struct intel_info { 201 pci_info bridge; 202 pci_info display; 203 DeviceType* type; 204 205 uint32* gtt_base; 206 phys_addr_t gtt_physical_base; 207 area_id gtt_area; 208 size_t gtt_entries; 209 size_t gtt_stolen_entries; 210 211 vuint32* registers; 212 area_id registers_area; 213 214 addr_t aperture_base; 215 phys_addr_t aperture_physical_base; 216 area_id aperture_area; 217 size_t aperture_size; 218 size_t aperture_stolen_size; 219 220 phys_addr_t scratch_page; 221 area_id scratch_area; 222 }; 223 224 static intel_info sInfo; 225 static pci_module_info* sPCI; 226 227 228 static bool 229 has_display_device(pci_info &info, uint32 deviceID) 230 { 231 for (uint32 index = 0; sPCI->get_nth_pci_info(index, &info) == B_OK; 232 index++) { 233 if (info.vendor_id != VENDOR_ID_INTEL 234 || info.device_id != deviceID 235 || info.class_base != PCI_display) 236 continue; 237 238 return true; 239 } 240 241 return false; 242 } 243 244 245 static uint16 246 gtt_memory_config(intel_info &info) 247 { 248 uint8 controlRegister = INTEL_GRAPHICS_MEMORY_CONTROL; 249 if (info.type->Generation() >= 6) 250 controlRegister = SNB_GRAPHICS_MEMORY_CONTROL; 251 252 return get_pci_config(info.bridge, controlRegister, 2); 253 } 254 255 256 static size_t 257 determine_gtt_stolen(intel_info &info) 258 { 259 uint16 memoryConfig = gtt_memory_config(info); 260 size_t memorySize = 1 << 20; // 1 MB 261 262 if (info.type->InGroup(INTEL_GROUP_83x)) { 263 // Older chips 264 switch (memoryConfig & STOLEN_MEMORY_MASK) { 265 case i830_LOCAL_MEMORY_ONLY: 266 // TODO: determine its size! 267 ERROR("getting local memory size not implemented.\n"); 268 break; 269 case i830_STOLEN_512K: 270 memorySize >>= 1; 271 break; 272 case i830_STOLEN_1M: 273 // default case 274 break; 275 case i830_STOLEN_8M: 276 memorySize *= 8; 277 break; 278 } 279 } else if (info.type->InGroup(INTEL_GROUP_SNB) 280 || info.type->InGroup(INTEL_GROUP_IVB) 281 || info.type->InGroup(INTEL_GROUP_HAS)) { 282 switch (memoryConfig & SNB_STOLEN_MEMORY_MASK) { 283 case SNB_STOLEN_MEMORY_32MB: 284 memorySize *= 32; 285 break; 286 case SNB_STOLEN_MEMORY_64MB: 287 memorySize *= 64; 288 break; 289 case SNB_STOLEN_MEMORY_96MB: 290 memorySize *= 96; 291 break; 292 case SNB_STOLEN_MEMORY_128MB: 293 memorySize *= 128; 294 break; 295 case SNB_STOLEN_MEMORY_160MB: 296 memorySize *= 160; 297 break; 298 case SNB_STOLEN_MEMORY_192MB: 299 memorySize *= 192; 300 break; 301 case SNB_STOLEN_MEMORY_224MB: 302 memorySize *= 224; 303 break; 304 case SNB_STOLEN_MEMORY_256MB: 305 memorySize *= 256; 306 break; 307 case SNB_STOLEN_MEMORY_288MB: 308 memorySize *= 288; 309 break; 310 case SNB_STOLEN_MEMORY_320MB: 311 memorySize *= 320; 312 break; 313 case SNB_STOLEN_MEMORY_352MB: 314 memorySize *= 352; 315 break; 316 case SNB_STOLEN_MEMORY_384MB: 317 memorySize *= 384; 318 break; 319 case SNB_STOLEN_MEMORY_416MB: 320 memorySize *= 416; 321 break; 322 case SNB_STOLEN_MEMORY_448MB: 323 memorySize *= 448; 324 break; 325 case SNB_STOLEN_MEMORY_480MB: 326 memorySize *= 480; 327 break; 328 case SNB_STOLEN_MEMORY_512MB: 329 memorySize *= 512; 330 break; 331 } 332 } else if (info.type->InGroup(INTEL_GROUP_BDW) 333 || info.type->InFamily(INTEL_FAMILY_LAKE)) { 334 switch (memoryConfig & BDW_STOLEN_MEMORY_MASK) { 335 case BDW_STOLEN_MEMORY_32MB: 336 memorySize *= 32; 337 break; 338 case BDW_STOLEN_MEMORY_64MB: 339 memorySize *= 64; 340 break; 341 case BDW_STOLEN_MEMORY_96MB: 342 memorySize *= 96; 343 break; 344 case BDW_STOLEN_MEMORY_128MB: 345 memorySize *= 128; 346 break; 347 case BDW_STOLEN_MEMORY_160MB: 348 memorySize *= 160; 349 break; 350 case BDW_STOLEN_MEMORY_192MB: 351 memorySize *= 192; 352 break; 353 case BDW_STOLEN_MEMORY_224MB: 354 memorySize *= 224; 355 break; 356 case BDW_STOLEN_MEMORY_256MB: 357 memorySize *= 256; 358 break; 359 case BDW_STOLEN_MEMORY_288MB: 360 memorySize *= 288; 361 break; 362 case BDW_STOLEN_MEMORY_320MB: 363 memorySize *= 320; 364 break; 365 case BDW_STOLEN_MEMORY_352MB: 366 memorySize *= 352; 367 break; 368 case BDW_STOLEN_MEMORY_384MB: 369 memorySize *= 384; 370 break; 371 case BDW_STOLEN_MEMORY_416MB: 372 memorySize *= 416; 373 break; 374 case BDW_STOLEN_MEMORY_448MB: 375 memorySize *= 448; 376 break; 377 case BDW_STOLEN_MEMORY_480MB: 378 memorySize *= 480; 379 break; 380 case BDW_STOLEN_MEMORY_512MB: 381 memorySize *= 512; 382 break; 383 case BDW_STOLEN_MEMORY_1024MB: 384 memorySize *= 1024; 385 break; 386 case BDW_STOLEN_MEMORY_1536MB: 387 memorySize *= 1536; 388 break; 389 } 390 if(info.type->InGroup(INTEL_GROUP_BDW)) { 391 if((memoryConfig & BDW_STOLEN_MEMORY_MASK) == BDW_STOLEN_MEMORY_2016MB) { 392 memorySize *= 2016; 393 } 394 } else if(info.type->InFamily(INTEL_FAMILY_LAKE)) { 395 switch(memoryConfig & BDW_STOLEN_MEMORY_MASK) { 396 case SKL_STOLEN_MEMORY_4MB: 397 memorySize *= 4; 398 break; 399 case SKL_STOLEN_MEMORY_8MB: 400 memorySize *= 8; 401 break; 402 case SKL_STOLEN_MEMORY_12MB: 403 memorySize *= 12; 404 break; 405 case SKL_STOLEN_MEMORY_16MB: 406 memorySize *= 16; 407 break; 408 case SKL_STOLEN_MEMORY_20MB: 409 memorySize *= 20; 410 break; 411 case SKL_STOLEN_MEMORY_24MB: 412 memorySize *= 24; 413 break; 414 case SKL_STOLEN_MEMORY_28MB: 415 memorySize *= 28; 416 break; 417 case SKL_STOLEN_MEMORY_32MB: 418 memorySize *= 32; 419 break; 420 case SKL_STOLEN_MEMORY_36MB: 421 memorySize *= 36; 422 break; 423 case SKL_STOLEN_MEMORY_40MB: 424 memorySize *= 40; 425 break; 426 case SKL_STOLEN_MEMORY_44MB: 427 memorySize *= 44; 428 break; 429 case SKL_STOLEN_MEMORY_48MB: 430 memorySize *= 48; 431 break; 432 case SKL_STOLEN_MEMORY_52MB: 433 memorySize *= 52; 434 break; 435 case SKL_STOLEN_MEMORY_56MB: 436 memorySize *= 56; 437 break; 438 case SKL_STOLEN_MEMORY_60MB: 439 memorySize *= 60; 440 break; 441 } 442 } 443 } else if (info.type->InGroup(INTEL_GROUP_85x) 444 || info.type->InFamily(INTEL_FAMILY_9xx) 445 || info.type->InGroup(INTEL_GROUP_ILK)) { 446 switch (memoryConfig & STOLEN_MEMORY_MASK) { 447 case i855_STOLEN_MEMORY_4M: 448 memorySize *= 4; 449 break; 450 case i855_STOLEN_MEMORY_8M: 451 memorySize *= 8; 452 break; 453 case i855_STOLEN_MEMORY_16M: 454 memorySize *= 16; 455 break; 456 case i855_STOLEN_MEMORY_32M: 457 memorySize *= 32; 458 break; 459 case i855_STOLEN_MEMORY_48M: 460 memorySize *= 48; 461 break; 462 case i855_STOLEN_MEMORY_64M: 463 memorySize *= 64; 464 break; 465 case i855_STOLEN_MEMORY_128M: 466 memorySize *= 128; 467 break; 468 case i855_STOLEN_MEMORY_256M: 469 memorySize *= 256; 470 break; 471 case G4X_STOLEN_MEMORY_96MB: 472 memorySize *= 96; 473 break; 474 case G4X_STOLEN_MEMORY_160MB: 475 memorySize *= 160; 476 break; 477 case G4X_STOLEN_MEMORY_224MB: 478 memorySize *= 224; 479 break; 480 case G4X_STOLEN_MEMORY_352MB: 481 memorySize *= 352; 482 break; 483 } 484 } else { 485 // TODO: error out! 486 memorySize = 4096; 487 } 488 return memorySize - 4096; 489 } 490 491 492 static size_t 493 determine_gtt_size(intel_info &info) 494 { 495 uint16 memoryConfig = gtt_memory_config(info); 496 size_t gttSize = 0; 497 498 if (info.type->IsModel(INTEL_MODEL_965)) { 499 switch (memoryConfig & i965_GTT_MASK) { 500 case i965_GTT_128K: 501 gttSize = 128 << 10; 502 break; 503 case i965_GTT_256K: 504 gttSize = 256 << 10; 505 break; 506 case i965_GTT_512K: 507 gttSize = 512 << 10; 508 break; 509 } 510 } else if (info.type->IsModel(INTEL_MODEL_G33) 511 || info.type->InGroup(INTEL_GROUP_PIN)) { 512 switch (memoryConfig & G33_GTT_MASK) { 513 case G33_GTT_1M: 514 gttSize = 1 << 20; 515 break; 516 case G33_GTT_2M: 517 gttSize = 2 << 20; 518 break; 519 } 520 } else if (info.type->InGroup(INTEL_GROUP_G4x) 521 || info.type->InGroup(INTEL_GROUP_ILK)) { 522 switch (memoryConfig & G4X_GTT_MASK) { 523 case G4X_GTT_NONE: 524 gttSize = 0; 525 break; 526 case G4X_GTT_1M_NO_IVT: 527 gttSize = 1 << 20; 528 break; 529 case G4X_GTT_2M_NO_IVT: 530 case G4X_GTT_2M_IVT: 531 gttSize = 2 << 20; 532 break; 533 case G4X_GTT_3M_IVT: 534 gttSize = 3 << 20; 535 break; 536 case G4X_GTT_4M_IVT: 537 gttSize = 4 << 20; 538 break; 539 } 540 } else if (info.type->InGroup(INTEL_GROUP_SNB) 541 || info.type->InGroup(INTEL_GROUP_IVB) 542 || info.type->InGroup(INTEL_GROUP_HAS)) { 543 switch (memoryConfig & SNB_GTT_SIZE_MASK) { 544 case SNB_GTT_SIZE_NONE: 545 gttSize = 0; 546 break; 547 case SNB_GTT_SIZE_1MB: 548 gttSize = 1 << 20; 549 break; 550 case SNB_GTT_SIZE_2MB: 551 gttSize = 2 << 20; 552 break; 553 } 554 } else if (info.type->InGroup(INTEL_GROUP_BDW) 555 || info.type->InFamily(INTEL_FAMILY_LAKE)) { 556 switch (memoryConfig & BDW_GTT_SIZE_MASK) { 557 case BDW_GTT_SIZE_NONE: 558 gttSize = 0; 559 break; 560 case BDW_GTT_SIZE_2MB: 561 gttSize = 2 << 20; 562 break; 563 case BDW_GTT_SIZE_4MB: 564 gttSize = 4 << 20; 565 break; 566 case BDW_GTT_SIZE_8MB: 567 gttSize = 8 << 20; 568 break; 569 } 570 } else { 571 // older models have the GTT as large as their frame buffer mapping 572 // TODO: check if the i9xx version works with the i8xx chips as well 573 size_t frameBufferSize = 0; 574 if (info.type->InFamily(INTEL_FAMILY_8xx)) { 575 if (info.type->InGroup(INTEL_GROUP_83x) 576 && (memoryConfig & MEMORY_MASK) == i830_FRAME_BUFFER_64M) 577 frameBufferSize = 64 << 20; 578 else 579 frameBufferSize = 128 << 20; 580 } else if (info.type->Generation() >= 3) { 581 frameBufferSize = info.display.u.h0.base_register_sizes[2]; 582 } 583 584 TRACE("frame buffer size %lu MB\n", frameBufferSize >> 20); 585 gttSize = frameBufferSize / 1024; 586 } 587 return gttSize; 588 } 589 590 591 static void 592 set_gtt_entry(intel_info &info, uint32 offset, phys_addr_t physicalAddress) 593 { 594 if (info.type->Generation() >= 8) { 595 // CHV + BXT 596 physicalAddress |= (physicalAddress >> 28) & 0x07f0; 597 // TODO: cache control? 598 } else if (info.type->Generation() >= 6) { 599 // SandyBridge, IronLake, IvyBridge, Haswell 600 physicalAddress |= (physicalAddress >> 28) & 0x0ff0; 601 physicalAddress |= 0x02; // cache control, l3 cacheable 602 } else if (info.type->Generation() >= 4) { 603 // Intel 9xx minus 91x, 94x, G33 604 // possible high bits are stored in the lower end 605 physicalAddress |= (physicalAddress >> 28) & 0x00f0; 606 // TODO: cache control? 607 } 608 609 // TODO: this is not 64-bit safe! 610 write32(info.gtt_base + (offset >> GTT_PAGE_SHIFT), 611 (uint32)physicalAddress | GTT_ENTRY_VALID); 612 } 613 614 615 static void 616 intel_unmap(intel_info &info) 617 { 618 delete_area(info.registers_area); 619 delete_area(info.gtt_area); 620 delete_area(info.scratch_area); 621 delete_area(info.aperture_area); 622 info.aperture_size = 0; 623 } 624 625 626 static status_t 627 intel_map(intel_info &info) 628 { 629 int fbIndex = 0; 630 int mmioIndex = 1; 631 if (info.type->Generation() >= 3) { 632 // for some reason Intel saw the need to change the order of the 633 // mappings with the introduction of the i9xx family 634 mmioIndex = 0; 635 fbIndex = 2; 636 } 637 638 phys_addr_t addr = info.display.u.h0.base_registers[mmioIndex]; 639 uint64 barSize = info.display.u.h0.base_register_sizes[mmioIndex]; 640 if ((info.display.u.h0.base_register_flags[mmioIndex] & PCI_address_type) == PCI_address_type_64) { 641 addr |= (uint64)info.display.u.h0.base_registers[mmioIndex + 1] << 32; 642 barSize |= (uint64)info.display.u.h0.base_register_sizes[mmioIndex + 1] << 32; 643 } 644 645 AreaKeeper mmioMapper; 646 info.registers_area = mmioMapper.Map("intel GMCH mmio", addr, barSize, 647 B_ANY_KERNEL_ADDRESS, B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, (void**)&info.registers); 648 649 if (mmioMapper.InitCheck() < B_OK) { 650 ERROR("could not map memory I/O!\n"); 651 return info.registers_area; 652 } 653 654 // make sure bus master, memory-mapped I/O, and frame buffer is enabled 655 set_pci_config(info.display, PCI_command, 2, 656 get_pci_config(info.display, PCI_command, 2) 657 | PCI_command_io | PCI_command_memory | PCI_command_master); 658 659 void* scratchAddress; 660 AreaKeeper scratchCreator; 661 info.scratch_area = scratchCreator.Create("intel GMCH scratch", 662 &scratchAddress, B_ANY_KERNEL_ADDRESS, B_PAGE_SIZE, B_FULL_LOCK, 663 B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA); 664 if (scratchCreator.InitCheck() < B_OK) { 665 ERROR("could not create scratch page!\n"); 666 return info.scratch_area; 667 } 668 669 physical_entry entry; 670 if (get_memory_map(scratchAddress, B_PAGE_SIZE, &entry, 1) != B_OK) 671 return B_ERROR; 672 673 // TODO: Review these 674 if (info.type->InFamily(INTEL_FAMILY_8xx)) { 675 info.gtt_physical_base = read32(info.registers 676 + INTEL_PAGE_TABLE_CONTROL) & ~PAGE_TABLE_ENABLED; 677 if (info.gtt_physical_base == 0) { 678 // TODO: not sure how this is supposed to work under Linux/FreeBSD, 679 // but on my i865, this code is needed for Haiku. 680 ERROR("Use GTT address fallback.\n"); 681 info.gtt_physical_base = info.display.u.h0.base_registers[mmioIndex] 682 + i830_GTT_BASE; 683 } 684 } else if (info.type->InGroup(INTEL_GROUP_91x)) { 685 info.gtt_physical_base = get_pci_config(info.display, i915_GTT_BASE, 4); 686 } else { 687 // 945+? 688 info.gtt_physical_base = addr + (2UL << 20); 689 } 690 691 size_t gttSize = determine_gtt_size(info); 692 size_t stolenSize = determine_gtt_stolen(info); 693 694 info.gtt_entries = gttSize / 4096; 695 info.gtt_stolen_entries = stolenSize / 4096; 696 697 TRACE("GTT base %" B_PRIxPHYSADDR ", size %lu, entries %lu, stolen %lu\n", 698 info.gtt_physical_base, gttSize, info.gtt_entries, stolenSize); 699 700 AreaKeeper gttMapper; 701 info.gtt_area = gttMapper.Map("intel GMCH gtt", 702 info.gtt_physical_base, gttSize, B_ANY_KERNEL_ADDRESS, 703 B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, (void**)&info.gtt_base); 704 if (gttMapper.InitCheck() < B_OK) { 705 ERROR("could not map GTT!\n"); 706 return info.gtt_area; 707 } 708 709 info.aperture_physical_base = info.display.u.h0.base_registers[fbIndex]; 710 info.aperture_stolen_size = stolenSize; 711 if ((info.display.u.h0.base_register_flags[fbIndex] & PCI_address_type) == PCI_address_type_64) { 712 info.aperture_physical_base |= (uint64)info.display.u.h0.base_registers[fbIndex + 1] << 32; 713 if (info.aperture_size == 0) { 714 info.aperture_size = info.display.u.h0.base_register_sizes[fbIndex] 715 |= (uint64)info.display.u.h0.base_register_sizes[fbIndex + 1] << 32; 716 } 717 } else if (info.aperture_size == 0) 718 info.aperture_size = info.display.u.h0.base_register_sizes[fbIndex]; 719 720 ERROR("detected %ld MB of stolen memory, aperture size %ld MB, " 721 "GTT size %ld KB\n", (stolenSize + (1023 << 10)) >> 20, 722 info.aperture_size >> 20, gttSize >> 10); 723 724 ERROR("GTT base = 0x%" B_PRIxPHYSADDR "\n", info.gtt_physical_base); 725 ERROR("MMIO base = 0x%" B_PRIx32 "\n", 726 info.display.u.h0.base_registers[mmioIndex]); 727 ERROR("GMR base = 0x%" B_PRIxPHYSADDR "\n", info.aperture_physical_base); 728 729 AreaKeeper apertureMapper; 730 info.aperture_area = apertureMapper.Map("intel graphics aperture", 731 info.aperture_physical_base, info.aperture_size, 732 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 733 B_READ_AREA | B_WRITE_AREA, (void**)&info.aperture_base); 734 if (apertureMapper.InitCheck() < B_OK) { 735 // try again without write combining 736 ERROR("enabling write combined mode failed.\n"); 737 738 info.aperture_area = apertureMapper.Map("intel graphics aperture", 739 info.aperture_physical_base, info.aperture_size, 740 B_ANY_KERNEL_BLOCK_ADDRESS, B_READ_AREA | B_WRITE_AREA, 741 (void**)&info.aperture_base); 742 } 743 if (apertureMapper.InitCheck() < B_OK) { 744 ERROR("could not map graphics aperture!\n"); 745 return info.aperture_area; 746 } 747 748 info.scratch_page = entry.address; 749 750 gttMapper.Detach(); 751 mmioMapper.Detach(); 752 scratchCreator.Detach(); 753 apertureMapper.Detach(); 754 755 return B_OK; 756 } 757 758 759 // #pragma mark - module interface 760 761 762 status_t 763 intel_create_aperture(uint8 bus, uint8 device, uint8 function, size_t size, 764 void** _aperture) 765 { 766 // TODO: we currently only support a single AGP bridge! 767 if ((bus != sInfo.bridge.bus || device != sInfo.bridge.device 768 || function != sInfo.bridge.function) 769 && (bus != sInfo.display.bus || device != sInfo.display.device 770 || function != sInfo.display.function)) 771 return B_BAD_VALUE; 772 773 sInfo.aperture_size = size; 774 775 if (intel_map(sInfo) < B_OK) 776 return B_ERROR; 777 778 uint16 gmchControl = get_pci_config(sInfo.bridge, 779 INTEL_GRAPHICS_MEMORY_CONTROL, 2) | MEMORY_CONTROL_ENABLED; 780 set_pci_config(sInfo.bridge, INTEL_GRAPHICS_MEMORY_CONTROL, 2, gmchControl); 781 782 write32(sInfo.registers + INTEL_PAGE_TABLE_CONTROL, 783 sInfo.gtt_physical_base | PAGE_TABLE_ENABLED); 784 read32(sInfo.registers + INTEL_PAGE_TABLE_CONTROL); 785 786 if (sInfo.scratch_page != 0) { 787 for (size_t i = sInfo.gtt_stolen_entries; i < sInfo.gtt_entries; i++) { 788 set_gtt_entry(sInfo, i << GTT_PAGE_SHIFT, sInfo.scratch_page); 789 } 790 read32(sInfo.gtt_base + sInfo.gtt_entries - 1); 791 } 792 793 asm("wbinvd;"); 794 795 *_aperture = NULL; 796 return B_OK; 797 } 798 799 800 void 801 intel_delete_aperture(void* aperture) 802 { 803 intel_unmap(sInfo); 804 } 805 806 807 static status_t 808 intel_get_aperture_info(void* aperture, aperture_info* info) 809 { 810 if (info == NULL) 811 return B_BAD_VALUE; 812 813 info->base = sInfo.aperture_base; 814 info->physical_base = sInfo.aperture_physical_base; 815 info->size = sInfo.aperture_size; 816 info->reserved_size = sInfo.aperture_stolen_size; 817 818 return B_OK; 819 } 820 821 822 status_t 823 intel_set_aperture_size(void* aperture, size_t size) 824 { 825 return B_ERROR; 826 } 827 828 829 static status_t 830 intel_bind_page(void* aperture, uint32 offset, phys_addr_t physicalAddress) 831 { 832 //TRACE("bind_page(offset %lx, physical %lx)\n", offset, physicalAddress); 833 834 set_gtt_entry(sInfo, offset, physicalAddress); 835 return B_OK; 836 } 837 838 839 static status_t 840 intel_unbind_page(void* aperture, uint32 offset) 841 { 842 //TRACE("unbind_page(offset %lx)\n", offset); 843 844 if (sInfo.scratch_page != 0) 845 set_gtt_entry(sInfo, offset, sInfo.scratch_page); 846 847 return B_OK; 848 } 849 850 851 void 852 intel_flush_tlbs(void* aperture) 853 { 854 read32(sInfo.gtt_base + sInfo.gtt_entries - 1); 855 asm("wbinvd;"); 856 } 857 858 859 // #pragma mark - 860 861 862 static status_t 863 intel_init() 864 { 865 TRACE("bus manager init\n"); 866 867 if (get_module(B_PCI_MODULE_NAME, (module_info**)&sPCI) != B_OK) 868 return B_ERROR; 869 870 for (uint32 index = 0; sPCI->get_nth_pci_info(index, &sInfo.bridge) == B_OK; 871 index++) { 872 if (sInfo.bridge.vendor_id != VENDOR_ID_INTEL 873 || sInfo.bridge.class_base != PCI_bridge) 874 continue; 875 876 // check device 877 for (uint32 i = 0; i < sizeof(kSupportedDevices) 878 / sizeof(kSupportedDevices[0]); i++) { 879 if (sInfo.bridge.device_id == kSupportedDevices[i].bridge_id) { 880 sInfo.type = new DeviceType(kSupportedDevices[i].type); 881 if (has_display_device(sInfo.display, 882 kSupportedDevices[i].display_id)) { 883 TRACE("found intel bridge\n"); 884 return B_OK; 885 } 886 } 887 } 888 } 889 890 return ENODEV; 891 } 892 893 894 static void 895 intel_uninit() 896 { 897 if (sInfo.type) 898 delete sInfo.type; 899 } 900 901 902 static int32 903 intel_std_ops(int32 op, ...) 904 { 905 switch (op) { 906 case B_MODULE_INIT: 907 return intel_init(); 908 case B_MODULE_UNINIT: 909 intel_uninit(); 910 return B_OK; 911 } 912 913 return B_BAD_VALUE; 914 } 915 916 917 static struct agp_gart_bus_module_info sIntelModuleInfo = { 918 { 919 "busses/agp_gart/intel/v0", 920 0, 921 intel_std_ops 922 }, 923 924 intel_create_aperture, 925 intel_delete_aperture, 926 927 intel_get_aperture_info, 928 intel_set_aperture_size, 929 intel_bind_page, 930 intel_unbind_page, 931 intel_flush_tlbs 932 }; 933 934 module_info* modules[] = { 935 (module_info*)&sIntelModuleInfo, 936 NULL 937 }; 938