1 /* 2 * Copyright 2008-2010, Axel Dörfler, axeld@pinc-software.de. 3 * Copyright 2011-2016, Haiku, Inc. All Rights Reserved. 4 * Distributed under the terms of the MIT License. 5 * 6 * Authors: 7 * Axel Dörfler, axeld@pinc-software.de 8 * Jerome Duval, jerome.duval@gmail.com 9 * Adrien Destugues, pulkomandy@gmail.com 10 * Michael Lotz, mmlr@mlotz.ch 11 * Alexander von Gluck IV, kallisti5@unixzen.com 12 */ 13 14 15 #include <AreaKeeper.h> 16 #include <intel_extreme.h> 17 18 #include <stdlib.h> 19 20 #include <AGP.h> 21 #include <KernelExport.h> 22 #include <PCI.h> 23 24 #include <new> 25 26 27 #define TRACE_INTEL 28 #ifdef TRACE_INTEL 29 # define TRACE(x...) dprintf("intel_gart: " x) 30 #else 31 # define TRACE(x...) ; 32 #endif 33 #define ERROR(x...) dprintf("intel_gart: " x) 34 35 36 /* read and write to PCI config space */ 37 #define get_pci_config(info, offset, size) \ 38 (sPCI->read_pci_config((info).bus, (info).device, (info).function, \ 39 (offset), (size))) 40 #define set_pci_config(info, offset, size, value) \ 41 (sPCI->write_pci_config((info).bus, (info).device, (info).function, \ 42 (offset), (size), (value))) 43 #define write32(address, data) \ 44 (*((volatile uint32*)(address)) = (data)) 45 #define read32(address) \ 46 (*((volatile uint32*)(address))) 47 48 49 // PCI "Host bridge" is most cases :-) 50 const struct supported_device { 51 uint32 bridge_id; 52 uint32 display_id; 53 int32 type; 54 const char *name; 55 } kSupportedDevices[] = { 56 {0x3575, 0x3577, INTEL_GROUP_83x, "i830GM"}, 57 {0x2560, 0x2562, INTEL_GROUP_83x, "i845G"}, 58 {0x3580, 0x3582, INTEL_GROUP_85x, "i855G"}, 59 {0x358c, 0x358e, INTEL_GROUP_85x, "i855G"}, 60 {0x2570, 0x2572, INTEL_GROUP_85x, "i865G"}, 61 62 // {0x2792, INTEL_GROUP_91x, "i910"}, 63 // {0x258a, INTEL_GROUP_91x, "i915"}, 64 {0x2580, 0x2582, INTEL_MODEL_915, "i915G"}, 65 {0x2590, 0x2592, INTEL_MODEL_915M, "i915GM"}, 66 {0x2770, 0x2772, INTEL_MODEL_945, "i945G"}, 67 {0x27a0, 0x27a2, INTEL_MODEL_945M, "i945GM"}, 68 {0x27ac, 0x27ae, INTEL_MODEL_945M, "i945GME"}, 69 70 {0x2970, 0x2972, INTEL_MODEL_965, "i946GZ"}, 71 {0x2980, 0x2982, INTEL_MODEL_965, "G35"}, 72 {0x2990, 0x2992, INTEL_MODEL_965, "i965Q"}, 73 {0x29a0, 0x29a2, INTEL_MODEL_965, "i965G"}, 74 {0x2a00, 0x2a02, INTEL_MODEL_965, "i965GM"}, 75 {0x2a10, 0x2a12, INTEL_MODEL_965, "i965GME"}, 76 77 {0x29b0, 0x29b2, INTEL_MODEL_G33, "G33"}, 78 {0x29c0, 0x29c2, INTEL_MODEL_G33, "Q35"}, 79 {0x29d0, 0x29d2, INTEL_MODEL_G33, "Q33"}, 80 81 {0x2a40, 0x2a42, INTEL_MODEL_GM45, "GM45"}, 82 {0x2e00, 0x2e02, INTEL_MODEL_G45, "IGD"}, 83 {0x2e10, 0x2e12, INTEL_MODEL_G45, "Q45"}, 84 {0x2e20, 0x2e22, INTEL_MODEL_G45, "G45"}, 85 {0x2e30, 0x2e32, INTEL_MODEL_G45, "G41"}, 86 {0x2e40, 0x2e42, INTEL_MODEL_G45, "B43"}, 87 {0x2e90, 0x2e92, INTEL_MODEL_G45, "B43"}, 88 89 {0xa000, 0xa001, INTEL_MODEL_PINE, "Atom D4xx"}, 90 {0xa000, 0xa002, INTEL_MODEL_PINE, "Atom D5xx"}, 91 {0xa010, 0xa011, INTEL_MODEL_PINEM, "Atom N4xx"}, 92 {0xa010, 0xa012, INTEL_MODEL_PINEM, "Atom N5xx"}, 93 94 {0x0040, 0x0042, INTEL_MODEL_ILKG, "IronLake Desktop"}, 95 {0x0044, 0x0046, INTEL_MODEL_ILKGM, "IronLake Mobile"}, 96 {0x0062, 0x0046, INTEL_MODEL_ILKGM, "IronLake Mobile"}, 97 {0x006a, 0x0046, INTEL_MODEL_ILKGM, "IronLake Mobile"}, 98 99 {0x0100, 0x0102, INTEL_MODEL_SNBG, "SandyBridge Desktop GT1"}, 100 {0x0100, 0x0112, INTEL_MODEL_SNBG, "SandyBridge Desktop GT2"}, 101 {0x0100, 0x0122, INTEL_MODEL_SNBG, "SandyBridge Desktop GT2+"}, 102 {0x0104, 0x0106, INTEL_MODEL_SNBGM, "SandyBridge Mobile GT1"}, 103 {0x0104, 0x0116, INTEL_MODEL_SNBGM, "SandyBridge Mobile GT2"}, 104 {0x0104, 0x0126, INTEL_MODEL_SNBGM, "SandyBridge Mobile GT2+"}, 105 {0x0108, 0x010a, INTEL_MODEL_SNBGS, "SandyBridge Server"}, 106 107 {0x0150, 0x0152, INTEL_MODEL_IVBG, "IvyBridge Desktop GT1"}, 108 {0x0150, 0x0162, INTEL_MODEL_IVBG, "IvyBridge Desktop GT2"}, 109 {0x0154, 0x0156, INTEL_MODEL_IVBGM, "IvyBridge Mobile GT1"}, 110 {0x0154, 0x0166, INTEL_MODEL_IVBGM, "IvyBridge Mobile GT2"}, 111 {0x0158, 0x015a, INTEL_MODEL_IVBGS, "IvyBridge Server GT1"}, 112 {0x0158, 0x016a, INTEL_MODEL_IVBGS, "IvyBridge Server GT2"}, 113 114 {0x0c00, 0x0412, INTEL_MODEL_HAS, "Haswell Desktop"}, 115 {0x0c04, 0x0416, INTEL_MODEL_HASM, "Haswell Mobile"}, 116 {0x0d04, 0x0d26, INTEL_MODEL_HASM, "Haswell Mobile"}, 117 {0x0a04, 0x0a16, INTEL_MODEL_HASM, "Haswell Mobile"}, 118 119 // XXX: 0x0f00 only confirmed on 0x0f30, 0x0f31 120 {0x0f00, 0x0155, INTEL_MODEL_VLV, "ValleyView Desktop"}, 121 {0x0f00, 0x0f30, INTEL_MODEL_VLVM, "ValleyView Mobile"}, 122 {0x0f00, 0x0f31, INTEL_MODEL_VLVM, "ValleyView Mobile"}, 123 {0x0f00, 0x0f32, INTEL_MODEL_VLVM, "ValleyView Mobile"}, 124 {0x0f00, 0x0f33, INTEL_MODEL_VLVM, "ValleyView Mobile"}, 125 {0x0f00, 0x0157, INTEL_MODEL_VLVM, "ValleyView Mobile"}, 126 127 {0x1604, 0x1616, INTEL_MODEL_BDWM, "HD Graphics 5500 (Broadwell GT2)"}, 128 129 // XXX: 0x1904 only confirmed on 0x1916 130 {0x1904, 0x1902, INTEL_MODEL_SKY, "Skylake GT1"}, 131 {0x1904, 0x1906, INTEL_MODEL_SKYM, "Skylake GT1"}, 132 {0x1904, 0x190a, INTEL_MODEL_SKYS, "Skylake GT1"}, 133 {0x1904, 0x190b, INTEL_MODEL_SKY, "Skylake GT1"}, 134 {0x1904, 0x190e, INTEL_MODEL_SKYM, "Skylake GT1"}, 135 {0x191f, 0x1912, INTEL_MODEL_SKY, "Skylake GT2"}, // confirmed 136 {0x1904, 0x1916, INTEL_MODEL_SKYM, "Skylake GT2"}, 137 {0x1904, 0x191a, INTEL_MODEL_SKYS, "Skylake GT2"}, 138 {0x1904, 0x191b, INTEL_MODEL_SKY, "Skylake GT2"}, 139 {0x1904, 0x191d, INTEL_MODEL_SKY, "Skylake GT2"}, 140 {0x1904, 0x191e, INTEL_MODEL_SKYM, "Skylake GT2"}, 141 {0x1904, 0x1921, INTEL_MODEL_SKYM, "Skylake GT2F"}, 142 {0x1904, 0x1926, INTEL_MODEL_SKYM, "Skylake GT3"}, 143 {0x1904, 0x192a, INTEL_MODEL_SKYS, "Skylake GT3"}, 144 {0x1904, 0x192b, INTEL_MODEL_SKY, "Skylake GT3"}, 145 }; 146 147 struct intel_info { 148 pci_info bridge; 149 pci_info display; 150 DeviceType* type; 151 152 uint32* gtt_base; 153 phys_addr_t gtt_physical_base; 154 area_id gtt_area; 155 size_t gtt_entries; 156 size_t gtt_stolen_entries; 157 158 vuint32* registers; 159 area_id registers_area; 160 161 addr_t aperture_base; 162 phys_addr_t aperture_physical_base; 163 area_id aperture_area; 164 size_t aperture_size; 165 size_t aperture_stolen_size; 166 167 phys_addr_t scratch_page; 168 area_id scratch_area; 169 }; 170 171 static intel_info sInfo; 172 static pci_module_info* sPCI; 173 174 175 static bool 176 has_display_device(pci_info &info, uint32 deviceID) 177 { 178 for (uint32 index = 0; sPCI->get_nth_pci_info(index, &info) == B_OK; 179 index++) { 180 if (info.vendor_id != VENDOR_ID_INTEL 181 || info.device_id != deviceID 182 || info.class_base != PCI_display) 183 continue; 184 185 return true; 186 } 187 188 return false; 189 } 190 191 192 static uint16 193 gtt_memory_config(intel_info &info) 194 { 195 uint8 controlRegister = INTEL_GRAPHICS_MEMORY_CONTROL; 196 if (info.type->InGroup(INTEL_GROUP_SNB)) 197 controlRegister = SNB_GRAPHICS_MEMORY_CONTROL; 198 199 return get_pci_config(info.bridge, controlRegister, 2); 200 } 201 202 203 static size_t 204 determine_gtt_stolen(intel_info &info) 205 { 206 uint16 memoryConfig = gtt_memory_config(info); 207 size_t memorySize = 1 << 20; // 1 MB 208 209 if (info.type->InGroup(INTEL_GROUP_83x)) { 210 // Older chips 211 switch (memoryConfig & STOLEN_MEMORY_MASK) { 212 case i830_LOCAL_MEMORY_ONLY: 213 // TODO: determine its size! 214 ERROR("getting local memory size not implemented.\n"); 215 break; 216 case i830_STOLEN_512K: 217 memorySize >>= 1; 218 break; 219 case i830_STOLEN_1M: 220 // default case 221 break; 222 case i830_STOLEN_8M: 223 memorySize *= 8; 224 break; 225 } 226 } else if (info.type->InGroup(INTEL_GROUP_SNB)) { 227 switch (memoryConfig & SNB_STOLEN_MEMORY_MASK) { 228 case SNB_STOLEN_MEMORY_32MB: 229 memorySize *= 32; 230 break; 231 case SNB_STOLEN_MEMORY_64MB: 232 memorySize *= 64; 233 break; 234 case SNB_STOLEN_MEMORY_96MB: 235 memorySize *= 96; 236 break; 237 case SNB_STOLEN_MEMORY_128MB: 238 memorySize *= 128; 239 break; 240 case SNB_STOLEN_MEMORY_160MB: 241 memorySize *= 160; 242 break; 243 case SNB_STOLEN_MEMORY_192MB: 244 memorySize *= 192; 245 break; 246 case SNB_STOLEN_MEMORY_224MB: 247 memorySize *= 224; 248 break; 249 case SNB_STOLEN_MEMORY_256MB: 250 memorySize *= 256; 251 break; 252 case SNB_STOLEN_MEMORY_288MB: 253 memorySize *= 288; 254 break; 255 case SNB_STOLEN_MEMORY_320MB: 256 memorySize *= 320; 257 break; 258 case SNB_STOLEN_MEMORY_352MB: 259 memorySize *= 352; 260 break; 261 case SNB_STOLEN_MEMORY_384MB: 262 memorySize *= 384; 263 break; 264 case SNB_STOLEN_MEMORY_416MB: 265 memorySize *= 416; 266 break; 267 case SNB_STOLEN_MEMORY_448MB: 268 memorySize *= 448; 269 break; 270 case SNB_STOLEN_MEMORY_480MB: 271 memorySize *= 480; 272 break; 273 case SNB_STOLEN_MEMORY_512MB: 274 memorySize *= 512; 275 break; 276 } 277 } else if (info.type->InGroup(INTEL_GROUP_85x) 278 || info.type->InFamily(INTEL_FAMILY_9xx) 279 || info.type->InFamily(INTEL_FAMILY_SER5) 280 || info.type->InFamily(INTEL_FAMILY_SOC0)) { 281 switch (memoryConfig & STOLEN_MEMORY_MASK) { 282 case i855_STOLEN_MEMORY_4M: 283 memorySize *= 4; 284 break; 285 case i855_STOLEN_MEMORY_8M: 286 memorySize *= 8; 287 break; 288 case i855_STOLEN_MEMORY_16M: 289 memorySize *= 16; 290 break; 291 case i855_STOLEN_MEMORY_32M: 292 memorySize *= 32; 293 break; 294 case i855_STOLEN_MEMORY_48M: 295 memorySize *= 48; 296 break; 297 case i855_STOLEN_MEMORY_64M: 298 memorySize *= 64; 299 break; 300 case i855_STOLEN_MEMORY_128M: 301 memorySize *= 128; 302 break; 303 case i855_STOLEN_MEMORY_256M: 304 memorySize *= 256; 305 break; 306 case G4X_STOLEN_MEMORY_96MB: 307 memorySize *= 96; 308 break; 309 case G4X_STOLEN_MEMORY_160MB: 310 memorySize *= 160; 311 break; 312 case G4X_STOLEN_MEMORY_224MB: 313 memorySize *= 224; 314 break; 315 case G4X_STOLEN_MEMORY_352MB: 316 memorySize *= 352; 317 break; 318 } 319 } else { 320 // TODO: error out! 321 memorySize = 4096; 322 } 323 return memorySize - 4096; 324 } 325 326 327 static size_t 328 determine_gtt_size(intel_info &info) 329 { 330 uint16 memoryConfig = gtt_memory_config(info); 331 size_t gttSize = 0; 332 333 if (info.type->IsModel(INTEL_MODEL_965)) { 334 switch (memoryConfig & i965_GTT_MASK) { 335 case i965_GTT_128K: 336 gttSize = 128 << 10; 337 break; 338 case i965_GTT_256K: 339 gttSize = 256 << 10; 340 break; 341 case i965_GTT_512K: 342 gttSize = 512 << 10; 343 break; 344 } 345 } else if (info.type->IsModel(INTEL_MODEL_G33) 346 || info.type->InGroup(INTEL_GROUP_PIN)) { 347 switch (memoryConfig & G33_GTT_MASK) { 348 case G33_GTT_1M: 349 gttSize = 1 << 20; 350 break; 351 case G33_GTT_2M: 352 gttSize = 2 << 20; 353 break; 354 } 355 } else if (info.type->InGroup(INTEL_GROUP_G4x) 356 || info.type->InGroup(INTEL_GROUP_ILK)) { 357 switch (memoryConfig & G4X_GTT_MASK) { 358 case G4X_GTT_NONE: 359 gttSize = 0; 360 break; 361 case G4X_GTT_1M_NO_IVT: 362 gttSize = 1 << 20; 363 break; 364 case G4X_GTT_2M_NO_IVT: 365 case G4X_GTT_2M_IVT: 366 gttSize = 2 << 20; 367 break; 368 case G4X_GTT_3M_IVT: 369 gttSize = 3 << 20; 370 break; 371 case G4X_GTT_4M_IVT: 372 gttSize = 4 << 20; 373 break; 374 } 375 } else if (info.type->InGroup(INTEL_GROUP_SNB)) { 376 switch (memoryConfig & SNB_GTT_SIZE_MASK) { 377 case SNB_GTT_SIZE_NONE: 378 gttSize = 0; 379 break; 380 case SNB_GTT_SIZE_1MB: 381 gttSize = 1 << 20; 382 break; 383 case SNB_GTT_SIZE_2MB: 384 gttSize = 2 << 20; 385 break; 386 } 387 } else { 388 // older models have the GTT as large as their frame buffer mapping 389 // TODO: check if the i9xx version works with the i8xx chips as well 390 size_t frameBufferSize = 0; 391 if (info.type->InFamily(INTEL_FAMILY_8xx)) { 392 if (info.type->InGroup(INTEL_GROUP_83x) 393 && (memoryConfig & MEMORY_MASK) == i830_FRAME_BUFFER_64M) 394 frameBufferSize = 64 << 20; 395 else 396 frameBufferSize = 128 << 20; 397 } else if (info.type->Generation() >= 3) { 398 frameBufferSize = info.display.u.h0.base_register_sizes[2]; 399 } 400 401 TRACE("frame buffer size %lu MB\n", frameBufferSize >> 20); 402 gttSize = frameBufferSize / 1024; 403 } 404 return gttSize; 405 } 406 407 408 static void 409 set_gtt_entry(intel_info &info, uint32 offset, phys_addr_t physicalAddress) 410 { 411 if (info.type->Generation() >= 8) { 412 // CHV + BXT 413 physicalAddress |= (physicalAddress >> 28) & 0x07f0; 414 // TODO: cache control? 415 } else if (info.type->Generation() >= 6) { 416 // SandyBridge, IronLake, IvyBridge, Haswell 417 physicalAddress |= (physicalAddress >> 28) & 0x0ff0; 418 physicalAddress |= 0x02; // cache control, l3 cacheable 419 } else if (info.type->Generation() >= 4) { 420 // Intel 9xx minus 91x, 94x, G33 421 // possible high bits are stored in the lower end 422 physicalAddress |= (physicalAddress >> 28) & 0x00f0; 423 // TODO: cache control? 424 } 425 426 // TODO: this is not 64-bit safe! 427 write32(info.gtt_base + (offset >> GTT_PAGE_SHIFT), 428 (uint32)physicalAddress | GTT_ENTRY_VALID); 429 } 430 431 432 static void 433 intel_unmap(intel_info &info) 434 { 435 delete_area(info.registers_area); 436 delete_area(info.gtt_area); 437 delete_area(info.scratch_area); 438 delete_area(info.aperture_area); 439 info.aperture_size = 0; 440 } 441 442 443 static status_t 444 intel_map(intel_info &info) 445 { 446 int fbIndex = 0; 447 int mmioIndex = 1; 448 if (info.type->Generation() >= 3) { 449 // for some reason Intel saw the need to change the order of the 450 // mappings with the introduction of the i9xx family 451 mmioIndex = 0; 452 fbIndex = 2; 453 } 454 455 AreaKeeper mmioMapper; 456 info.registers_area = mmioMapper.Map("intel GMCH mmio", 457 info.display.u.h0.base_registers[mmioIndex], 458 info.display.u.h0.base_register_sizes[mmioIndex], B_ANY_KERNEL_ADDRESS, 459 B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, (void**)&info.registers); 460 461 if (mmioMapper.InitCheck() < B_OK) { 462 ERROR("could not map memory I/O!\n"); 463 return info.registers_area; 464 } 465 466 // make sure bus master, memory-mapped I/O, and frame buffer is enabled 467 set_pci_config(info.display, PCI_command, 2, 468 get_pci_config(info.display, PCI_command, 2) 469 | PCI_command_io | PCI_command_memory | PCI_command_master); 470 471 void* scratchAddress; 472 AreaKeeper scratchCreator; 473 info.scratch_area = scratchCreator.Create("intel GMCH scratch", 474 &scratchAddress, B_ANY_KERNEL_ADDRESS, B_PAGE_SIZE, B_FULL_LOCK, 475 B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA); 476 if (scratchCreator.InitCheck() < B_OK) { 477 ERROR("could not create scratch page!\n"); 478 return info.scratch_area; 479 } 480 481 physical_entry entry; 482 if (get_memory_map(scratchAddress, B_PAGE_SIZE, &entry, 1) != B_OK) 483 return B_ERROR; 484 485 // TODO: Review these 486 if (info.type->InFamily(INTEL_FAMILY_8xx)) { 487 info.gtt_physical_base = read32(info.registers 488 + INTEL_PAGE_TABLE_CONTROL) & ~PAGE_TABLE_ENABLED; 489 if (info.gtt_physical_base == 0) { 490 // TODO: not sure how this is supposed to work under Linux/FreeBSD, 491 // but on my i865, this code is needed for Haiku. 492 ERROR("Use GTT address fallback.\n"); 493 info.gtt_physical_base = info.display.u.h0.base_registers[mmioIndex] 494 + i830_GTT_BASE; 495 } 496 } else if (info.type->InGroup(INTEL_GROUP_91x)) { 497 info.gtt_physical_base = get_pci_config(info.display, i915_GTT_BASE, 4); 498 } else { 499 // 945+? 500 info.gtt_physical_base = info.display.u.h0.base_registers[mmioIndex] 501 + (2UL << 20); 502 } 503 504 size_t gttSize = determine_gtt_size(info); 505 size_t stolenSize = determine_gtt_stolen(info); 506 507 info.gtt_entries = gttSize / 4096; 508 info.gtt_stolen_entries = stolenSize / 4096; 509 510 TRACE("GTT base %" B_PRIxPHYSADDR ", size %lu, entries %lu, stolen %lu\n", 511 info.gtt_physical_base, gttSize, info.gtt_entries, stolenSize); 512 513 AreaKeeper gttMapper; 514 info.gtt_area = gttMapper.Map("intel GMCH gtt", 515 info.gtt_physical_base, gttSize, B_ANY_KERNEL_ADDRESS, 516 B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, (void**)&info.gtt_base); 517 if (gttMapper.InitCheck() < B_OK) { 518 ERROR("could not map GTT!\n"); 519 return info.gtt_area; 520 } 521 522 info.aperture_physical_base = info.display.u.h0.base_registers[fbIndex]; 523 info.aperture_stolen_size = stolenSize; 524 if (info.aperture_size == 0) 525 info.aperture_size = info.display.u.h0.base_register_sizes[fbIndex]; 526 527 ERROR("detected %ld MB of stolen memory, aperture size %ld MB, " 528 "GTT size %ld KB\n", (stolenSize + (1023 << 10)) >> 20, 529 info.aperture_size >> 20, gttSize >> 10); 530 531 ERROR("GTT base = 0x%" B_PRIxPHYSADDR "\n", info.gtt_physical_base); 532 ERROR("MMIO base = 0x%" B_PRIx32 "\n", 533 info.display.u.h0.base_registers[mmioIndex]); 534 ERROR("GMR base = 0x%" B_PRIxPHYSADDR "\n", info.aperture_physical_base); 535 536 AreaKeeper apertureMapper; 537 info.aperture_area = apertureMapper.Map("intel graphics aperture", 538 info.aperture_physical_base, info.aperture_size, 539 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 540 B_READ_AREA | B_WRITE_AREA, (void**)&info.aperture_base); 541 if (apertureMapper.InitCheck() < B_OK) { 542 // try again without write combining 543 ERROR("enabling write combined mode failed.\n"); 544 545 info.aperture_area = apertureMapper.Map("intel graphics aperture", 546 info.aperture_physical_base, info.aperture_size, 547 B_ANY_KERNEL_BLOCK_ADDRESS, B_READ_AREA | B_WRITE_AREA, 548 (void**)&info.aperture_base); 549 } 550 if (apertureMapper.InitCheck() < B_OK) { 551 ERROR("could not map graphics aperture!\n"); 552 return info.aperture_area; 553 } 554 555 info.scratch_page = entry.address; 556 557 gttMapper.Detach(); 558 mmioMapper.Detach(); 559 scratchCreator.Detach(); 560 apertureMapper.Detach(); 561 562 return B_OK; 563 } 564 565 566 // #pragma mark - module interface 567 568 569 status_t 570 intel_create_aperture(uint8 bus, uint8 device, uint8 function, size_t size, 571 void** _aperture) 572 { 573 // TODO: we currently only support a single AGP bridge! 574 if ((bus != sInfo.bridge.bus || device != sInfo.bridge.device 575 || function != sInfo.bridge.function) 576 && (bus != sInfo.display.bus || device != sInfo.display.device 577 || function != sInfo.display.function)) 578 return B_BAD_VALUE; 579 580 sInfo.aperture_size = size; 581 582 if (intel_map(sInfo) < B_OK) 583 return B_ERROR; 584 585 uint16 gmchControl = get_pci_config(sInfo.bridge, 586 INTEL_GRAPHICS_MEMORY_CONTROL, 2) | MEMORY_CONTROL_ENABLED; 587 set_pci_config(sInfo.bridge, INTEL_GRAPHICS_MEMORY_CONTROL, 2, gmchControl); 588 589 write32(sInfo.registers + INTEL_PAGE_TABLE_CONTROL, 590 sInfo.gtt_physical_base | PAGE_TABLE_ENABLED); 591 read32(sInfo.registers + INTEL_PAGE_TABLE_CONTROL); 592 593 if (sInfo.scratch_page != 0) { 594 for (size_t i = sInfo.gtt_stolen_entries; i < sInfo.gtt_entries; i++) { 595 set_gtt_entry(sInfo, i << GTT_PAGE_SHIFT, sInfo.scratch_page); 596 } 597 read32(sInfo.gtt_base + sInfo.gtt_entries - 1); 598 } 599 600 asm("wbinvd;"); 601 602 *_aperture = NULL; 603 return B_OK; 604 } 605 606 607 void 608 intel_delete_aperture(void* aperture) 609 { 610 intel_unmap(sInfo); 611 } 612 613 614 static status_t 615 intel_get_aperture_info(void* aperture, aperture_info* info) 616 { 617 if (info == NULL) 618 return B_BAD_VALUE; 619 620 info->base = sInfo.aperture_base; 621 info->physical_base = sInfo.aperture_physical_base; 622 info->size = sInfo.aperture_size; 623 info->reserved_size = sInfo.aperture_stolen_size; 624 625 return B_OK; 626 } 627 628 629 status_t 630 intel_set_aperture_size(void* aperture, size_t size) 631 { 632 return B_ERROR; 633 } 634 635 636 static status_t 637 intel_bind_page(void* aperture, uint32 offset, phys_addr_t physicalAddress) 638 { 639 //TRACE("bind_page(offset %lx, physical %lx)\n", offset, physicalAddress); 640 641 set_gtt_entry(sInfo, offset, physicalAddress); 642 return B_OK; 643 } 644 645 646 static status_t 647 intel_unbind_page(void* aperture, uint32 offset) 648 { 649 //TRACE("unbind_page(offset %lx)\n", offset); 650 651 if (sInfo.scratch_page != 0) 652 set_gtt_entry(sInfo, offset, sInfo.scratch_page); 653 654 return B_OK; 655 } 656 657 658 void 659 intel_flush_tlbs(void* aperture) 660 { 661 read32(sInfo.gtt_base + sInfo.gtt_entries - 1); 662 asm("wbinvd;"); 663 } 664 665 666 // #pragma mark - 667 668 669 static status_t 670 intel_init() 671 { 672 TRACE("bus manager init\n"); 673 674 if (get_module(B_PCI_MODULE_NAME, (module_info**)&sPCI) != B_OK) 675 return B_ERROR; 676 677 for (uint32 index = 0; sPCI->get_nth_pci_info(index, &sInfo.bridge) == B_OK; 678 index++) { 679 if (sInfo.bridge.vendor_id != VENDOR_ID_INTEL 680 || sInfo.bridge.class_base != PCI_bridge) 681 continue; 682 683 // check device 684 for (uint32 i = 0; i < sizeof(kSupportedDevices) 685 / sizeof(kSupportedDevices[0]); i++) { 686 if (sInfo.bridge.device_id == kSupportedDevices[i].bridge_id) { 687 sInfo.type = new DeviceType(kSupportedDevices[i].type); 688 if (has_display_device(sInfo.display, 689 kSupportedDevices[i].display_id)) { 690 TRACE("found intel bridge\n"); 691 return B_OK; 692 } 693 } 694 } 695 } 696 697 return ENODEV; 698 } 699 700 701 static void 702 intel_uninit() 703 { 704 if (sInfo.type) 705 delete sInfo.type; 706 } 707 708 709 static int32 710 intel_std_ops(int32 op, ...) 711 { 712 switch (op) { 713 case B_MODULE_INIT: 714 return intel_init(); 715 case B_MODULE_UNINIT: 716 intel_uninit(); 717 return B_OK; 718 } 719 720 return B_BAD_VALUE; 721 } 722 723 724 static struct agp_gart_bus_module_info sIntelModuleInfo = { 725 { 726 "busses/agp_gart/intel/v0", 727 0, 728 intel_std_ops 729 }, 730 731 intel_create_aperture, 732 intel_delete_aperture, 733 734 intel_get_aperture_info, 735 intel_set_aperture_size, 736 intel_bind_page, 737 intel_unbind_page, 738 intel_flush_tlbs 739 }; 740 741 module_info* modules[] = { 742 (module_info*)&sIntelModuleInfo, 743 NULL 744 }; 745