1 /* 2 * Copyright 2008-2010, Axel Dörfler, axeld@pinc-software.de. 3 * Copyright 2011-2016, Haiku, Inc. All Rights Reserved. 4 * Distributed under the terms of the MIT License. 5 * 6 * Authors: 7 * Axel Dörfler, axeld@pinc-software.de 8 * Jerome Duval, jerome.duval@gmail.com 9 * Adrien Destugues, pulkomandy@gmail.com 10 * Michael Lotz, mmlr@mlotz.ch 11 * Alexander von Gluck IV, kallisti5@unixzen.com 12 */ 13 14 15 #include <AreaKeeper.h> 16 #include <intel_extreme.h> 17 18 #include <stdlib.h> 19 20 #include <AGP.h> 21 #include <KernelExport.h> 22 #include <PCI.h> 23 24 #include <new> 25 26 27 #define TRACE_INTEL 28 #ifdef TRACE_INTEL 29 # define TRACE(x...) dprintf("intel_gart: " x) 30 #else 31 # define TRACE(x...) ; 32 #endif 33 #define ERROR(x...) dprintf("intel_gart: " x) 34 35 36 /* read and write to PCI config space */ 37 #define get_pci_config(info, offset, size) \ 38 (sPCI->read_pci_config((info).bus, (info).device, (info).function, \ 39 (offset), (size))) 40 #define set_pci_config(info, offset, size, value) \ 41 (sPCI->write_pci_config((info).bus, (info).device, (info).function, \ 42 (offset), (size), (value))) 43 #define write32(address, data) \ 44 (*((volatile uint32*)(address)) = (data)) 45 #define read32(address) \ 46 (*((volatile uint32*)(address))) 47 48 49 // PCI "Host bridge" is most cases :-) 50 const struct supported_device { 51 uint32 bridge_id; 52 uint32 display_id; 53 int32 type; 54 const char *name; 55 } kSupportedDevices[] = { 56 {0x3575, 0x3577, INTEL_GROUP_83x, "i830GM"}, 57 {0x2560, 0x2562, INTEL_GROUP_83x, "i845G"}, 58 {0x3580, 0x3582, INTEL_GROUP_85x, "i855G"}, 59 {0x358c, 0x358e, INTEL_GROUP_85x, "i855G"}, 60 {0x2570, 0x2572, INTEL_GROUP_85x, "i865G"}, 61 62 // {0x2792, INTEL_GROUP_91x, "i910"}, 63 // {0x258a, INTEL_GROUP_91x, "i915"}, 64 {0x2580, 0x2582, INTEL_MODEL_915, "i915G"}, 65 {0x2590, 0x2592, INTEL_MODEL_915M, "i915GM"}, 66 {0x2770, 0x2772, INTEL_MODEL_945, "i945G"}, 67 {0x27a0, 0x27a2, INTEL_MODEL_945M, "i945GM"}, 68 {0x27ac, 0x27ae, INTEL_MODEL_945M, "i945GME"}, 69 70 {0x2970, 0x2972, INTEL_MODEL_965, "i946GZ"}, 71 {0x2980, 0x2982, INTEL_MODEL_965, "G35"}, 72 {0x2990, 0x2992, INTEL_MODEL_965, "i965Q"}, 73 {0x29a0, 0x29a2, INTEL_MODEL_965, "i965G"}, 74 {0x2a00, 0x2a02, INTEL_MODEL_965, "i965GM"}, 75 {0x2a10, 0x2a12, INTEL_MODEL_965, "i965GME"}, 76 77 {0x29b0, 0x29b2, INTEL_MODEL_G33, "G33"}, 78 {0x29c0, 0x29c2, INTEL_MODEL_G33, "Q35"}, 79 {0x29d0, 0x29d2, INTEL_MODEL_G33, "Q33"}, 80 81 {0x2a40, 0x2a42, INTEL_MODEL_GM45, "GM45"}, 82 {0x2e00, 0x2e02, INTEL_MODEL_G45, "IGD"}, 83 {0x2e10, 0x2e12, INTEL_MODEL_G45, "Q45"}, 84 {0x2e20, 0x2e22, INTEL_MODEL_G45, "G45"}, 85 {0x2e30, 0x2e32, INTEL_MODEL_G45, "G41"}, 86 {0x2e40, 0x2e42, INTEL_MODEL_G45, "B43"}, 87 {0x2e90, 0x2e92, INTEL_MODEL_G45, "B43"}, 88 89 {0xa000, 0xa001, INTEL_MODEL_PINE, "Atom D4xx"}, 90 {0xa000, 0xa002, INTEL_MODEL_PINE, "Atom D5xx"}, 91 {0xa010, 0xa011, INTEL_MODEL_PINEM, "Atom N4xx"}, 92 {0xa010, 0xa012, INTEL_MODEL_PINEM, "Atom N5xx"}, 93 94 {0x0040, 0x0042, INTEL_MODEL_ILKG, "IronLake Desktop"}, 95 {0x0044, 0x0046, INTEL_MODEL_ILKGM, "IronLake Mobile"}, 96 {0x0062, 0x0046, INTEL_MODEL_ILKGM, "IronLake Mobile"}, 97 {0x006a, 0x0046, INTEL_MODEL_ILKGM, "IronLake Mobile"}, 98 99 {0x0100, 0x0102, INTEL_MODEL_SNBG, "SandyBridge Desktop GT1"}, 100 {0x0100, 0x0112, INTEL_MODEL_SNBG, "SandyBridge Desktop GT2"}, 101 {0x0100, 0x0122, INTEL_MODEL_SNBG, "SandyBridge Desktop GT2+"}, 102 {0x0104, 0x0106, INTEL_MODEL_SNBGM, "SandyBridge Mobile GT1"}, 103 {0x0104, 0x0116, INTEL_MODEL_SNBGM, "SandyBridge Mobile GT2"}, 104 {0x0104, 0x0126, INTEL_MODEL_SNBGM, "SandyBridge Mobile GT2+"}, 105 {0x0108, 0x010a, INTEL_MODEL_SNBGS, "SandyBridge Server"}, 106 107 {0x0150, 0x0152, INTEL_MODEL_IVBG, "IvyBridge Desktop GT1"}, 108 {0x0150, 0x0162, INTEL_MODEL_IVBG, "IvyBridge Desktop GT2"}, 109 {0x0154, 0x0156, INTEL_MODEL_IVBGM, "IvyBridge Mobile GT1"}, 110 {0x0154, 0x0166, INTEL_MODEL_IVBGM, "IvyBridge Mobile GT2"}, 111 {0x0158, 0x015a, INTEL_MODEL_IVBGS, "IvyBridge Server GT1"}, 112 {0x0158, 0x016a, INTEL_MODEL_IVBGS, "IvyBridge Server GT2"}, 113 114 {0x0c00, 0x0412, INTEL_MODEL_HAS, "Haswell Desktop"}, 115 {0x0c04, 0x0416, INTEL_MODEL_HASM, "Haswell Mobile"}, 116 {0x0d04, 0x0d26, INTEL_MODEL_HASM, "Haswell Mobile"}, 117 {0x0a04, 0x0a16, INTEL_MODEL_HASM, "Haswell Mobile"}, 118 119 // XXX: 0x0f00 only confirmed on 0x0f30, 0x0f31 120 {0x0f00, 0x0155, INTEL_MODEL_VLV, "ValleyView Desktop"}, 121 {0x0f00, 0x0f30, INTEL_MODEL_VLVM, "ValleyView Mobile"}, 122 {0x0f00, 0x0f31, INTEL_MODEL_VLVM, "ValleyView Mobile"}, 123 {0x0f00, 0x0f32, INTEL_MODEL_VLVM, "ValleyView Mobile"}, 124 {0x0f00, 0x0f33, INTEL_MODEL_VLVM, "ValleyView Mobile"}, 125 {0x0f00, 0x0157, INTEL_MODEL_VLVM, "ValleyView Mobile"}, 126 127 {0x1604, 0x1616, INTEL_MODEL_BDWM, "HD Graphics 5500 (Broadwell GT2)"}, 128 129 // XXX: 0x1904 only confirmed on 0x1916 130 {0x1904, 0x1902, INTEL_MODEL_SKY, "Skylake GT1"}, 131 {0x1904, 0x1906, INTEL_MODEL_SKYM, "Skylake GT1"}, 132 {0x1904, 0x190a, INTEL_MODEL_SKYS, "Skylake GT1"}, 133 {0x1904, 0x190b, INTEL_MODEL_SKY, "Skylake GT1"}, 134 {0x1904, 0x190e, INTEL_MODEL_SKYM, "Skylake GT1"}, 135 {0x191f, 0x1912, INTEL_MODEL_SKY, "Skylake GT2"}, // confirmed 136 {0x1904, 0x1916, INTEL_MODEL_SKYM, "Skylake GT2"}, 137 {0x1904, 0x191a, INTEL_MODEL_SKYS, "Skylake GT2"}, 138 {0x1904, 0x191b, INTEL_MODEL_SKY, "Skylake GT2"}, 139 {0x1904, 0x191d, INTEL_MODEL_SKY, "Skylake GT2"}, 140 {0x1904, 0x191e, INTEL_MODEL_SKYM, "Skylake GT2"}, 141 {0x1904, 0x1921, INTEL_MODEL_SKYM, "Skylake GT2F"}, 142 {0x1904, 0x1926, INTEL_MODEL_SKYM, "Skylake GT3"}, 143 {0x1904, 0x192a, INTEL_MODEL_SKYS, "Skylake GT3"}, 144 {0x1904, 0x192b, INTEL_MODEL_SKY, "Skylake GT3"}, 145 146 {0x5904, 0x5906, INTEL_MODEL_KBY, "Kabylake ULT GT1"}, 147 {0x590f, 0x5902, INTEL_MODEL_KBY, "Kabylake DT GT1"}, 148 {0x5904, 0x5916, INTEL_MODEL_KBYM, "Kabylake ULT GT2"}, 149 {0x590c, 0x5916, INTEL_MODEL_KBYM, "Kabylake ULT GT2"}, 150 {0x5904, 0x5921, INTEL_MODEL_KBYM, "Kabylake ULT GT2F"}, 151 {0x590c, 0x591c, INTEL_MODEL_KBY, "Kabylake ULX GT2"}, 152 {0x590c, 0x591e, INTEL_MODEL_KBY, "Kabylake ULX GT2"}, 153 {0x591f, 0x5912, INTEL_MODEL_KBY, "Kabylake DT GT2"}, 154 {0x5914, 0x5917, INTEL_MODEL_KBYM, "Kabylake Mobile GT2"}, 155 {0x5910, 0x591b, INTEL_MODEL_KBYM, "Kabylake Halo GT2"}, 156 {0x5918, 0x591d, INTEL_MODEL_KBY, "Kabylake WKS GT2"}, 157 {0x5904, 0x5926, INTEL_MODEL_KBY, "Kabylake ULT GT3"}, 158 {0x5904, 0x5927, INTEL_MODEL_KBY, "Kabylake ULT GT3"}, 159 160 {0x3e0f, 0x3e90, INTEL_MODEL_CFL, "CoffeeLake GT1"}, 161 {0x3e0f, 0x3e93, INTEL_MODEL_CFL, "CoffeeLake GT1"}, 162 {0x3e1f, 0x3e91, INTEL_MODEL_CFL, "CoffeeLake GT2"}, 163 {0x3ec2, 0x3e92, INTEL_MODEL_CFL, "CoffeeLake GT2"}, 164 {0x3e18, 0x3e96, INTEL_MODEL_CFL, "CoffeeLake GT2"}, 165 {0x3e30, 0x3e98, INTEL_MODEL_CFL, "CoffeeLake GT2"}, 166 {0x3e31, 0x3e9a, INTEL_MODEL_CFL, "CoffeeLake GT2"}, 167 {0x3ec4, 0x3e9b, INTEL_MODEL_CFLM, "CoffeeLake Halo GT2"}, 168 {0x3e10, 0x3eab, INTEL_MODEL_CFLM, "CoffeeLake Halo GT2"}, 169 {0x3ec4, 0x3eab, INTEL_MODEL_CFLM, "CoffeeLake Halo GT2"}, 170 {0x3ed0, 0x3ea5, INTEL_MODEL_CFL, "CoffeeLake GT3"}, 171 {0x3ed0, 0x3ea6, INTEL_MODEL_CFL, "CoffeeLake GT3"}, 172 173 {0x4e22, 0x4e55, INTEL_MODEL_JSL, "JasperLake"}, 174 {0x4e24, 0x4e55, INTEL_MODEL_JSL, "JasperLake"}, 175 {0x4e12, 0x4e61, INTEL_MODEL_JSL, "JasperLake"}, 176 {0x4e26, 0x4e71, INTEL_MODEL_JSLM, "JasperLake"}, 177 {0x4e28, 0x4e71, INTEL_MODEL_JSLM, "JasperLake"}, 178 }; 179 180 struct intel_info { 181 pci_info bridge; 182 pci_info display; 183 DeviceType* type; 184 185 uint32* gtt_base; 186 phys_addr_t gtt_physical_base; 187 area_id gtt_area; 188 size_t gtt_entries; 189 size_t gtt_stolen_entries; 190 191 vuint32* registers; 192 area_id registers_area; 193 194 addr_t aperture_base; 195 phys_addr_t aperture_physical_base; 196 area_id aperture_area; 197 size_t aperture_size; 198 size_t aperture_stolen_size; 199 200 phys_addr_t scratch_page; 201 area_id scratch_area; 202 }; 203 204 static intel_info sInfo; 205 static pci_module_info* sPCI; 206 207 208 static bool 209 has_display_device(pci_info &info, uint32 deviceID) 210 { 211 for (uint32 index = 0; sPCI->get_nth_pci_info(index, &info) == B_OK; 212 index++) { 213 if (info.vendor_id != VENDOR_ID_INTEL 214 || info.device_id != deviceID 215 || info.class_base != PCI_display) 216 continue; 217 218 return true; 219 } 220 221 return false; 222 } 223 224 225 static uint16 226 gtt_memory_config(intel_info &info) 227 { 228 uint8 controlRegister = INTEL_GRAPHICS_MEMORY_CONTROL; 229 if (info.type->Generation() >= 6) 230 controlRegister = SNB_GRAPHICS_MEMORY_CONTROL; 231 232 return get_pci_config(info.bridge, controlRegister, 2); 233 } 234 235 236 static size_t 237 determine_gtt_stolen(intel_info &info) 238 { 239 uint16 memoryConfig = gtt_memory_config(info); 240 size_t memorySize = 1 << 20; // 1 MB 241 242 if (info.type->InGroup(INTEL_GROUP_83x)) { 243 // Older chips 244 switch (memoryConfig & STOLEN_MEMORY_MASK) { 245 case i830_LOCAL_MEMORY_ONLY: 246 // TODO: determine its size! 247 ERROR("getting local memory size not implemented.\n"); 248 break; 249 case i830_STOLEN_512K: 250 memorySize >>= 1; 251 break; 252 case i830_STOLEN_1M: 253 // default case 254 break; 255 case i830_STOLEN_8M: 256 memorySize *= 8; 257 break; 258 } 259 } else if (info.type->InGroup(INTEL_GROUP_SNB) 260 || info.type->InGroup(INTEL_GROUP_IVB) 261 || info.type->InGroup(INTEL_GROUP_HAS)) { 262 switch (memoryConfig & SNB_STOLEN_MEMORY_MASK) { 263 case SNB_STOLEN_MEMORY_32MB: 264 memorySize *= 32; 265 break; 266 case SNB_STOLEN_MEMORY_64MB: 267 memorySize *= 64; 268 break; 269 case SNB_STOLEN_MEMORY_96MB: 270 memorySize *= 96; 271 break; 272 case SNB_STOLEN_MEMORY_128MB: 273 memorySize *= 128; 274 break; 275 case SNB_STOLEN_MEMORY_160MB: 276 memorySize *= 160; 277 break; 278 case SNB_STOLEN_MEMORY_192MB: 279 memorySize *= 192; 280 break; 281 case SNB_STOLEN_MEMORY_224MB: 282 memorySize *= 224; 283 break; 284 case SNB_STOLEN_MEMORY_256MB: 285 memorySize *= 256; 286 break; 287 case SNB_STOLEN_MEMORY_288MB: 288 memorySize *= 288; 289 break; 290 case SNB_STOLEN_MEMORY_320MB: 291 memorySize *= 320; 292 break; 293 case SNB_STOLEN_MEMORY_352MB: 294 memorySize *= 352; 295 break; 296 case SNB_STOLEN_MEMORY_384MB: 297 memorySize *= 384; 298 break; 299 case SNB_STOLEN_MEMORY_416MB: 300 memorySize *= 416; 301 break; 302 case SNB_STOLEN_MEMORY_448MB: 303 memorySize *= 448; 304 break; 305 case SNB_STOLEN_MEMORY_480MB: 306 memorySize *= 480; 307 break; 308 case SNB_STOLEN_MEMORY_512MB: 309 memorySize *= 512; 310 break; 311 } 312 } else if (info.type->InGroup(INTEL_GROUP_BDW) 313 || info.type->InFamily(INTEL_FAMILY_LAKE)) { 314 switch (memoryConfig & BDW_STOLEN_MEMORY_MASK) { 315 case BDW_STOLEN_MEMORY_32MB: 316 memorySize *= 32; 317 break; 318 case BDW_STOLEN_MEMORY_64MB: 319 memorySize *= 64; 320 break; 321 case BDW_STOLEN_MEMORY_96MB: 322 memorySize *= 96; 323 break; 324 case BDW_STOLEN_MEMORY_128MB: 325 memorySize *= 128; 326 break; 327 case BDW_STOLEN_MEMORY_160MB: 328 memorySize *= 160; 329 break; 330 case BDW_STOLEN_MEMORY_192MB: 331 memorySize *= 192; 332 break; 333 case BDW_STOLEN_MEMORY_224MB: 334 memorySize *= 224; 335 break; 336 case BDW_STOLEN_MEMORY_256MB: 337 memorySize *= 256; 338 break; 339 case BDW_STOLEN_MEMORY_288MB: 340 memorySize *= 288; 341 break; 342 case BDW_STOLEN_MEMORY_320MB: 343 memorySize *= 320; 344 break; 345 case BDW_STOLEN_MEMORY_352MB: 346 memorySize *= 352; 347 break; 348 case BDW_STOLEN_MEMORY_384MB: 349 memorySize *= 384; 350 break; 351 case BDW_STOLEN_MEMORY_416MB: 352 memorySize *= 416; 353 break; 354 case BDW_STOLEN_MEMORY_448MB: 355 memorySize *= 448; 356 break; 357 case BDW_STOLEN_MEMORY_480MB: 358 memorySize *= 480; 359 break; 360 case BDW_STOLEN_MEMORY_512MB: 361 memorySize *= 512; 362 break; 363 case BDW_STOLEN_MEMORY_1024MB: 364 memorySize *= 1024; 365 break; 366 case BDW_STOLEN_MEMORY_1536MB: 367 memorySize *= 1536; 368 break; 369 } 370 if(info.type->InGroup(INTEL_GROUP_BDW)) { 371 if((memoryConfig & BDW_STOLEN_MEMORY_MASK) == BDW_STOLEN_MEMORY_2016MB) { 372 memorySize *= 2016; 373 } 374 } else if(info.type->InFamily(INTEL_FAMILY_LAKE)) { 375 switch(memoryConfig & BDW_STOLEN_MEMORY_MASK) { 376 case SKL_STOLEN_MEMORY_4MB: 377 memorySize *= 4; 378 break; 379 case SKL_STOLEN_MEMORY_8MB: 380 memorySize *= 8; 381 break; 382 case SKL_STOLEN_MEMORY_12MB: 383 memorySize *= 12; 384 break; 385 case SKL_STOLEN_MEMORY_16MB: 386 memorySize *= 16; 387 break; 388 case SKL_STOLEN_MEMORY_20MB: 389 memorySize *= 20; 390 break; 391 case SKL_STOLEN_MEMORY_24MB: 392 memorySize *= 24; 393 break; 394 case SKL_STOLEN_MEMORY_28MB: 395 memorySize *= 28; 396 break; 397 case SKL_STOLEN_MEMORY_32MB: 398 memorySize *= 32; 399 break; 400 case SKL_STOLEN_MEMORY_36MB: 401 memorySize *= 36; 402 break; 403 case SKL_STOLEN_MEMORY_40MB: 404 memorySize *= 40; 405 break; 406 case SKL_STOLEN_MEMORY_44MB: 407 memorySize *= 44; 408 break; 409 case SKL_STOLEN_MEMORY_48MB: 410 memorySize *= 48; 411 break; 412 case SKL_STOLEN_MEMORY_52MB: 413 memorySize *= 52; 414 break; 415 case SKL_STOLEN_MEMORY_56MB: 416 memorySize *= 56; 417 break; 418 case SKL_STOLEN_MEMORY_60MB: 419 memorySize *= 60; 420 break; 421 } 422 } 423 } else if (info.type->InGroup(INTEL_GROUP_85x) 424 || info.type->InFamily(INTEL_FAMILY_9xx) 425 || info.type->InGroup(INTEL_GROUP_ILK)) { 426 switch (memoryConfig & STOLEN_MEMORY_MASK) { 427 case i855_STOLEN_MEMORY_4M: 428 memorySize *= 4; 429 break; 430 case i855_STOLEN_MEMORY_8M: 431 memorySize *= 8; 432 break; 433 case i855_STOLEN_MEMORY_16M: 434 memorySize *= 16; 435 break; 436 case i855_STOLEN_MEMORY_32M: 437 memorySize *= 32; 438 break; 439 case i855_STOLEN_MEMORY_48M: 440 memorySize *= 48; 441 break; 442 case i855_STOLEN_MEMORY_64M: 443 memorySize *= 64; 444 break; 445 case i855_STOLEN_MEMORY_128M: 446 memorySize *= 128; 447 break; 448 case i855_STOLEN_MEMORY_256M: 449 memorySize *= 256; 450 break; 451 case G4X_STOLEN_MEMORY_96MB: 452 memorySize *= 96; 453 break; 454 case G4X_STOLEN_MEMORY_160MB: 455 memorySize *= 160; 456 break; 457 case G4X_STOLEN_MEMORY_224MB: 458 memorySize *= 224; 459 break; 460 case G4X_STOLEN_MEMORY_352MB: 461 memorySize *= 352; 462 break; 463 } 464 } else { 465 // TODO: error out! 466 memorySize = 4096; 467 } 468 return memorySize - 4096; 469 } 470 471 472 static size_t 473 determine_gtt_size(intel_info &info) 474 { 475 uint16 memoryConfig = gtt_memory_config(info); 476 size_t gttSize = 0; 477 478 if (info.type->IsModel(INTEL_MODEL_965)) { 479 switch (memoryConfig & i965_GTT_MASK) { 480 case i965_GTT_128K: 481 gttSize = 128 << 10; 482 break; 483 case i965_GTT_256K: 484 gttSize = 256 << 10; 485 break; 486 case i965_GTT_512K: 487 gttSize = 512 << 10; 488 break; 489 } 490 } else if (info.type->IsModel(INTEL_MODEL_G33) 491 || info.type->InGroup(INTEL_GROUP_PIN)) { 492 switch (memoryConfig & G33_GTT_MASK) { 493 case G33_GTT_1M: 494 gttSize = 1 << 20; 495 break; 496 case G33_GTT_2M: 497 gttSize = 2 << 20; 498 break; 499 } 500 } else if (info.type->InGroup(INTEL_GROUP_G4x) 501 || info.type->InGroup(INTEL_GROUP_ILK)) { 502 switch (memoryConfig & G4X_GTT_MASK) { 503 case G4X_GTT_NONE: 504 gttSize = 0; 505 break; 506 case G4X_GTT_1M_NO_IVT: 507 gttSize = 1 << 20; 508 break; 509 case G4X_GTT_2M_NO_IVT: 510 case G4X_GTT_2M_IVT: 511 gttSize = 2 << 20; 512 break; 513 case G4X_GTT_3M_IVT: 514 gttSize = 3 << 20; 515 break; 516 case G4X_GTT_4M_IVT: 517 gttSize = 4 << 20; 518 break; 519 } 520 } else if (info.type->InGroup(INTEL_GROUP_SNB) 521 || info.type->InGroup(INTEL_GROUP_IVB) 522 || info.type->InGroup(INTEL_GROUP_HAS)) { 523 switch (memoryConfig & SNB_GTT_SIZE_MASK) { 524 case SNB_GTT_SIZE_NONE: 525 gttSize = 0; 526 break; 527 case SNB_GTT_SIZE_1MB: 528 gttSize = 1 << 20; 529 break; 530 case SNB_GTT_SIZE_2MB: 531 gttSize = 2 << 20; 532 break; 533 } 534 } else if (info.type->InGroup(INTEL_GROUP_BDW) 535 || info.type->InFamily(INTEL_FAMILY_LAKE)) { 536 switch (memoryConfig & BDW_GTT_SIZE_MASK) { 537 case BDW_GTT_SIZE_NONE: 538 gttSize = 0; 539 break; 540 case BDW_GTT_SIZE_2MB: 541 gttSize = 2 << 20; 542 break; 543 case BDW_GTT_SIZE_4MB: 544 gttSize = 4 << 20; 545 break; 546 case BDW_GTT_SIZE_8MB: 547 gttSize = 8 << 20; 548 break; 549 } 550 } else { 551 // older models have the GTT as large as their frame buffer mapping 552 // TODO: check if the i9xx version works with the i8xx chips as well 553 size_t frameBufferSize = 0; 554 if (info.type->InFamily(INTEL_FAMILY_8xx)) { 555 if (info.type->InGroup(INTEL_GROUP_83x) 556 && (memoryConfig & MEMORY_MASK) == i830_FRAME_BUFFER_64M) 557 frameBufferSize = 64 << 20; 558 else 559 frameBufferSize = 128 << 20; 560 } else if (info.type->Generation() >= 3) { 561 frameBufferSize = info.display.u.h0.base_register_sizes[2]; 562 } 563 564 TRACE("frame buffer size %lu MB\n", frameBufferSize >> 20); 565 gttSize = frameBufferSize / 1024; 566 } 567 return gttSize; 568 } 569 570 571 static void 572 set_gtt_entry(intel_info &info, uint32 offset, phys_addr_t physicalAddress) 573 { 574 if (info.type->Generation() >= 8) { 575 // CHV + BXT 576 physicalAddress |= (physicalAddress >> 28) & 0x07f0; 577 // TODO: cache control? 578 } else if (info.type->Generation() >= 6) { 579 // SandyBridge, IronLake, IvyBridge, Haswell 580 physicalAddress |= (physicalAddress >> 28) & 0x0ff0; 581 physicalAddress |= 0x02; // cache control, l3 cacheable 582 } else if (info.type->Generation() >= 4) { 583 // Intel 9xx minus 91x, 94x, G33 584 // possible high bits are stored in the lower end 585 physicalAddress |= (physicalAddress >> 28) & 0x00f0; 586 // TODO: cache control? 587 } 588 589 // TODO: this is not 64-bit safe! 590 write32(info.gtt_base + (offset >> GTT_PAGE_SHIFT), 591 (uint32)physicalAddress | GTT_ENTRY_VALID); 592 } 593 594 595 static void 596 intel_unmap(intel_info &info) 597 { 598 delete_area(info.registers_area); 599 delete_area(info.gtt_area); 600 delete_area(info.scratch_area); 601 delete_area(info.aperture_area); 602 info.aperture_size = 0; 603 } 604 605 606 static status_t 607 intel_map(intel_info &info) 608 { 609 int fbIndex = 0; 610 int mmioIndex = 1; 611 if (info.type->Generation() >= 3) { 612 // for some reason Intel saw the need to change the order of the 613 // mappings with the introduction of the i9xx family 614 mmioIndex = 0; 615 fbIndex = 2; 616 } 617 618 phys_addr_t addr = info.display.u.h0.base_registers[mmioIndex]; 619 uint64 barSize = info.display.u.h0.base_register_sizes[mmioIndex]; 620 if ((info.display.u.h0.base_register_flags[mmioIndex] & PCI_address_type) == PCI_address_type_64) { 621 addr |= (uint64)info.display.u.h0.base_registers[mmioIndex + 1] << 32; 622 barSize |= (uint64)info.display.u.h0.base_register_sizes[mmioIndex + 1] << 32; 623 } 624 625 AreaKeeper mmioMapper; 626 info.registers_area = mmioMapper.Map("intel GMCH mmio", addr, barSize, 627 B_ANY_KERNEL_ADDRESS, B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, (void**)&info.registers); 628 629 if (mmioMapper.InitCheck() < B_OK) { 630 ERROR("could not map memory I/O!\n"); 631 return info.registers_area; 632 } 633 634 // make sure bus master, memory-mapped I/O, and frame buffer is enabled 635 set_pci_config(info.display, PCI_command, 2, 636 get_pci_config(info.display, PCI_command, 2) 637 | PCI_command_io | PCI_command_memory | PCI_command_master); 638 639 void* scratchAddress; 640 AreaKeeper scratchCreator; 641 info.scratch_area = scratchCreator.Create("intel GMCH scratch", 642 &scratchAddress, B_ANY_KERNEL_ADDRESS, B_PAGE_SIZE, B_FULL_LOCK, 643 B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA); 644 if (scratchCreator.InitCheck() < B_OK) { 645 ERROR("could not create scratch page!\n"); 646 return info.scratch_area; 647 } 648 649 physical_entry entry; 650 if (get_memory_map(scratchAddress, B_PAGE_SIZE, &entry, 1) != B_OK) 651 return B_ERROR; 652 653 // TODO: Review these 654 if (info.type->InFamily(INTEL_FAMILY_8xx)) { 655 info.gtt_physical_base = read32(info.registers 656 + INTEL_PAGE_TABLE_CONTROL) & ~PAGE_TABLE_ENABLED; 657 if (info.gtt_physical_base == 0) { 658 // TODO: not sure how this is supposed to work under Linux/FreeBSD, 659 // but on my i865, this code is needed for Haiku. 660 ERROR("Use GTT address fallback.\n"); 661 info.gtt_physical_base = info.display.u.h0.base_registers[mmioIndex] 662 + i830_GTT_BASE; 663 } 664 } else if (info.type->InGroup(INTEL_GROUP_91x)) { 665 info.gtt_physical_base = get_pci_config(info.display, i915_GTT_BASE, 4); 666 } else { 667 // 945+? 668 info.gtt_physical_base = addr + (2UL << 20); 669 } 670 671 size_t gttSize = determine_gtt_size(info); 672 size_t stolenSize = determine_gtt_stolen(info); 673 674 info.gtt_entries = gttSize / 4096; 675 info.gtt_stolen_entries = stolenSize / 4096; 676 677 TRACE("GTT base %" B_PRIxPHYSADDR ", size %lu, entries %lu, stolen %lu\n", 678 info.gtt_physical_base, gttSize, info.gtt_entries, stolenSize); 679 680 AreaKeeper gttMapper; 681 info.gtt_area = gttMapper.Map("intel GMCH gtt", 682 info.gtt_physical_base, gttSize, B_ANY_KERNEL_ADDRESS, 683 B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, (void**)&info.gtt_base); 684 if (gttMapper.InitCheck() < B_OK) { 685 ERROR("could not map GTT!\n"); 686 return info.gtt_area; 687 } 688 689 info.aperture_physical_base = info.display.u.h0.base_registers[fbIndex]; 690 info.aperture_stolen_size = stolenSize; 691 if ((info.display.u.h0.base_register_flags[fbIndex] & PCI_address_type) == PCI_address_type_64) { 692 info.aperture_physical_base |= (uint64)info.display.u.h0.base_registers[fbIndex + 1] << 32; 693 if (info.aperture_size == 0) { 694 info.aperture_size = info.display.u.h0.base_register_sizes[fbIndex] 695 |= (uint64)info.display.u.h0.base_register_sizes[fbIndex + 1] << 32; 696 } 697 } else if (info.aperture_size == 0) 698 info.aperture_size = info.display.u.h0.base_register_sizes[fbIndex]; 699 700 ERROR("detected %ld MB of stolen memory, aperture size %ld MB, " 701 "GTT size %ld KB\n", (stolenSize + (1023 << 10)) >> 20, 702 info.aperture_size >> 20, gttSize >> 10); 703 704 ERROR("GTT base = 0x%" B_PRIxPHYSADDR "\n", info.gtt_physical_base); 705 ERROR("MMIO base = 0x%" B_PRIx32 "\n", 706 info.display.u.h0.base_registers[mmioIndex]); 707 ERROR("GMR base = 0x%" B_PRIxPHYSADDR "\n", info.aperture_physical_base); 708 709 AreaKeeper apertureMapper; 710 info.aperture_area = apertureMapper.Map("intel graphics aperture", 711 info.aperture_physical_base, info.aperture_size, 712 B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, 713 B_READ_AREA | B_WRITE_AREA, (void**)&info.aperture_base); 714 if (apertureMapper.InitCheck() < B_OK) { 715 // try again without write combining 716 ERROR("enabling write combined mode failed.\n"); 717 718 info.aperture_area = apertureMapper.Map("intel graphics aperture", 719 info.aperture_physical_base, info.aperture_size, 720 B_ANY_KERNEL_BLOCK_ADDRESS, B_READ_AREA | B_WRITE_AREA, 721 (void**)&info.aperture_base); 722 } 723 if (apertureMapper.InitCheck() < B_OK) { 724 ERROR("could not map graphics aperture!\n"); 725 return info.aperture_area; 726 } 727 728 info.scratch_page = entry.address; 729 730 gttMapper.Detach(); 731 mmioMapper.Detach(); 732 scratchCreator.Detach(); 733 apertureMapper.Detach(); 734 735 return B_OK; 736 } 737 738 739 // #pragma mark - module interface 740 741 742 status_t 743 intel_create_aperture(uint8 bus, uint8 device, uint8 function, size_t size, 744 void** _aperture) 745 { 746 // TODO: we currently only support a single AGP bridge! 747 if ((bus != sInfo.bridge.bus || device != sInfo.bridge.device 748 || function != sInfo.bridge.function) 749 && (bus != sInfo.display.bus || device != sInfo.display.device 750 || function != sInfo.display.function)) 751 return B_BAD_VALUE; 752 753 sInfo.aperture_size = size; 754 755 if (intel_map(sInfo) < B_OK) 756 return B_ERROR; 757 758 uint16 gmchControl = get_pci_config(sInfo.bridge, 759 INTEL_GRAPHICS_MEMORY_CONTROL, 2) | MEMORY_CONTROL_ENABLED; 760 set_pci_config(sInfo.bridge, INTEL_GRAPHICS_MEMORY_CONTROL, 2, gmchControl); 761 762 write32(sInfo.registers + INTEL_PAGE_TABLE_CONTROL, 763 sInfo.gtt_physical_base | PAGE_TABLE_ENABLED); 764 read32(sInfo.registers + INTEL_PAGE_TABLE_CONTROL); 765 766 if (sInfo.scratch_page != 0) { 767 for (size_t i = sInfo.gtt_stolen_entries; i < sInfo.gtt_entries; i++) { 768 set_gtt_entry(sInfo, i << GTT_PAGE_SHIFT, sInfo.scratch_page); 769 } 770 read32(sInfo.gtt_base + sInfo.gtt_entries - 1); 771 } 772 773 asm("wbinvd;"); 774 775 *_aperture = NULL; 776 return B_OK; 777 } 778 779 780 void 781 intel_delete_aperture(void* aperture) 782 { 783 intel_unmap(sInfo); 784 } 785 786 787 static status_t 788 intel_get_aperture_info(void* aperture, aperture_info* info) 789 { 790 if (info == NULL) 791 return B_BAD_VALUE; 792 793 info->base = sInfo.aperture_base; 794 info->physical_base = sInfo.aperture_physical_base; 795 info->size = sInfo.aperture_size; 796 info->reserved_size = sInfo.aperture_stolen_size; 797 798 return B_OK; 799 } 800 801 802 status_t 803 intel_set_aperture_size(void* aperture, size_t size) 804 { 805 return B_ERROR; 806 } 807 808 809 static status_t 810 intel_bind_page(void* aperture, uint32 offset, phys_addr_t physicalAddress) 811 { 812 //TRACE("bind_page(offset %lx, physical %lx)\n", offset, physicalAddress); 813 814 set_gtt_entry(sInfo, offset, physicalAddress); 815 return B_OK; 816 } 817 818 819 static status_t 820 intel_unbind_page(void* aperture, uint32 offset) 821 { 822 //TRACE("unbind_page(offset %lx)\n", offset); 823 824 if (sInfo.scratch_page != 0) 825 set_gtt_entry(sInfo, offset, sInfo.scratch_page); 826 827 return B_OK; 828 } 829 830 831 void 832 intel_flush_tlbs(void* aperture) 833 { 834 read32(sInfo.gtt_base + sInfo.gtt_entries - 1); 835 asm("wbinvd;"); 836 } 837 838 839 // #pragma mark - 840 841 842 static status_t 843 intel_init() 844 { 845 TRACE("bus manager init\n"); 846 847 if (get_module(B_PCI_MODULE_NAME, (module_info**)&sPCI) != B_OK) 848 return B_ERROR; 849 850 for (uint32 index = 0; sPCI->get_nth_pci_info(index, &sInfo.bridge) == B_OK; 851 index++) { 852 if (sInfo.bridge.vendor_id != VENDOR_ID_INTEL 853 || sInfo.bridge.class_base != PCI_bridge) 854 continue; 855 856 // check device 857 for (uint32 i = 0; i < sizeof(kSupportedDevices) 858 / sizeof(kSupportedDevices[0]); i++) { 859 if (sInfo.bridge.device_id == kSupportedDevices[i].bridge_id) { 860 sInfo.type = new DeviceType(kSupportedDevices[i].type); 861 if (has_display_device(sInfo.display, 862 kSupportedDevices[i].display_id)) { 863 TRACE("found intel bridge\n"); 864 return B_OK; 865 } 866 } 867 } 868 } 869 870 return ENODEV; 871 } 872 873 874 static void 875 intel_uninit() 876 { 877 if (sInfo.type) 878 delete sInfo.type; 879 } 880 881 882 static int32 883 intel_std_ops(int32 op, ...) 884 { 885 switch (op) { 886 case B_MODULE_INIT: 887 return intel_init(); 888 case B_MODULE_UNINIT: 889 intel_uninit(); 890 return B_OK; 891 } 892 893 return B_BAD_VALUE; 894 } 895 896 897 static struct agp_gart_bus_module_info sIntelModuleInfo = { 898 { 899 "busses/agp_gart/intel/v0", 900 0, 901 intel_std_ops 902 }, 903 904 intel_create_aperture, 905 intel_delete_aperture, 906 907 intel_get_aperture_info, 908 intel_set_aperture_size, 909 intel_bind_page, 910 intel_unbind_page, 911 intel_flush_tlbs 912 }; 913 914 module_info* modules[] = { 915 (module_info*)&sIntelModuleInfo, 916 NULL 917 }; 918