1 /******************************************************************************* 2 * 3 * Module Name: hwregs - Read/write access functions for the various ACPI 4 * control and status registers. 5 * 6 ******************************************************************************/ 7 8 /****************************************************************************** 9 * 10 * 1. Copyright Notice 11 * 12 * Some or all of this work - Copyright (c) 1999 - 2016, Intel Corp. 13 * All rights reserved. 14 * 15 * 2. License 16 * 17 * 2.1. This is your license from Intel Corp. under its intellectual property 18 * rights. You may have additional license terms from the party that provided 19 * you this software, covering your right to use that party's intellectual 20 * property rights. 21 * 22 * 2.2. Intel grants, free of charge, to any person ("Licensee") obtaining a 23 * copy of the source code appearing in this file ("Covered Code") an 24 * irrevocable, perpetual, worldwide license under Intel's copyrights in the 25 * base code distributed originally by Intel ("Original Intel Code") to copy, 26 * make derivatives, distribute, use and display any portion of the Covered 27 * Code in any form, with the right to sublicense such rights; and 28 * 29 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent 30 * license (with the right to sublicense), under only those claims of Intel 31 * patents that are infringed by the Original Intel Code, to make, use, sell, 32 * offer to sell, and import the Covered Code and derivative works thereof 33 * solely to the minimum extent necessary to exercise the above copyright 34 * license, and in no event shall the patent license extend to any additions 35 * to or modifications of the Original Intel Code. No other license or right 36 * is granted directly or by implication, estoppel or otherwise; 37 * 38 * The above copyright and patent license is granted only if the following 39 * conditions are met: 40 * 41 * 3. Conditions 42 * 43 * 3.1. Redistribution of Source with Rights to Further Distribute Source. 44 * Redistribution of source code of any substantial portion of the Covered 45 * Code or modification with rights to further distribute source must include 46 * the above Copyright Notice, the above License, this list of Conditions, 47 * and the following Disclaimer and Export Compliance provision. In addition, 48 * Licensee must cause all Covered Code to which Licensee contributes to 49 * contain a file documenting the changes Licensee made to create that Covered 50 * Code and the date of any change. Licensee must include in that file the 51 * documentation of any changes made by any predecessor Licensee. Licensee 52 * must include a prominent statement that the modification is derived, 53 * directly or indirectly, from Original Intel Code. 54 * 55 * 3.2. Redistribution of Source with no Rights to Further Distribute Source. 56 * Redistribution of source code of any substantial portion of the Covered 57 * Code or modification without rights to further distribute source must 58 * include the following Disclaimer and Export Compliance provision in the 59 * documentation and/or other materials provided with distribution. In 60 * addition, Licensee may not authorize further sublicense of source of any 61 * portion of the Covered Code, and must include terms to the effect that the 62 * license from Licensee to its licensee is limited to the intellectual 63 * property embodied in the software Licensee provides to its licensee, and 64 * not to intellectual property embodied in modifications its licensee may 65 * make. 66 * 67 * 3.3. Redistribution of Executable. Redistribution in executable form of any 68 * substantial portion of the Covered Code or modification must reproduce the 69 * above Copyright Notice, and the following Disclaimer and Export Compliance 70 * provision in the documentation and/or other materials provided with the 71 * distribution. 72 * 73 * 3.4. Intel retains all right, title, and interest in and to the Original 74 * Intel Code. 75 * 76 * 3.5. Neither the name Intel nor any other trademark owned or controlled by 77 * Intel shall be used in advertising or otherwise to promote the sale, use or 78 * other dealings in products derived from or relating to the Covered Code 79 * without prior written authorization from Intel. 80 * 81 * 4. Disclaimer and Export Compliance 82 * 83 * 4.1. INTEL MAKES NO WARRANTY OF ANY KIND REGARDING ANY SOFTWARE PROVIDED 84 * HERE. ANY SOFTWARE ORIGINATING FROM INTEL OR DERIVED FROM INTEL SOFTWARE 85 * IS PROVIDED "AS IS," AND INTEL WILL NOT PROVIDE ANY SUPPORT, ASSISTANCE, 86 * INSTALLATION, TRAINING OR OTHER SERVICES. INTEL WILL NOT PROVIDE ANY 87 * UPDATES, ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY DISCLAIMS ANY 88 * IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A 89 * PARTICULAR PURPOSE. 90 * 91 * 4.2. IN NO EVENT SHALL INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES 92 * OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS, LOST DATA, LOSS OF USE OR 93 * COSTS OF PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, OR FOR ANY INDIRECT, 94 * SPECIAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THIS AGREEMENT, UNDER ANY 95 * CAUSE OF ACTION OR THEORY OF LIABILITY, AND IRRESPECTIVE OF WHETHER INTEL 96 * HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. THESE LIMITATIONS 97 * SHALL APPLY NOTWITHSTANDING THE FAILURE OF THE ESSENTIAL PURPOSE OF ANY 98 * LIMITED REMEDY. 99 * 100 * 4.3. Licensee shall not export, either directly or indirectly, any of this 101 * software or system incorporating such software without first obtaining any 102 * required license or other approval from the U. S. Department of Commerce or 103 * any other agency or department of the United States Government. In the 104 * event Licensee exports any such software from the United States or 105 * re-exports any such software from a foreign destination, Licensee shall 106 * ensure that the distribution and export/re-export of the software is in 107 * compliance with all laws, regulations, orders, or other restrictions of the 108 * U.S. Export Administration Regulations. Licensee agrees that neither it nor 109 * any of its subsidiaries will export/re-export any technical data, process, 110 * software, or service, directly or indirectly, to any country for which the 111 * United States government or any agency thereof requires an export license, 112 * other governmental approval, or letter of assurance, without first obtaining 113 * such license, approval or letter. 114 * 115 *****************************************************************************/ 116 117 #include "acpi.h" 118 #include "accommon.h" 119 #include "acevents.h" 120 121 #define _COMPONENT ACPI_HARDWARE 122 ACPI_MODULE_NAME ("hwregs") 123 124 125 #if (!ACPI_REDUCED_HARDWARE) 126 127 /* Local Prototypes */ 128 129 static ACPI_STATUS 130 AcpiHwReadMultiple ( 131 UINT32 *Value, 132 ACPI_GENERIC_ADDRESS *RegisterA, 133 ACPI_GENERIC_ADDRESS *RegisterB); 134 135 static ACPI_STATUS 136 AcpiHwWriteMultiple ( 137 UINT32 Value, 138 ACPI_GENERIC_ADDRESS *RegisterA, 139 ACPI_GENERIC_ADDRESS *RegisterB); 140 141 #endif /* !ACPI_REDUCED_HARDWARE */ 142 143 144 /****************************************************************************** 145 * 146 * FUNCTION: AcpiHwValidateRegister 147 * 148 * PARAMETERS: Reg - GAS register structure 149 * MaxBitWidth - Max BitWidth supported (32 or 64) 150 * Address - Pointer to where the gas->address 151 * is returned 152 * 153 * RETURN: Status 154 * 155 * DESCRIPTION: Validate the contents of a GAS register. Checks the GAS 156 * pointer, Address, SpaceId, BitWidth, and BitOffset. 157 * 158 ******************************************************************************/ 159 160 ACPI_STATUS 161 AcpiHwValidateRegister ( 162 ACPI_GENERIC_ADDRESS *Reg, 163 UINT8 MaxBitWidth, 164 UINT64 *Address) 165 { 166 167 /* Must have a valid pointer to a GAS structure */ 168 169 if (!Reg) 170 { 171 return (AE_BAD_PARAMETER); 172 } 173 174 /* 175 * Copy the target address. This handles possible alignment issues. 176 * Address must not be null. A null address also indicates an optional 177 * ACPI register that is not supported, so no error message. 178 */ 179 ACPI_MOVE_64_TO_64 (Address, &Reg->Address); 180 if (!(*Address)) 181 { 182 return (AE_BAD_ADDRESS); 183 } 184 185 /* Validate the SpaceID */ 186 187 if ((Reg->SpaceId != ACPI_ADR_SPACE_SYSTEM_MEMORY) && 188 (Reg->SpaceId != ACPI_ADR_SPACE_SYSTEM_IO)) 189 { 190 ACPI_ERROR ((AE_INFO, 191 "Unsupported address space: 0x%X", Reg->SpaceId)); 192 return (AE_SUPPORT); 193 } 194 195 /* Validate the BitWidth */ 196 197 if ((Reg->BitWidth != 8) && 198 (Reg->BitWidth != 16) && 199 (Reg->BitWidth != 32) && 200 (Reg->BitWidth != MaxBitWidth)) 201 { 202 ACPI_ERROR ((AE_INFO, 203 "Unsupported register bit width: 0x%X", Reg->BitWidth)); 204 return (AE_SUPPORT); 205 } 206 207 /* Validate the BitOffset. Just a warning for now. */ 208 209 if (Reg->BitOffset != 0) 210 { 211 ACPI_WARNING ((AE_INFO, 212 "Unsupported register bit offset: 0x%X", Reg->BitOffset)); 213 } 214 215 return (AE_OK); 216 } 217 218 219 /****************************************************************************** 220 * 221 * FUNCTION: AcpiHwRead 222 * 223 * PARAMETERS: Value - Where the value is returned 224 * Reg - GAS register structure 225 * 226 * RETURN: Status 227 * 228 * DESCRIPTION: Read from either memory or IO space. This is a 32-bit max 229 * version of AcpiRead, used internally since the overhead of 230 * 64-bit values is not needed. 231 * 232 * LIMITATIONS: <These limitations also apply to AcpiHwWrite> 233 * BitWidth must be exactly 8, 16, or 32. 234 * SpaceID must be SystemMemory or SystemIO. 235 * BitOffset and AccessWidth are currently ignored, as there has 236 * not been a need to implement these. 237 * 238 ******************************************************************************/ 239 240 ACPI_STATUS 241 AcpiHwRead ( 242 UINT32 *Value, 243 ACPI_GENERIC_ADDRESS *Reg) 244 { 245 UINT64 Address; 246 UINT64 Value64; 247 ACPI_STATUS Status; 248 249 250 ACPI_FUNCTION_NAME (HwRead); 251 252 253 /* Validate contents of the GAS register */ 254 255 Status = AcpiHwValidateRegister (Reg, 32, &Address); 256 if (ACPI_FAILURE (Status)) 257 { 258 return (Status); 259 } 260 261 /* Initialize entire 32-bit return value to zero */ 262 263 *Value = 0; 264 265 /* 266 * Two address spaces supported: Memory or IO. PCI_Config is 267 * not supported here because the GAS structure is insufficient 268 */ 269 if (Reg->SpaceId == ACPI_ADR_SPACE_SYSTEM_MEMORY) 270 { 271 Status = AcpiOsReadMemory ((ACPI_PHYSICAL_ADDRESS) 272 Address, &Value64, Reg->BitWidth); 273 274 *Value = (UINT32) Value64; 275 } 276 else /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */ 277 { 278 Status = AcpiHwReadPort ((ACPI_IO_ADDRESS) 279 Address, Value, Reg->BitWidth); 280 } 281 282 ACPI_DEBUG_PRINT ((ACPI_DB_IO, 283 "Read: %8.8X width %2d from %8.8X%8.8X (%s)\n", 284 *Value, Reg->BitWidth, ACPI_FORMAT_UINT64 (Address), 285 AcpiUtGetRegionName (Reg->SpaceId))); 286 287 return (Status); 288 } 289 290 291 /****************************************************************************** 292 * 293 * FUNCTION: AcpiHwWrite 294 * 295 * PARAMETERS: Value - Value to be written 296 * Reg - GAS register structure 297 * 298 * RETURN: Status 299 * 300 * DESCRIPTION: Write to either memory or IO space. This is a 32-bit max 301 * version of AcpiWrite, used internally since the overhead of 302 * 64-bit values is not needed. 303 * 304 ******************************************************************************/ 305 306 ACPI_STATUS 307 AcpiHwWrite ( 308 UINT32 Value, 309 ACPI_GENERIC_ADDRESS *Reg) 310 { 311 UINT64 Address; 312 ACPI_STATUS Status; 313 314 315 ACPI_FUNCTION_NAME (HwWrite); 316 317 318 /* Validate contents of the GAS register */ 319 320 Status = AcpiHwValidateRegister (Reg, 32, &Address); 321 if (ACPI_FAILURE (Status)) 322 { 323 return (Status); 324 } 325 326 /* 327 * Two address spaces supported: Memory or IO. PCI_Config is 328 * not supported here because the GAS structure is insufficient 329 */ 330 if (Reg->SpaceId == ACPI_ADR_SPACE_SYSTEM_MEMORY) 331 { 332 Status = AcpiOsWriteMemory ((ACPI_PHYSICAL_ADDRESS) 333 Address, (UINT64) Value, Reg->BitWidth); 334 } 335 else /* ACPI_ADR_SPACE_SYSTEM_IO, validated earlier */ 336 { 337 Status = AcpiHwWritePort ((ACPI_IO_ADDRESS) 338 Address, Value, Reg->BitWidth); 339 } 340 341 ACPI_DEBUG_PRINT ((ACPI_DB_IO, 342 "Wrote: %8.8X width %2d to %8.8X%8.8X (%s)\n", 343 Value, Reg->BitWidth, ACPI_FORMAT_UINT64 (Address), 344 AcpiUtGetRegionName (Reg->SpaceId))); 345 346 return (Status); 347 } 348 349 350 #if (!ACPI_REDUCED_HARDWARE) 351 /******************************************************************************* 352 * 353 * FUNCTION: AcpiHwClearAcpiStatus 354 * 355 * PARAMETERS: None 356 * 357 * RETURN: Status 358 * 359 * DESCRIPTION: Clears all fixed and general purpose status bits 360 * 361 ******************************************************************************/ 362 363 ACPI_STATUS 364 AcpiHwClearAcpiStatus ( 365 void) 366 { 367 ACPI_STATUS Status; 368 ACPI_CPU_FLAGS LockFlags = 0; 369 370 371 ACPI_FUNCTION_TRACE (HwClearAcpiStatus); 372 373 374 ACPI_DEBUG_PRINT ((ACPI_DB_IO, "About to write %04X to %8.8X%8.8X\n", 375 ACPI_BITMASK_ALL_FIXED_STATUS, 376 ACPI_FORMAT_UINT64 (AcpiGbl_XPm1aStatus.Address))); 377 378 LockFlags = AcpiOsAcquireLock (AcpiGbl_HardwareLock); 379 380 /* Clear the fixed events in PM1 A/B */ 381 382 Status = AcpiHwRegisterWrite (ACPI_REGISTER_PM1_STATUS, 383 ACPI_BITMASK_ALL_FIXED_STATUS); 384 385 AcpiOsReleaseLock (AcpiGbl_HardwareLock, LockFlags); 386 387 if (ACPI_FAILURE (Status)) 388 { 389 goto Exit; 390 } 391 392 /* Clear the GPE Bits in all GPE registers in all GPE blocks */ 393 394 Status = AcpiEvWalkGpeList (AcpiHwClearGpeBlock, NULL); 395 396 Exit: 397 return_ACPI_STATUS (Status); 398 } 399 400 401 /******************************************************************************* 402 * 403 * FUNCTION: AcpiHwGetBitRegisterInfo 404 * 405 * PARAMETERS: RegisterId - Index of ACPI Register to access 406 * 407 * RETURN: The bitmask to be used when accessing the register 408 * 409 * DESCRIPTION: Map RegisterId into a register bitmask. 410 * 411 ******************************************************************************/ 412 413 ACPI_BIT_REGISTER_INFO * 414 AcpiHwGetBitRegisterInfo ( 415 UINT32 RegisterId) 416 { 417 ACPI_FUNCTION_ENTRY (); 418 419 420 if (RegisterId > ACPI_BITREG_MAX) 421 { 422 ACPI_ERROR ((AE_INFO, "Invalid BitRegister ID: 0x%X", RegisterId)); 423 return (NULL); 424 } 425 426 return (&AcpiGbl_BitRegisterInfo[RegisterId]); 427 } 428 429 430 /****************************************************************************** 431 * 432 * FUNCTION: AcpiHwWritePm1Control 433 * 434 * PARAMETERS: Pm1aControl - Value to be written to PM1A control 435 * Pm1bControl - Value to be written to PM1B control 436 * 437 * RETURN: Status 438 * 439 * DESCRIPTION: Write the PM1 A/B control registers. These registers are 440 * different than than the PM1 A/B status and enable registers 441 * in that different values can be written to the A/B registers. 442 * Most notably, the SLP_TYP bits can be different, as per the 443 * values returned from the _Sx predefined methods. 444 * 445 ******************************************************************************/ 446 447 ACPI_STATUS 448 AcpiHwWritePm1Control ( 449 UINT32 Pm1aControl, 450 UINT32 Pm1bControl) 451 { 452 ACPI_STATUS Status; 453 454 455 ACPI_FUNCTION_TRACE (HwWritePm1Control); 456 457 458 Status = AcpiHwWrite (Pm1aControl, &AcpiGbl_FADT.XPm1aControlBlock); 459 if (ACPI_FAILURE (Status)) 460 { 461 return_ACPI_STATUS (Status); 462 } 463 464 if (AcpiGbl_FADT.XPm1bControlBlock.Address) 465 { 466 Status = AcpiHwWrite (Pm1bControl, &AcpiGbl_FADT.XPm1bControlBlock); 467 } 468 return_ACPI_STATUS (Status); 469 } 470 471 472 /****************************************************************************** 473 * 474 * FUNCTION: AcpiHwRegisterRead 475 * 476 * PARAMETERS: RegisterId - ACPI Register ID 477 * ReturnValue - Where the register value is returned 478 * 479 * RETURN: Status and the value read. 480 * 481 * DESCRIPTION: Read from the specified ACPI register 482 * 483 ******************************************************************************/ 484 485 ACPI_STATUS 486 AcpiHwRegisterRead ( 487 UINT32 RegisterId, 488 UINT32 *ReturnValue) 489 { 490 UINT32 Value = 0; 491 ACPI_STATUS Status; 492 493 494 ACPI_FUNCTION_TRACE (HwRegisterRead); 495 496 497 switch (RegisterId) 498 { 499 case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */ 500 501 Status = AcpiHwReadMultiple (&Value, 502 &AcpiGbl_XPm1aStatus, 503 &AcpiGbl_XPm1bStatus); 504 break; 505 506 case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access each */ 507 508 Status = AcpiHwReadMultiple (&Value, 509 &AcpiGbl_XPm1aEnable, 510 &AcpiGbl_XPm1bEnable); 511 break; 512 513 case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */ 514 515 Status = AcpiHwReadMultiple (&Value, 516 &AcpiGbl_FADT.XPm1aControlBlock, 517 &AcpiGbl_FADT.XPm1bControlBlock); 518 519 /* 520 * Zero the write-only bits. From the ACPI specification, "Hardware 521 * Write-Only Bits": "Upon reads to registers with write-only bits, 522 * software masks out all write-only bits." 523 */ 524 Value &= ~ACPI_PM1_CONTROL_WRITEONLY_BITS; 525 break; 526 527 case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */ 528 529 Status = AcpiHwRead (&Value, &AcpiGbl_FADT.XPm2ControlBlock); 530 break; 531 532 case ACPI_REGISTER_PM_TIMER: /* 32-bit access */ 533 534 Status = AcpiHwRead (&Value, &AcpiGbl_FADT.XPmTimerBlock); 535 break; 536 537 case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */ 538 539 Status = AcpiHwReadPort (AcpiGbl_FADT.SmiCommand, &Value, 8); 540 break; 541 542 default: 543 544 ACPI_ERROR ((AE_INFO, "Unknown Register ID: 0x%X", 545 RegisterId)); 546 Status = AE_BAD_PARAMETER; 547 break; 548 } 549 550 if (ACPI_SUCCESS (Status)) 551 { 552 *ReturnValue = Value; 553 } 554 555 return_ACPI_STATUS (Status); 556 } 557 558 559 /****************************************************************************** 560 * 561 * FUNCTION: AcpiHwRegisterWrite 562 * 563 * PARAMETERS: RegisterId - ACPI Register ID 564 * Value - The value to write 565 * 566 * RETURN: Status 567 * 568 * DESCRIPTION: Write to the specified ACPI register 569 * 570 * NOTE: In accordance with the ACPI specification, this function automatically 571 * preserves the value of the following bits, meaning that these bits cannot be 572 * changed via this interface: 573 * 574 * PM1_CONTROL[0] = SCI_EN 575 * PM1_CONTROL[9] 576 * PM1_STATUS[11] 577 * 578 * ACPI References: 579 * 1) Hardware Ignored Bits: When software writes to a register with ignored 580 * bit fields, it preserves the ignored bit fields 581 * 2) SCI_EN: OSPM always preserves this bit position 582 * 583 ******************************************************************************/ 584 585 ACPI_STATUS 586 AcpiHwRegisterWrite ( 587 UINT32 RegisterId, 588 UINT32 Value) 589 { 590 ACPI_STATUS Status; 591 UINT32 ReadValue; 592 593 594 ACPI_FUNCTION_TRACE (HwRegisterWrite); 595 596 597 switch (RegisterId) 598 { 599 case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */ 600 /* 601 * Handle the "ignored" bit in PM1 Status. According to the ACPI 602 * specification, ignored bits are to be preserved when writing. 603 * Normally, this would mean a read/modify/write sequence. However, 604 * preserving a bit in the status register is different. Writing a 605 * one clears the status, and writing a zero preserves the status. 606 * Therefore, we must always write zero to the ignored bit. 607 * 608 * This behavior is clarified in the ACPI 4.0 specification. 609 */ 610 Value &= ~ACPI_PM1_STATUS_PRESERVED_BITS; 611 612 Status = AcpiHwWriteMultiple (Value, 613 &AcpiGbl_XPm1aStatus, 614 &AcpiGbl_XPm1bStatus); 615 break; 616 617 case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access each */ 618 619 Status = AcpiHwWriteMultiple (Value, 620 &AcpiGbl_XPm1aEnable, 621 &AcpiGbl_XPm1bEnable); 622 break; 623 624 case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */ 625 /* 626 * Perform a read first to preserve certain bits (per ACPI spec) 627 * Note: This includes SCI_EN, we never want to change this bit 628 */ 629 Status = AcpiHwReadMultiple (&ReadValue, 630 &AcpiGbl_FADT.XPm1aControlBlock, 631 &AcpiGbl_FADT.XPm1bControlBlock); 632 if (ACPI_FAILURE (Status)) 633 { 634 goto Exit; 635 } 636 637 /* Insert the bits to be preserved */ 638 639 ACPI_INSERT_BITS (Value, ACPI_PM1_CONTROL_PRESERVED_BITS, ReadValue); 640 641 /* Now we can write the data */ 642 643 Status = AcpiHwWriteMultiple (Value, 644 &AcpiGbl_FADT.XPm1aControlBlock, 645 &AcpiGbl_FADT.XPm1bControlBlock); 646 break; 647 648 case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */ 649 /* 650 * For control registers, all reserved bits must be preserved, 651 * as per the ACPI spec. 652 */ 653 Status = AcpiHwRead (&ReadValue, &AcpiGbl_FADT.XPm2ControlBlock); 654 if (ACPI_FAILURE (Status)) 655 { 656 goto Exit; 657 } 658 659 /* Insert the bits to be preserved */ 660 661 ACPI_INSERT_BITS (Value, ACPI_PM2_CONTROL_PRESERVED_BITS, ReadValue); 662 663 Status = AcpiHwWrite (Value, &AcpiGbl_FADT.XPm2ControlBlock); 664 break; 665 666 case ACPI_REGISTER_PM_TIMER: /* 32-bit access */ 667 668 Status = AcpiHwWrite (Value, &AcpiGbl_FADT.XPmTimerBlock); 669 break; 670 671 case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */ 672 673 /* SMI_CMD is currently always in IO space */ 674 675 Status = AcpiHwWritePort (AcpiGbl_FADT.SmiCommand, Value, 8); 676 break; 677 678 default: 679 680 ACPI_ERROR ((AE_INFO, "Unknown Register ID: 0x%X", 681 RegisterId)); 682 Status = AE_BAD_PARAMETER; 683 break; 684 } 685 686 Exit: 687 return_ACPI_STATUS (Status); 688 } 689 690 691 /****************************************************************************** 692 * 693 * FUNCTION: AcpiHwReadMultiple 694 * 695 * PARAMETERS: Value - Where the register value is returned 696 * RegisterA - First ACPI register (required) 697 * RegisterB - Second ACPI register (optional) 698 * 699 * RETURN: Status 700 * 701 * DESCRIPTION: Read from the specified two-part ACPI register (such as PM1 A/B) 702 * 703 ******************************************************************************/ 704 705 static ACPI_STATUS 706 AcpiHwReadMultiple ( 707 UINT32 *Value, 708 ACPI_GENERIC_ADDRESS *RegisterA, 709 ACPI_GENERIC_ADDRESS *RegisterB) 710 { 711 UINT32 ValueA = 0; 712 UINT32 ValueB = 0; 713 ACPI_STATUS Status; 714 715 716 /* The first register is always required */ 717 718 Status = AcpiHwRead (&ValueA, RegisterA); 719 if (ACPI_FAILURE (Status)) 720 { 721 return (Status); 722 } 723 724 /* Second register is optional */ 725 726 if (RegisterB->Address) 727 { 728 Status = AcpiHwRead (&ValueB, RegisterB); 729 if (ACPI_FAILURE (Status)) 730 { 731 return (Status); 732 } 733 } 734 735 /* 736 * OR the two return values together. No shifting or masking is necessary, 737 * because of how the PM1 registers are defined in the ACPI specification: 738 * 739 * "Although the bits can be split between the two register blocks (each 740 * register block has a unique pointer within the FADT), the bit positions 741 * are maintained. The register block with unimplemented bits (that is, 742 * those implemented in the other register block) always returns zeros, 743 * and writes have no side effects" 744 */ 745 *Value = (ValueA | ValueB); 746 return (AE_OK); 747 } 748 749 750 /****************************************************************************** 751 * 752 * FUNCTION: AcpiHwWriteMultiple 753 * 754 * PARAMETERS: Value - The value to write 755 * RegisterA - First ACPI register (required) 756 * RegisterB - Second ACPI register (optional) 757 * 758 * RETURN: Status 759 * 760 * DESCRIPTION: Write to the specified two-part ACPI register (such as PM1 A/B) 761 * 762 ******************************************************************************/ 763 764 static ACPI_STATUS 765 AcpiHwWriteMultiple ( 766 UINT32 Value, 767 ACPI_GENERIC_ADDRESS *RegisterA, 768 ACPI_GENERIC_ADDRESS *RegisterB) 769 { 770 ACPI_STATUS Status; 771 772 773 /* The first register is always required */ 774 775 Status = AcpiHwWrite (Value, RegisterA); 776 if (ACPI_FAILURE (Status)) 777 { 778 return (Status); 779 } 780 781 /* 782 * Second register is optional 783 * 784 * No bit shifting or clearing is necessary, because of how the PM1 785 * registers are defined in the ACPI specification: 786 * 787 * "Although the bits can be split between the two register blocks (each 788 * register block has a unique pointer within the FADT), the bit positions 789 * are maintained. The register block with unimplemented bits (that is, 790 * those implemented in the other register block) always returns zeros, 791 * and writes have no side effects" 792 */ 793 if (RegisterB->Address) 794 { 795 Status = AcpiHwWrite (Value, RegisterB); 796 } 797 798 return (Status); 799 } 800 801 #endif /* !ACPI_REDUCED_HARDWARE */ 802