1 /* 2 Haiku S3 Savage driver adapted from the X.org Savage driver. 3 4 Copyright (C) 1994-2000 The XFree86 Project, Inc. All Rights Reserved. 5 Copyright (c) 2003-2006, X.Org Foundation 6 7 Copyright 2007-2008 Haiku, Inc. All rights reserved. 8 Distributed under the terms of the MIT license. 9 10 Authors: 11 Gerald Zajac 2006-2008 12 */ 13 14 #ifndef __SAVAGE_H__ 15 #define __SAVAGE_H__ 16 17 18 19 #define CURSOR_BYTES 1024 // bytes used for cursor image in video memory 20 21 #define ADVANCED_FUNC_CTRL 0x850C 22 #define SYSTEM_CONTROL_REG 0x83DA 23 24 25 // Stream Processor 1. 26 27 // Primary Stream 1 Frame Buffer Address 0. 28 #define PRI_STREAM_FBUF_ADDR0 0x81c0 29 // Primary Stream 1 Frame Buffer Address 1. 30 #define PRI_STREAM_FBUF_ADDR1 0x81c4 31 // Primary Stream 1 Stride. 32 #define PRI_STREAM_STRIDE 0x81c8 33 34 // Stream Processor 2. 35 36 // Primary Stream 2 Frame Buffer Address 0. 37 #define PRI_STREAM2_FBUF_ADDR0 0x81b0 38 // Primary Stream 2 Frame Buffer Address 1. 39 #define PRI_STREAM2_FBUF_ADDR1 0x81b4 40 // Primary Stream 2 Stride. 41 #define PRI_STREAM2_STRIDE 0x81b8 42 43 #define MEMORY_CTRL0_REG 0xCA 44 #define MEMORY_CONFIG_REG 0x31 45 46 // Bitmap descriptor register. 47 #define S3_GLB_BD_LOW 0x8168 48 #define S3_GLB_BD_HIGH 0x816C 49 #define S3_PRI_BD_LOW 0x8170 50 #define S3_PRI_BD_HIGH 0x8174 51 #define S3_SEC_BD_LOW 0x8178 52 #define S3_SEC_BD_HIGH 0x817c 53 54 #define MEM_PS1 0x10 // CRCA_4 :Primary stream 1 55 #define MEM_PS2 0x20 // CRCA_5 :Primary stream 2 56 57 #define SRC_BASE 0xa4d4 58 #define DEST_BASE 0xa4d8 59 #define CLIP_L_R 0xa4dc 60 #define CLIP_T_B 0xa4e0 61 #define DEST_SRC_STR 0xa4e4 62 #define MONO_PAT_0 0xa4e8 63 #define MONO_PAT_1 0xa4ec 64 65 #define DISABLE_BLOCK_WRITE_2D 0x10 // CR88_4 =1 : disable block write 66 67 #define STATUS_WORD0 (ReadReg32(0x48C00)) 68 #define ALT_STATUS_WORD0 (ReadReg32(0x48C60)) 69 #define MAXFIFO 0x7f00 70 71 // BCI definitions. 72 //================= 73 74 #define TILE_FORMAT_LINEAR 0 75 76 // BD - BCI enable. 77 #define BCI_ENABLE 8 // savage4, MX, IX, 3D 78 #define BCI_ENABLE_TWISTER 0 // twister, prosavage, DDR, supersavage, 2000 79 80 #define S3_BIG_ENDIAN 4 81 #define S3_LITTLE_ENDIAN 0 82 #define S3_BD64 1 83 84 #define BCI_BUFFER_OFFSET 0x10000 85 86 #define BCI_GET_PTR vuint32* bci_ptr = ((uint32*)(gInfo.regs + BCI_BUFFER_OFFSET)) 87 #define BCI_SEND(dw) (*bci_ptr++ = ((uint32)(dw))) 88 89 #define BCI_CMD_NOP 0x40000000 90 #define BCI_CMD_RECT 0x48000000 91 #define BCI_CMD_RECT_XP 0x01000000 92 #define BCI_CMD_RECT_YP 0x02000000 93 #define BCI_CMD_GET_ROP(cmd) (((cmd) >> 16) & 0xFF) 94 #define BCI_CMD_SET_ROP(cmd, rop) ((cmd) |= ((rop & 0xFF) << 16)) 95 96 #define BCI_CMD_SEND_COLOR 0x00008000 97 #define BCI_CMD_DEST_PBD_NEW 0x00000C00 98 #define BCI_CMD_SRC_SOLID 0x00000000 99 #define BCI_CMD_SRC_SBD_COLOR_NEW 0x00000140 100 101 #define BCI_W_H(w, h) ((((h) << 16) | (w)) & 0x0FFF0FFF) 102 #define BCI_X_Y(x, y) ((((y) << 16) | (x)) & 0x0FFF0FFF) 103 104 105 static inline void VerticalRetraceWait() 106 { 107 if (ReadCrtcReg(0x17) & 0x80) { 108 int i = 0x10000; 109 while ((ReadReg8(SYSTEM_CONTROL_REG) & 0x08) == 0x08 && i--) ; 110 i = 0x10000; 111 while ((ReadReg8(SYSTEM_CONTROL_REG) & 0x08) == 0x00 && i--) ; 112 } 113 } 114 115 116 #endif // __SAVAGE_H__ 117