1 /* 2 Haiku S3 Savage driver adapted from the X.org Savage driver. 3 4 Copyright (C) 1994-2000 The XFree86 Project, Inc. All Rights Reserved. 5 Copyright (c) 2003-2006, X.Org Foundation 6 7 Copyright 2007-2008 Haiku, Inc. All rights reserved. 8 Distributed under the terms of the MIT license. 9 10 Authors: 11 Gerald Zajac 2006-2008 12 */ 13 14 #ifndef __SAVAGE_H__ 15 #define __SAVAGE_H__ 16 17 18 19 #define CURSOR_BYTES 1024 // bytes used for cursor image in video memory 20 21 #define ADVANCED_FUNC_CTRL 0x850C 22 #define SYSTEM_CONTROL_REG 0x83DA 23 24 25 // Stream Processor 1. 26 27 // Primary Stream 1 Frame Buffer Address 0. 28 #define PRI_STREAM_FBUF_ADDR0 0x81c0 29 // Primary Stream 1 Frame Buffer Address 1. 30 #define PRI_STREAM_FBUF_ADDR1 0x81c4 31 // Primary Stream 1 Stride. 32 #define PRI_STREAM_STRIDE 0x81c8 33 34 // Stream Processor 2. 35 36 // Primary Stream 2 Frame Buffer Address 0. 37 #define PRI_STREAM2_FBUF_ADDR0 0x81b0 38 // Primary Stream 2 Frame Buffer Address 1. 39 #define PRI_STREAM2_FBUF_ADDR1 0x81b4 40 // Primary Stream 2 Stride. 41 #define PRI_STREAM2_STRIDE 0x81b8 42 43 #define S3_GLOBAL_GBD_REG 0x816C // global bitmap descriptor register 44 45 #define MEMORY_CTRL0_REG 0xCA 46 #define MEM_PS1 0x10 // CRCA_4 :Primary stream 1 47 #define MEM_PS2 0x20 // CRCA_5 :Primary stream 2 48 49 #define SRC_BASE 0xa4d4 50 #define DEST_BASE 0xa4d8 51 #define CLIP_L_R 0xa4dc 52 #define CLIP_T_B 0xa4e0 53 #define DEST_SRC_STR 0xa4e4 54 #define MONO_PAT_0 0xa4e8 55 #define MONO_PAT_1 0xa4ec 56 57 #define DISABLE_BLOCK_WRITE_2D 0x10 // CR88_4 =1 : disable block write 58 59 #define STATUS_WORD0 (ReadReg32(0x48C00)) 60 #define ALT_STATUS_WORD0 (ReadReg32(0x48C60)) 61 #define MAXFIFO 0x7f00 62 63 // BCI definitions. 64 //================= 65 66 #define TILE_FORMAT_LINEAR 0 67 68 #define BCI_ENABLE 8 // savage4, MX, IX, 3D 69 #define BCI_ENABLE_TWISTER 0 // twister, prosavage, DDR, supersavage, 2000 70 71 #define S3_BIG_ENDIAN 4 72 #define S3_LITTLE_ENDIAN 0 73 #define S3_BD64 1 74 75 #define BCI_BD_BW_DISABLE 0x10000000 76 #define BCI_BUFFER_OFFSET 0x10000 77 78 #define BCI_GET_PTR vuint32* bci_ptr = ((uint32*)(gInfo.regs + BCI_BUFFER_OFFSET)) 79 #define BCI_SEND(dw) (*bci_ptr++ = ((uint32)(dw))) 80 81 #define BCI_CMD_NOP 0x40000000 82 #define BCI_CMD_RECT 0x48000000 83 #define BCI_CMD_RECT_XP 0x01000000 84 #define BCI_CMD_RECT_YP 0x02000000 85 #define BCI_CMD_GET_ROP(cmd) (((cmd) >> 16) & 0xFF) 86 #define BCI_CMD_SET_ROP(cmd, rop) ((cmd) |= ((rop & 0xFF) << 16)) 87 88 #define BCI_CMD_SEND_COLOR 0x00008000 89 #define BCI_CMD_DEST_PBD_NEW 0x00000C00 90 #define BCI_CMD_SRC_SOLID 0x00000000 91 #define BCI_CMD_SRC_SBD_COLOR_NEW 0x00000140 92 93 #define BCI_W_H(w, h) ((((h) << 16) | (w)) & 0x0FFF0FFF) 94 #define BCI_X_Y(x, y) ((((y) << 16) | (x)) & 0x0FFF0FFF) 95 96 97 static inline void VerticalRetraceWait() 98 { 99 if (ReadCrtcReg(0x17) & 0x80) { 100 int i = 0x10000; 101 while ((ReadReg8(SYSTEM_CONTROL_REG) & 0x08) == 0x08 && i--) ; 102 i = 0x10000; 103 while ((ReadReg8(SYSTEM_CONTROL_REG) & 0x08) == 0x00 && i--) ; 104 } 105 } 106 107 108 #endif // __SAVAGE_H__ 109