1 /* 2 * Copyright 2006-2011, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Alexander von Gluck, kallisti5@unixzen.com 7 */ 8 #ifndef RADEON_HD_PLL_H 9 #define RADEON_HD_PLL_H 10 11 12 #include <SupportDefs.h> 13 14 15 #define MAX_TOLERANCE 10 16 17 #define PLL_MIN_DEFAULT 16000 18 #define PLL_MAX_DEFAULT 400000 19 #define PLL_REFERENCE_DEFAULT 27000 20 21 /* limited by the number of bits available */ 22 #define FB_DIV_MIN 4 23 #define FB_DIV_LIMIT 2048 24 #define REF_DIV_MIN 2 25 #define REF_DIV_LIMIT 1024 26 #define POST_DIV_MIN 2 27 #define POST_DIV_LIMIT 127 28 29 /* pll flags */ 30 #define PLL_USE_BIOS_DIVS (1 << 0) 31 #define PLL_NO_ODD_POST_DIV (1 << 1) 32 #define PLL_USE_REF_DIV (1 << 2) 33 #define PLL_LEGACY (1 << 3) 34 #define PLL_PREFER_LOW_REF_DIV (1 << 4) 35 #define PLL_PREFER_HIGH_REF_DIV (1 << 5) 36 #define PLL_PREFER_LOW_FB_DIV (1 << 6) 37 #define PLL_PREFER_HIGH_FB_DIV (1 << 7) 38 #define PLL_PREFER_LOW_POST_DIV (1 << 8) 39 #define PLL_PREFER_HIGH_POST_DIV (1 << 9) 40 #define PLL_USE_FRAC_FB_DIV (1 << 10) 41 #define PLL_PREFER_CLOSEST_LOWER (1 << 11) 42 #define PLL_USE_POST_DIV (1 << 12) 43 #define PLL_IS_LCD (1 << 13) 44 #define PLL_PREFER_MINM_OVER_MAXP (1 << 14) 45 46 47 struct pll_info { 48 /* pixel clock to be programmed (kHz)*/ 49 uint32 pixelClock; 50 51 /* external DisplayPort clock freq */ 52 uint32 dpExternalClock; 53 54 /* flags for the current clock */ 55 uint32 flags; 56 57 /* pll id */ 58 uint32 id; 59 60 /* reference frequency */ 61 uint32 referenceFreq; 62 63 /* fixed dividers */ 64 uint32 postDiv; 65 uint32 referenceDiv; 66 uint32 feedbackDiv; 67 uint32 feedbackDivFrac; 68 69 /* pll in/out limits */ 70 uint32 pllInMin; 71 uint32 pllInMax; 72 uint32 pllOutMin; 73 uint32 pllOutMax; 74 uint32 lcdPllOutMin; 75 uint32 lcdPllOutMax; 76 uint32 bestVco; 77 78 /* divider limits */ 79 uint32 minRefDiv; 80 uint32 maxRefDiv; 81 uint32 minPostDiv; 82 uint32 maxPostDiv; 83 uint32 minFeedbackDiv; 84 uint32 maxFeedbackDiv; 85 uint32 minFeedbackDivFrac; 86 uint32 maxFeedbackDivFrac; 87 }; 88 89 90 status_t pll_adjust(pll_info* pll, uint8 crtcID); 91 status_t pll_compute(pll_info* pll); 92 void pll_setup_flags(pll_info* pll, uint8 crtcID); 93 status_t pll_limit_probe(pll_info* pll); 94 status_t pll_set(uint8 pllID, uint32 pixelClock, uint8 crtcID); 95 96 97 #endif /* RADEON_HD_PLL_H */ 98