1 /* 2 * Copyright 2006-2011, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Alexander von Gluck, kallisti5@unixzen.com 7 */ 8 9 10 #include "pll.h" 11 12 #include <stdio.h> 13 #include <stdlib.h> 14 #include <string.h> 15 #include <math.h> 16 17 #include "accelerant_protos.h" 18 #include "accelerant.h" 19 #include "bios.h" 20 #include "connector.h" 21 #include "display.h" 22 #include "displayport.h" 23 #include "encoder.h" 24 #include "utility.h" 25 26 27 #define TRACE_PLL 28 #ifdef TRACE_PLL 29 extern "C" void _sPrintf(const char* format, ...); 30 # define TRACE(x...) _sPrintf("radeon_hd: " x) 31 #else 32 # define TRACE(x...) ; 33 #endif 34 35 #define ERROR(x...) _sPrintf("radeon_hd: " x) 36 37 38 status_t 39 pll_limit_probe(pll_info* pll) 40 { 41 uint8 tableMajor; 42 uint8 tableMinor; 43 uint16 tableOffset; 44 45 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 46 if (atom_parse_data_header(gAtomContext, index, NULL, 47 &tableMajor, &tableMinor, &tableOffset) != B_OK) { 48 ERROR("%s: Couldn't parse data header\n", __func__); 49 return B_ERROR; 50 } 51 52 TRACE("%s: table %" B_PRIu8 ".%" B_PRIu8 "\n", __func__, 53 tableMajor, tableMinor); 54 55 union atomFirmwareInfo { 56 ATOM_FIRMWARE_INFO info; 57 ATOM_FIRMWARE_INFO_V1_2 info_12; 58 ATOM_FIRMWARE_INFO_V1_3 info_13; 59 ATOM_FIRMWARE_INFO_V1_4 info_14; 60 ATOM_FIRMWARE_INFO_V2_1 info_21; 61 ATOM_FIRMWARE_INFO_V2_2 info_22; 62 }; 63 union atomFirmwareInfo* firmwareInfo 64 = (union atomFirmwareInfo*)(gAtomContext->bios + tableOffset); 65 66 /* pixel clock limits */ 67 pll->referenceFreq 68 = B_LENDIAN_TO_HOST_INT16(firmwareInfo->info.usReferenceClock) * 10; 69 70 if (tableMinor < 2) { 71 pll->pllOutMin 72 = B_LENDIAN_TO_HOST_INT16( 73 firmwareInfo->info.usMinPixelClockPLL_Output) * 10; 74 } else { 75 pll->pllOutMin 76 = B_LENDIAN_TO_HOST_INT32( 77 firmwareInfo->info_12.ulMinPixelClockPLL_Output) * 10; 78 } 79 80 pll->pllOutMax 81 = B_LENDIAN_TO_HOST_INT32( 82 firmwareInfo->info.ulMaxPixelClockPLL_Output) * 10; 83 84 if (tableMinor >= 4) { 85 pll->lcdPllOutMin 86 = B_LENDIAN_TO_HOST_INT16( 87 firmwareInfo->info_14.usLcdMinPixelClockPLL_Output) * 1000; 88 89 if (pll->lcdPllOutMin == 0) 90 pll->lcdPllOutMin = pll->pllOutMin; 91 92 pll->lcdPllOutMax 93 = B_LENDIAN_TO_HOST_INT16( 94 firmwareInfo->info_14.usLcdMaxPixelClockPLL_Output) * 1000; 95 96 if (pll->lcdPllOutMax == 0) 97 pll->lcdPllOutMax = pll->pllOutMax; 98 99 } else { 100 pll->lcdPllOutMin = pll->pllOutMin; 101 pll->lcdPllOutMax = pll->pllOutMax; 102 } 103 104 if (pll->pllOutMin == 0) { 105 pll->pllOutMin = 64800 * 10; 106 // Avivo+ limit 107 } 108 109 pll->minPostDiv = POST_DIV_MIN; 110 pll->maxPostDiv = POST_DIV_LIMIT; 111 pll->minRefDiv = REF_DIV_MIN; 112 pll->maxRefDiv = REF_DIV_LIMIT; 113 pll->minFeedbackDiv = FB_DIV_MIN; 114 pll->maxFeedbackDiv = FB_DIV_LIMIT; 115 116 pll->pllInMin = B_LENDIAN_TO_HOST_INT16( 117 firmwareInfo->info.usMinPixelClockPLL_Input) * 10; 118 pll->pllInMax = B_LENDIAN_TO_HOST_INT16( 119 firmwareInfo->info.usMaxPixelClockPLL_Input) * 10; 120 121 TRACE("%s: referenceFreq: %" B_PRIu16 "; pllOutMin: %" B_PRIu16 "; " 122 " pllOutMax: %" B_PRIu16 "; pllInMin: %" B_PRIu16 ";" 123 "pllInMax: %" B_PRIu16 "\n", __func__, pll->referenceFreq, 124 pll->pllOutMin, pll->pllOutMax, pll->pllInMin, pll->pllInMax); 125 126 return B_OK; 127 } 128 129 130 status_t 131 pll_ppll_ss_probe(pll_info* pll, uint32 ssID) 132 { 133 uint8 tableMajor; 134 uint8 tableMinor; 135 uint16 headerOffset; 136 uint16 headerSize; 137 138 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info); 139 if (atom_parse_data_header(gAtomContext, index, &headerSize, 140 &tableMajor, &tableMinor, &headerOffset) != B_OK) { 141 ERROR("%s: Couldn't parse data header\n", __func__); 142 return B_ERROR; 143 } 144 145 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info 146 = (struct _ATOM_SPREAD_SPECTRUM_INFO*)((uint16*)gAtomContext->bios 147 + headerOffset); 148 149 int indices = (headerSize - sizeof(ATOM_COMMON_TABLE_HEADER)) 150 / sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT); 151 152 int i; 153 for (i = 0; i < indices; i++) { 154 if (ss_info->asSS_Info[i].ucSS_Id == ssID) { 155 pll->ssPercentage = B_LENDIAN_TO_HOST_INT16( 156 ss_info->asSS_Info[i].usSpreadSpectrumPercentage); 157 pll->ssType = ss_info->asSS_Info[i].ucSpreadSpectrumType; 158 pll->ssStep = ss_info->asSS_Info[i].ucSS_Step; 159 pll->ssDelay = ss_info->asSS_Info[i].ucSS_Delay; 160 pll->ssRange = ss_info->asSS_Info[i].ucSS_Range; 161 pll->ssReferenceDiv 162 = ss_info->asSS_Info[i].ucRecommendedRef_Div; 163 return B_OK; 164 } 165 } 166 167 return B_ERROR; 168 } 169 170 171 status_t 172 pll_asic_ss_probe(pll_info* pll, uint32 ssID) 173 { 174 uint8 tableMajor; 175 uint8 tableMinor; 176 uint16 headerOffset; 177 uint16 headerSize; 178 179 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 180 if (atom_parse_data_header(gAtomContext, index, &headerSize, 181 &tableMajor, &tableMinor, &headerOffset) != B_OK) { 182 ERROR("%s: Couldn't parse data header\n", __func__); 183 return B_ERROR; 184 } 185 186 union asicSSInfo { 187 struct _ATOM_ASIC_INTERNAL_SS_INFO info; 188 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2; 189 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3; 190 }; 191 192 union asicSSInfo *ss_info 193 = (union asicSSInfo*)((uint16*)gAtomContext->bios + headerOffset); 194 195 int i; 196 int indices; 197 switch (tableMajor) { 198 case 1: 199 indices = (headerSize - sizeof(ATOM_COMMON_TABLE_HEADER)) 200 / sizeof(ATOM_ASIC_SS_ASSIGNMENT); 201 202 for (i = 0; i < indices; i++) { 203 if (ss_info->info.asSpreadSpectrum[i].ucClockIndication 204 != ssID) { 205 continue; 206 } 207 TRACE("%s: ss match found\n", __func__); 208 if (pll->pixelClock > B_LENDIAN_TO_HOST_INT32( 209 ss_info->info.asSpreadSpectrum[i].ulTargetClockRange)) { 210 TRACE("%s: pixelClock > targetClockRange!\n", __func__); 211 continue; 212 } 213 214 pll->ssPercentage = B_LENDIAN_TO_HOST_INT16( 215 ss_info->info.asSpreadSpectrum[i].usSpreadSpectrumPercentage 216 ); 217 218 pll->ssType 219 = ss_info->info.asSpreadSpectrum[i].ucSpreadSpectrumMode; 220 pll->ssRate = B_LENDIAN_TO_HOST_INT16( 221 ss_info->info.asSpreadSpectrum[i].usSpreadRateInKhz); 222 return B_OK; 223 } 224 break; 225 case 2: 226 indices = (headerSize - sizeof(ATOM_COMMON_TABLE_HEADER)) 227 / sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2); 228 229 for (i = 0; i < indices; i++) { 230 if (ss_info->info_2.asSpreadSpectrum[i].ucClockIndication 231 != ssID) { 232 continue; 233 } 234 TRACE("%s: ss match found\n", __func__); 235 if (pll->pixelClock > B_LENDIAN_TO_HOST_INT32( 236 ss_info->info_2.asSpreadSpectrum[i].ulTargetClockRange)) { 237 TRACE("%s: pixelClock > targetClockRange!\n", __func__); 238 continue; 239 } 240 241 pll->ssPercentage = B_LENDIAN_TO_HOST_INT16( 242 ss_info 243 ->info_2.asSpreadSpectrum[i].usSpreadSpectrumPercentage 244 ); 245 246 pll->ssType 247 = ss_info->info_2.asSpreadSpectrum[i].ucSpreadSpectrumMode; 248 pll->ssRate = B_LENDIAN_TO_HOST_INT16( 249 ss_info->info_2.asSpreadSpectrum[i].usSpreadRateIn10Hz); 250 return B_OK; 251 } 252 break; 253 case 3: 254 indices = (headerSize - sizeof(ATOM_COMMON_TABLE_HEADER)) 255 / sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3); 256 257 for (i = 0; i < indices; i++) { 258 if (ss_info->info_3.asSpreadSpectrum[i].ucClockIndication 259 != ssID) { 260 continue; 261 } 262 TRACE("%s: ss match found\n", __func__); 263 if (pll->pixelClock > B_LENDIAN_TO_HOST_INT32( 264 ss_info->info_3.asSpreadSpectrum[i].ulTargetClockRange)) { 265 TRACE("%s: pixelClock > targetClockRange!\n", __func__); 266 continue; 267 } 268 269 pll->ssPercentage = B_LENDIAN_TO_HOST_INT16( 270 ss_info 271 ->info_3.asSpreadSpectrum[i].usSpreadSpectrumPercentage 272 ); 273 274 pll->ssType 275 = ss_info->info_3.asSpreadSpectrum[i].ucSpreadSpectrumMode; 276 pll->ssRate = B_LENDIAN_TO_HOST_INT16( 277 ss_info->info_3.asSpreadSpectrum[i].usSpreadRateIn10Hz); 278 return B_OK; 279 } 280 break; 281 default: 282 ERROR("%s: Unknown SS table version!\n", __func__); 283 return B_ERROR; 284 } 285 286 ERROR("%s: No potential spread spectrum data found!\n", __func__); 287 return B_ERROR; 288 } 289 290 291 void 292 pll_compute_post_divider(pll_info* pll) 293 { 294 if ((pll->flags & PLL_USE_POST_DIV) != 0) { 295 TRACE("%s: using AtomBIOS post divider\n", __func__); 296 return; 297 } 298 299 uint32 vco; 300 if ((pll->flags & PLL_PREFER_MINM_OVER_MAXP) != 0) { 301 if ((pll->flags & PLL_IS_LCD) != 0) 302 vco = pll->lcdPllOutMin; 303 else 304 vco = pll->pllOutMin; 305 } else { 306 if ((pll->flags & PLL_IS_LCD) != 0) 307 vco = pll->lcdPllOutMax; 308 else 309 vco = pll->pllOutMin; 310 } 311 312 TRACE("%s: vco = %" B_PRIu32 "\n", __func__, vco); 313 314 uint32 postDivider = vco / pll->pixelClock; 315 uint32 tmp = vco % pll->pixelClock; 316 317 if ((pll->flags & PLL_PREFER_MINM_OVER_MAXP) != 0) { 318 if (tmp) 319 postDivider++; 320 } else { 321 if (!tmp) 322 postDivider--; 323 } 324 325 if (postDivider > pll->maxPostDiv) 326 postDivider = pll->maxPostDiv; 327 else if (postDivider < pll->minPostDiv) 328 postDivider = pll->minPostDiv; 329 330 pll->postDiv = postDivider; 331 TRACE("%s: postDiv = %" B_PRIu32 "\n", __func__, postDivider); 332 } 333 334 335 status_t 336 pll_compute(pll_info* pll) 337 { 338 pll_compute_post_divider(pll); 339 340 uint32 targetClock = pll->pixelClock; 341 342 pll->feedbackDiv = 0; 343 pll->feedbackDivFrac = 0; 344 uint32 referenceFrequency = pll->referenceFreq; 345 346 if ((pll->flags & PLL_USE_REF_DIV) != 0) { 347 TRACE("%s: using AtomBIOS reference divider\n", __func__); 348 } else { 349 TRACE("%s: using minimum reference divider\n", __func__); 350 pll->referenceDiv = pll->minRefDiv; 351 } 352 353 if ((pll->flags & PLL_USE_FRAC_FB_DIV) != 0) { 354 TRACE("%s: using AtomBIOS fractional feedback divider\n", __func__); 355 356 uint32 tmp = pll->postDiv * pll->referenceDiv; 357 tmp *= targetClock; 358 pll->feedbackDiv = tmp / pll->referenceFreq; 359 pll->feedbackDivFrac = tmp % pll->referenceFreq; 360 361 if (pll->feedbackDiv > pll->maxFeedbackDiv) 362 pll->feedbackDiv = pll->maxFeedbackDiv; 363 else if (pll->feedbackDiv < pll->minFeedbackDiv) 364 pll->feedbackDiv = pll->minFeedbackDiv; 365 366 pll->feedbackDivFrac 367 = (100 * pll->feedbackDivFrac) / pll->referenceFreq; 368 369 if (pll->feedbackDivFrac >= 5) { 370 pll->feedbackDivFrac -= 5; 371 pll->feedbackDivFrac /= 10; 372 pll->feedbackDivFrac++; 373 } 374 if (pll->feedbackDivFrac >= 10) { 375 pll->feedbackDiv++; 376 pll->feedbackDivFrac = 0; 377 } 378 } else { 379 TRACE("%s: performing fractional feedback calculations\n", __func__); 380 381 while (pll->referenceDiv <= pll->maxRefDiv) { 382 // get feedback divider 383 uint32 retroEncabulator = pll->postDiv * pll->referenceDiv; 384 385 retroEncabulator *= targetClock; 386 pll->feedbackDiv = retroEncabulator / referenceFrequency; 387 pll->feedbackDivFrac 388 = retroEncabulator % referenceFrequency; 389 390 if (pll->feedbackDiv > pll->maxFeedbackDiv) 391 pll->feedbackDiv = pll->maxFeedbackDiv; 392 else if (pll->feedbackDiv < pll->minFeedbackDiv) 393 pll->feedbackDiv = pll->minFeedbackDiv; 394 395 if (pll->feedbackDivFrac >= (referenceFrequency / 2)) 396 pll->feedbackDiv++; 397 398 pll->feedbackDivFrac = 0; 399 400 if (pll->referenceDiv == 0 401 || pll->postDiv == 0 402 || targetClock == 0) { 403 TRACE("%s: Caught division by zero!\n", __func__); 404 TRACE("%s: referenceDiv %" B_PRIu32 "\n", 405 __func__, pll->referenceDiv); 406 TRACE("%s: postDiv %" B_PRIu32 "\n", 407 __func__, pll->postDiv); 408 TRACE("%s: targetClock %" B_PRIu32 "\n", 409 __func__, targetClock); 410 return B_ERROR; 411 } 412 uint32 tmp = (referenceFrequency * pll->feedbackDiv) 413 / (pll->postDiv * pll->referenceDiv); 414 tmp = (tmp * 1000) / targetClock; 415 416 if (tmp > (1000 + (MAX_TOLERANCE / 10))) 417 pll->referenceDiv++; 418 else if (tmp >= (1000 - (MAX_TOLERANCE / 10))) 419 break; 420 else 421 pll->referenceDiv++; 422 } 423 } 424 425 if (pll->referenceDiv == 0 || pll->postDiv == 0) { 426 TRACE("%s: Caught division by zero of post or reference divider\n", 427 __func__); 428 return B_ERROR; 429 } 430 431 uint32 calculatedClock 432 = ((referenceFrequency * pll->feedbackDiv * 10) 433 + (referenceFrequency * pll->feedbackDivFrac)) 434 / (pll->referenceDiv * pll->postDiv * 10); 435 436 TRACE("%s: pixel clock: %" B_PRIu32 " gives:" 437 " feedbackDivider = %" B_PRIu32 ".%" B_PRIu32 438 "; referenceDivider = %" B_PRIu32 "; postDivider = %" B_PRIu32 "\n", 439 __func__, pll->pixelClock, pll->feedbackDiv, pll->feedbackDivFrac, 440 pll->referenceDiv, pll->postDiv); 441 442 if (pll->pixelClock != calculatedClock) { 443 TRACE("%s: pixel clock %" B_PRIu32 " was changed to %" B_PRIu32 "\n", 444 __func__, pll->pixelClock, calculatedClock); 445 pll->pixelClock = calculatedClock; 446 } 447 448 return B_OK; 449 } 450 451 452 void 453 pll_setup_flags(pll_info* pll, uint8 crtcID) 454 { 455 radeon_shared_info &info = *gInfo->shared_info; 456 uint32 connectorIndex = gDisplay[crtcID]->connectorIndex; 457 uint32 encoderFlags = gConnector[connectorIndex]->encoder.flags; 458 459 uint32 dceVersion = (info.dceMajor * 100) + info.dceMinor; 460 461 TRACE("%s: CRTC: %" B_PRIu8 ", PLL: %" B_PRIu8 "\n", __func__, 462 crtcID, pll->id); 463 464 if (dceVersion >= 302 && pll->pixelClock > 200000) 465 pll->flags |= PLL_PREFER_HIGH_FB_DIV; 466 else 467 pll->flags |= PLL_PREFER_LOW_REF_DIV; 468 469 if (info.chipsetID < RADEON_RV770) 470 pll->flags |= PLL_PREFER_MINM_OVER_MAXP; 471 472 if ((encoderFlags & ATOM_DEVICE_LCD_SUPPORT) != 0) { 473 pll->flags |= PLL_IS_LCD; 474 475 // use reference divider for spread spectrum 476 TRACE("%s: Spread Spectrum is %" B_PRIu32 "%%\n", __func__, 477 pll->ssPercentage); 478 if (pll->ssPercentage > 0) { 479 if (pll->ssReferenceDiv > 0) { 480 TRACE("%s: using Spread Spectrum reference divider. " 481 "refDiv was: %" B_PRIu32 ", now: %" B_PRIu32 "\n", 482 __func__, pll->referenceDiv, pll->ssReferenceDiv); 483 pll->flags |= PLL_USE_REF_DIV; 484 pll->referenceDiv = pll->ssReferenceDiv; 485 486 // TODO: IS AVIVO+? 487 pll->flags |= PLL_USE_FRAC_FB_DIV; 488 } 489 } 490 } 491 492 if ((encoderFlags & ATOM_DEVICE_TV_SUPPORT) != 0) 493 pll->flags |= PLL_PREFER_CLOSEST_LOWER; 494 495 if ((info.chipsetFlags & CHIP_APU) != 0) { 496 // Use fractional feedback on APU's 497 pll->flags |= PLL_USE_FRAC_FB_DIV; 498 } 499 } 500 501 502 status_t 503 pll_adjust(pll_info* pll, display_mode* mode, uint8 crtcID) 504 { 505 radeon_shared_info &info = *gInfo->shared_info; 506 507 uint32 pixelClock = pll->pixelClock; 508 // original as pixel_clock will be adjusted 509 510 uint32 connectorIndex = gDisplay[crtcID]->connectorIndex; 511 connector_info* connector = gConnector[connectorIndex]; 512 513 uint32 encoderID = connector->encoder.objectID; 514 uint32 encoderMode = display_get_encoder_mode(connectorIndex); 515 uint32 encoderFlags = connector->encoder.flags; 516 517 uint32 externalEncoderID = 0; 518 if (connector->encoderExternal.isDPBridge) 519 externalEncoderID = connector->encoderExternal.objectID; 520 521 if (info.dceMajor >= 3) { 522 523 uint8 tableMajor; 524 uint8 tableMinor; 525 526 int index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); 527 if (atom_parse_cmd_header(gAtomContext, index, &tableMajor, &tableMinor) 528 != B_OK) { 529 ERROR("%s: Couldn't find AtomBIOS PLL adjustment\n", __func__); 530 return B_ERROR; 531 } 532 533 TRACE("%s: table %" B_PRIu8 ".%" B_PRIu8 "\n", __func__, 534 tableMajor, tableMinor); 535 536 // Prepare arguments for AtomBIOS call 537 union adjustPixelClock { 538 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; 539 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; 540 }; 541 union adjustPixelClock args; 542 memset(&args, 0, sizeof(args)); 543 544 switch (tableMajor) { 545 case 1: 546 switch (tableMinor) { 547 case 1: 548 case 2: 549 args.v1.usPixelClock 550 = B_HOST_TO_LENDIAN_INT16(pixelClock / 10); 551 args.v1.ucTransmitterID = encoderID; 552 args.v1.ucEncodeMode = encoderMode; 553 if (pll->ssPercentage > 0) { 554 args.v1.ucConfig 555 |= ADJUST_DISPLAY_CONFIG_SS_ENABLE; 556 } 557 558 atom_execute_table(gAtomContext, index, (uint32*)&args); 559 // get returned adjusted clock 560 pll->pixelClock 561 = B_LENDIAN_TO_HOST_INT16(args.v1.usPixelClock); 562 pll->pixelClock *= 10; 563 break; 564 case 3: 565 args.v3.sInput.usPixelClock 566 = B_HOST_TO_LENDIAN_INT16(pixelClock / 10); 567 args.v3.sInput.ucTransmitterID = encoderID; 568 args.v3.sInput.ucEncodeMode = encoderMode; 569 args.v3.sInput.ucDispPllConfig = 0; 570 if (pll->ssPercentage > 0) { 571 args.v3.sInput.ucDispPllConfig 572 |= DISPPLL_CONFIG_SS_ENABLE; 573 } 574 575 // Handle DP adjustments 576 if (encoderMode == ATOM_ENCODER_MODE_DP 577 || encoderMode == ATOM_ENCODER_MODE_DP_MST) { 578 TRACE("%s: encoderMode is DP\n", __func__); 579 args.v3.sInput.ucDispPllConfig 580 |= DISPPLL_CONFIG_COHERENT_MODE; 581 /* 16200 or 27000 */ 582 uint32 dpLinkSpeed 583 = dp_get_link_rate(connectorIndex, mode); 584 args.v3.sInput.usPixelClock 585 = B_HOST_TO_LENDIAN_INT16(dpLinkSpeed / 10); 586 } else if ((encoderFlags & ATOM_DEVICE_DFP_SUPPORT) 587 != 0) { 588 #if 0 589 if (encoderMode == ATOM_ENCODER_MODE_HDMI) { 590 /* deep color support */ 591 args.v3.sInput.usPixelClock = 592 cpu_to_le16((mode->clock * bpc / 8) / 10); 593 } 594 #endif 595 if (pixelClock > 165000) { 596 args.v3.sInput.ucDispPllConfig 597 |= DISPPLL_CONFIG_DUAL_LINK; 598 } 599 if (1) { // dig coherent mode? 600 args.v3.sInput.ucDispPllConfig 601 |= DISPPLL_CONFIG_COHERENT_MODE; 602 } 603 } 604 605 args.v3.sInput.ucExtTransmitterID = externalEncoderID; 606 607 atom_execute_table(gAtomContext, index, (uint32*)&args); 608 609 // get returned adjusted clock 610 pll->pixelClock 611 = B_LENDIAN_TO_HOST_INT32( 612 args.v3.sOutput.ulDispPllFreq); 613 pll->pixelClock *= 10; 614 // convert to kHz for storage 615 616 if (args.v3.sOutput.ucRefDiv) { 617 pll->flags |= PLL_USE_FRAC_FB_DIV; 618 pll->flags |= PLL_USE_REF_DIV; 619 pll->referenceDiv = args.v3.sOutput.ucRefDiv; 620 } 621 if (args.v3.sOutput.ucPostDiv) { 622 pll->flags |= PLL_USE_FRAC_FB_DIV; 623 pll->flags |= PLL_USE_POST_DIV; 624 pll->postDiv = args.v3.sOutput.ucPostDiv; 625 } 626 break; 627 default: 628 TRACE("%s: ERROR: table version %" B_PRIu8 ".%" B_PRIu8 629 " unknown\n", __func__, tableMajor, tableMinor); 630 return B_ERROR; 631 } 632 break; 633 default: 634 TRACE("%s: ERROR: table version %" B_PRIu8 ".%" B_PRIu8 635 " unknown\n", __func__, tableMajor, tableMinor); 636 return B_ERROR; 637 } 638 } 639 640 TRACE("%s: was: %" B_PRIu32 ", now: %" B_PRIu32 "\n", __func__, 641 pixelClock, pll->pixelClock); 642 643 return B_OK; 644 } 645 646 647 status_t 648 pll_set(display_mode* mode, uint8 crtcID) 649 { 650 uint32 connectorIndex = gDisplay[crtcID]->connectorIndex; 651 pll_info* pll = &gConnector[connectorIndex]->encoder.pll; 652 653 pll->pixelClock = mode->timing.pixel_clock; 654 655 radeon_shared_info &info = *gInfo->shared_info; 656 657 // Probe for PLL spread spectrum info; 658 pll->ssPercentage = 0; 659 pll->ssType = 0; 660 pll->ssStep = 0; 661 pll->ssDelay = 0; 662 pll->ssRange = 0; 663 pll->ssReferenceDiv = 0; 664 665 switch (display_get_encoder_mode(connectorIndex)) { 666 case ATOM_ENCODER_MODE_DP_MST: 667 case ATOM_ENCODER_MODE_DP: 668 if (info.dceMajor >= 4) 669 pll_asic_ss_probe(pll, ASIC_INTERNAL_SS_ON_DP); 670 else { 671 // TODO: DP Clock == 1.62Ghz? 672 pll_ppll_ss_probe(pll, ATOM_DP_SS_ID1); 673 } 674 break; 675 case ATOM_ENCODER_MODE_LVDS: 676 if (info.dceMajor >= 4) 677 pll_asic_ss_probe(pll, gInfo->lvdsSpreadSpectrumID); 678 else 679 pll_ppll_ss_probe(pll, gInfo->lvdsSpreadSpectrumID); 680 break; 681 case ATOM_ENCODER_MODE_DVI: 682 if (info.dceMajor >= 4) 683 pll_asic_ss_probe(pll, ASIC_INTERNAL_SS_ON_TMDS); 684 break; 685 case ATOM_ENCODER_MODE_HDMI: 686 if (info.dceMajor >= 4) 687 pll_asic_ss_probe(pll, ASIC_INTERNAL_SS_ON_HDMI); 688 break; 689 } 690 691 pll_setup_flags(pll, crtcID); 692 // set up any special flags 693 pll_adjust(pll, mode, crtcID); 694 // get any needed clock adjustments, set reference/post dividers 695 pll_compute(pll); 696 // compute dividers 697 698 display_crtc_ss(pll, ATOM_DISABLE); 699 // disable ss 700 701 uint8 tableMajor; 702 uint8 tableMinor; 703 704 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 705 atom_parse_cmd_header(gAtomContext, index, &tableMajor, &tableMinor); 706 707 TRACE("%s: table %" B_PRIu8 ".%" B_PRIu8 "\n", __func__, 708 tableMajor, tableMinor); 709 710 uint32 bitsPerColor = 8; 711 // TODO: Digital Depth, EDID 1.4+ on digital displays 712 // isn't in Haiku edid common code? 713 714 // Prepare arguments for AtomBIOS call 715 union setPixelClock { 716 SET_PIXEL_CLOCK_PS_ALLOCATION base; 717 PIXEL_CLOCK_PARAMETERS v1; 718 PIXEL_CLOCK_PARAMETERS_V2 v2; 719 PIXEL_CLOCK_PARAMETERS_V3 v3; 720 PIXEL_CLOCK_PARAMETERS_V5 v5; 721 PIXEL_CLOCK_PARAMETERS_V6 v6; 722 }; 723 union setPixelClock args; 724 memset(&args, 0, sizeof(args)); 725 726 switch (tableMinor) { 727 case 1: 728 args.v1.usPixelClock 729 = B_HOST_TO_LENDIAN_INT16(pll->pixelClock / 10); 730 args.v1.usRefDiv = B_HOST_TO_LENDIAN_INT16(pll->referenceDiv); 731 args.v1.usFbDiv = B_HOST_TO_LENDIAN_INT16(pll->feedbackDiv); 732 args.v1.ucFracFbDiv = pll->feedbackDivFrac; 733 args.v1.ucPostDiv = pll->postDiv; 734 args.v1.ucPpll = pll->id; 735 args.v1.ucCRTC = crtcID; 736 args.v1.ucRefDivSrc = 1; 737 break; 738 case 2: 739 args.v2.usPixelClock 740 = B_HOST_TO_LENDIAN_INT16(pll->pixelClock / 10); 741 args.v2.usRefDiv = B_HOST_TO_LENDIAN_INT16(pll->referenceDiv); 742 args.v2.usFbDiv = B_HOST_TO_LENDIAN_INT16(pll->feedbackDiv); 743 args.v2.ucFracFbDiv = pll->feedbackDivFrac; 744 args.v2.ucPostDiv = pll->postDiv; 745 args.v2.ucPpll = pll->id; 746 args.v2.ucCRTC = crtcID; 747 args.v2.ucRefDivSrc = 1; 748 break; 749 case 3: 750 args.v3.usPixelClock 751 = B_HOST_TO_LENDIAN_INT16(pll->pixelClock / 10); 752 args.v3.usRefDiv = B_HOST_TO_LENDIAN_INT16(pll->referenceDiv); 753 args.v3.usFbDiv = B_HOST_TO_LENDIAN_INT16(pll->feedbackDiv); 754 args.v3.ucFracFbDiv = pll->feedbackDivFrac; 755 args.v3.ucPostDiv = pll->postDiv; 756 args.v3.ucPpll = pll->id; 757 args.v3.ucMiscInfo = (pll->id << 2); 758 if (pll->ssPercentage > 0 759 && (pll->ssType & ATOM_EXTERNAL_SS_MASK) != 0) { 760 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC; 761 } 762 args.v3.ucTransmitterId 763 = gConnector[connectorIndex]->encoder.objectID; 764 args.v3.ucEncoderMode = display_get_encoder_mode(connectorIndex); 765 break; 766 case 5: 767 args.v5.ucCRTC = crtcID; 768 args.v5.usPixelClock 769 = B_HOST_TO_LENDIAN_INT16(pll->pixelClock / 10); 770 args.v5.ucRefDiv = pll->referenceDiv; 771 args.v5.usFbDiv = B_HOST_TO_LENDIAN_INT16(pll->feedbackDiv); 772 args.v5.ulFbDivDecFrac 773 = B_HOST_TO_LENDIAN_INT32(pll->feedbackDivFrac * 100000); 774 args.v5.ucPostDiv = pll->postDiv; 775 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ 776 if (pll->ssPercentage > 0 777 && (pll->ssType & ATOM_EXTERNAL_SS_MASK) != 0) { 778 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC; 779 } 780 switch (bitsPerColor) { 781 case 8: 782 default: 783 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP; 784 break; 785 case 10: 786 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP; 787 break; 788 } 789 args.v5.ucTransmitterID 790 = gConnector[connectorIndex]->encoder.objectID; 791 args.v5.ucEncoderMode 792 = display_get_encoder_mode(connectorIndex); 793 args.v5.ucPpll = pll->id; 794 break; 795 case 6: 796 args.v6.ulDispEngClkFreq 797 = B_HOST_TO_LENDIAN_INT32(crtcID << 24 | pll->pixelClock / 10); 798 args.v6.ucRefDiv = pll->referenceDiv; 799 args.v6.usFbDiv = B_HOST_TO_LENDIAN_INT16(pll->feedbackDiv); 800 args.v6.ulFbDivDecFrac 801 = B_HOST_TO_LENDIAN_INT32(pll->feedbackDivFrac * 100000); 802 args.v6.ucPostDiv = pll->postDiv; 803 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */ 804 if (pll->ssPercentage > 0 805 && (pll->ssType & ATOM_EXTERNAL_SS_MASK) != 0) { 806 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC; 807 } 808 switch (bitsPerColor) { 809 case 8: 810 default: 811 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP; 812 break; 813 case 10: 814 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP; 815 break; 816 case 12: 817 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP; 818 break; 819 case 16: 820 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP; 821 break; 822 } 823 args.v6.ucTransmitterID 824 = gConnector[connectorIndex]->encoder.objectID; 825 args.v6.ucEncoderMode = display_get_encoder_mode(connectorIndex); 826 args.v6.ucPpll = pll->id; 827 break; 828 default: 829 TRACE("%s: ERROR: table version %" B_PRIu8 ".%" B_PRIu8 " TODO\n", 830 __func__, tableMajor, tableMinor); 831 return B_ERROR; 832 } 833 834 TRACE("%s: set adjusted pixel clock %" B_PRIu32 " (was %" B_PRIu32 ")\n", 835 __func__, pll->pixelClock, mode->timing.pixel_clock); 836 837 status_t result = atom_execute_table(gAtomContext, index, (uint32*)&args); 838 839 display_crtc_ss(pll, ATOM_ENABLE); 840 841 return result; 842 } 843 844 845 status_t 846 pll_external_set(uint32 clock) 847 { 848 TRACE("%s: set external pll clock to %" B_PRIu32 "\n", __func__, clock); 849 850 if (clock == 0) 851 ERROR("%s: Warning: default display clock is 0?\n", __func__); 852 853 // also known as PLL display engineering 854 uint8 tableMajor; 855 uint8 tableMinor; 856 857 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 858 atom_parse_cmd_header(gAtomContext, index, &tableMajor, &tableMinor); 859 860 TRACE("%s: table %" B_PRIu8 ".%" B_PRIu8 "\n", __func__, 861 tableMajor, tableMinor); 862 863 union setPixelClock { 864 SET_PIXEL_CLOCK_PS_ALLOCATION base; 865 PIXEL_CLOCK_PARAMETERS v1; 866 PIXEL_CLOCK_PARAMETERS_V2 v2; 867 PIXEL_CLOCK_PARAMETERS_V3 v3; 868 PIXEL_CLOCK_PARAMETERS_V5 v5; 869 PIXEL_CLOCK_PARAMETERS_V6 v6; 870 }; 871 union setPixelClock args; 872 memset(&args, 0, sizeof(args)); 873 874 radeon_shared_info &info = *gInfo->shared_info; 875 uint32 dceVersion = (info.dceMajor * 100) + info.dceMinor; 876 switch (tableMajor) { 877 case 1: 878 switch(tableMinor) { 879 case 5: 880 // If the default DC PLL clock is specified, 881 // SetPixelClock provides the dividers. 882 args.v5.ucCRTC = ATOM_CRTC_INVALID; 883 args.v5.usPixelClock = B_HOST_TO_LENDIAN_INT16(clock); 884 args.v5.ucPpll = ATOM_DCPLL; 885 break; 886 case 6: 887 // If the default DC PLL clock is specified, 888 // SetPixelClock provides the dividers. 889 args.v6.ulDispEngClkFreq = B_HOST_TO_LENDIAN_INT32(clock); 890 if (dceVersion == 601) 891 args.v6.ucPpll = ATOM_EXT_PLL1; 892 else if (dceVersion >= 600) 893 args.v6.ucPpll = ATOM_PPLL0; 894 else 895 args.v6.ucPpll = ATOM_DCPLL; 896 break; 897 default: 898 ERROR("%s: Unknown table version %" B_PRIu8 899 ".%" B_PRIu8 "\n", __func__, tableMajor, tableMinor); 900 } 901 break; 902 default: 903 ERROR("%s: Unknown table version %" B_PRIu8 904 ".%" B_PRIu8 "\n", __func__, tableMajor, tableMinor); 905 } 906 return B_OK; 907 } 908 909 910 void 911 pll_external_init() 912 { 913 radeon_shared_info &info = *gInfo->shared_info; 914 915 if (info.dceMajor >= 6) { 916 pll_external_set(gInfo->displayClockFrequency); 917 } else if (info.dceMajor >= 4) { 918 // Create our own pseudo pll 919 pll_info pll; 920 bool ssPresent = pll_asic_ss_probe(&pll, ASIC_INTERNAL_SS_ON_DCPLL) 921 == B_OK ? true : false; 922 if (ssPresent) 923 display_crtc_ss(&pll, ATOM_DISABLE); 924 pll_external_set(gInfo->displayClockFrequency); 925 if (ssPresent) 926 display_crtc_ss(&pll, ATOM_ENABLE); 927 } 928 } 929 930 931 status_t 932 pll_pick(uint32 connectorIndex) 933 { 934 pll_info* pll = &gConnector[connectorIndex]->encoder.pll; 935 radeon_shared_info &info = *gInfo->shared_info; 936 937 bool linkB = gConnector[connectorIndex]->encoder.linkEnumeration 938 == GRAPH_OBJECT_ENUM_ID2 ? true : false; 939 940 if (info.dceMajor == 6 && info.dceMinor == 1) { 941 // DCE 6.1 APU 942 if (gConnector[connectorIndex]->encoder.objectID 943 == ENCODER_OBJECT_ID_INTERNAL_UNIPHY && !linkB) { 944 pll->id = ATOM_PPLL2; 945 return B_OK; 946 } 947 // TODO: check for used PLL1 and use PLL2? 948 pll->id = ATOM_PPLL1; 949 return B_OK; 950 } else if (info.dceMajor >= 4) { 951 if (connector_is_dp(connectorIndex)) { 952 if (gInfo->dpExternalClock) { 953 pll->id = ATOM_PPLL_INVALID; 954 return B_OK; 955 } else if (info.dceMajor >= 6) { 956 pll->id = ATOM_PPLL1; 957 return B_OK; 958 } else if (info.dceMajor >= 5) { 959 pll->id = ATOM_DCPLL; 960 return B_OK; 961 } 962 } 963 pll->id = ATOM_PPLL1; 964 return B_OK; 965 } 966 967 // TODO: Should return the CRTCID here. 968 pll->id = ATOM_PPLL1; 969 return B_OK; 970 } 971