1 /* 2 * Copyright 2006-2011, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Alexander von Gluck, kallisti5@unixzen.com 7 */ 8 #ifndef RADEON_HD_GPU_H 9 #define RADEON_HD_GPU_H 10 11 12 #include "accelerant.h" 13 14 #include <video_configuration.h> 15 16 17 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 18 #define HDP_NONSURFACE_BASE 0x2C04 19 #define HDP_NONSURFACE_INFO 0x2C08 20 #define HDP_NONSURFACE_SIZE 0x2C0C 21 22 23 // GPU Control registers. These are combined as 24 // the registers exist on all models, some flags 25 // are different though and are commented as such 26 #define CP_ME_CNTL 0x86D8 27 #define CP_ME_HALT (1 << 28) 28 #define CP_PFP_HALT (1 << 26) 29 #define CP_ME_RAM_DATA 0xC160 30 #define CP_ME_RAM_RADDR 0xC158 31 #define CP_ME_RAM_WADDR 0xC15C 32 #define CP_MEQ_THRESHOLDS 0x8764 33 #define STQ_SPLIT(x) ((x) << 0) 34 #define CP_PERFMON_CNTL 0x87FC 35 #define CP_PFP_UCODE_ADDR 0xC150 36 #define CP_PFP_UCODE_DATA 0xC154 37 #define CP_QUEUE_THRESHOLDS 0x8760 38 #define ROQ_IB1_START(x) ((x) << 0) 39 #define ROQ_IB2_START(x) ((x) << 8) 40 #define CP_RB_BASE 0xC100 41 #define CP_RB_CNTL 0xC104 42 #define RB_BUFSZ(x) ((x) << 0) 43 #define RB_BLKSZ(x) ((x) << 8) 44 #define RB_NO_UPDATE (1 << 27) 45 #define RB_RPTR_WR_ENA (1 << 31) 46 #define BUF_SWAP_32BIT (2 << 16) 47 #define CP_RB_RPTR 0x8700 48 #define CP_RB_RPTR_ADDR 0xC10C 49 #define RB_RPTR_SWAP(x) ((x) << 0) 50 #define CP_RB_RPTR_ADDR_HI 0xC110 51 #define CP_RB_RPTR_WR 0xC108 52 #define CP_RB_WPTR 0xC114 53 #define CP_RB_WPTR_ADDR 0xC118 54 #define CP_RB_WPTR_ADDR_HI 0xC11C 55 #define CP_RB_WPTR_DELAY 0x8704 56 #define CP_SEM_WAIT_TIMER 0x85BC 57 #define CP_DEBUG 0xC1FC 58 59 #define NI_GRBM_CNTL 0x8000 60 #define GRBM_READ_TIMEOUT(x) ((x) << 0) 61 #define GRBM_STATUS 0x8010 62 #define CMDFIFO_AVAIL_MASK 0x0000000F 63 #define RING2_RQ_PENDING (1 << 4) 64 #define SRBM_RQ_PENDING (1 << 5) 65 #define RING1_RQ_PENDING (1 << 6) 66 #define CF_RQ_PENDING (1 << 7) 67 #define PF_RQ_PENDING (1 << 8) 68 #define GDS_DMA_RQ_PENDING (1 << 9) 69 #define GRBM_EE_BUSY (1 << 10) 70 #define SX_CLEAN (1 << 11) // ni 71 #define VC_BUSY (1 << 11) // r600 72 #define DB_CLEAN (1 << 12) 73 #define CB_CLEAN (1 << 13) 74 #define TA_BUSY (1 << 14) 75 #define GDS_BUSY (1 << 15) 76 #define VGT_BUSY_NO_DMA (1 << 16) 77 #define VGT_BUSY (1 << 17) 78 #define IA_BUSY_NO_DMA (1 << 18) // ni 79 #define TA03_BUSY (1 << 18) // r600 80 #define IA_BUSY (1 << 19) // ni 81 #define TC_BUSY (1 << 19) // r600 82 #define SX_BUSY (1 << 20) 83 #define SH_BUSY (1 << 21) 84 #define SPI_BUSY (1 << 22) // AKA SPI03_BUSY r600 85 #define SMX_BUSY (1 << 23) 86 #define SC_BUSY (1 << 24) 87 #define PA_BUSY (1 << 25) 88 #define DB_BUSY (1 << 26) // AKA DB03_BUSY r600 89 #define CR_BUSY (1 << 27) 90 #define CP_COHERENCY_BUSY (1 << 28) 91 #define CP_BUSY (1 << 29) 92 #define CB_BUSY (1 << 30) 93 #define GUI_ACTIVE (1 << 31) 94 #define GRBM_STATUS2 0x8014 // AKA GRBM_STATUS_SE0 ON NI 95 #define CR_CLEAN (1 << 0) 96 #define SMX_CLEAN (1 << 1) 97 #define SPI0_BUSY (1 << 8) 98 #define SPI1_BUSY (1 << 9) 99 #define SPI2_BUSY (1 << 10) 100 #define SPI3_BUSY (1 << 11) 101 #define TA0_BUSY (1 << 12) 102 #define TA1_BUSY (1 << 13) 103 #define TA2_BUSY (1 << 14) 104 #define TA3_BUSY (1 << 15) 105 #define DB0_BUSY (1 << 16) 106 #define DB1_BUSY (1 << 17) 107 #define DB2_BUSY (1 << 18) 108 #define DB3_BUSY (1 << 19) 109 #define CB0_BUSY (1 << 20) 110 #define CB1_BUSY (1 << 21) 111 #define CB2_BUSY (1 << 22) 112 #define CB3_BUSY (1 << 23) 113 #define NI_GRBM_STATUS_SE1 0x8018 114 #define SE_SX_CLEAN (1 << 0) 115 #define SE_DB_CLEAN (1 << 1) 116 #define SE_CB_CLEAN (1 << 2) 117 #define SE_VGT_BUSY (1 << 23) 118 #define SE_PA_BUSY (1 << 24) 119 #define SE_TA_BUSY (1 << 25) 120 #define SE_SX_BUSY (1 << 26) 121 #define SE_SPI_BUSY (1 << 27) 122 #define SE_SH_BUSY (1 << 28) 123 #define SE_SC_BUSY (1 << 29) 124 #define SE_DB_BUSY (1 << 30) 125 #define SE_CB_BUSY (1 << 31) 126 #define GRBM_SOFT_RESET 0x8020 127 #define SRBM_STATUS 0x0E50 128 #define RLC_RQ_PENDING (1 << 3) 129 #define RCU_RQ_PENDING (1 << 4) 130 #define GRBM_RQ_PENDING (1 << 5) 131 #define HI_RQ_PENDING (1 << 6) 132 #define IO_EXTERN_SIGNAL (1 << 7) 133 #define VMC_BUSY (1 << 8) 134 #define MCB_BUSY (1 << 9) 135 #define MCDZ_BUSY (1 << 10) 136 #define MCDY_BUSY (1 << 11) 137 #define MCDX_BUSY (1 << 12) 138 #define MCDW_BUSY (1 << 13) 139 #define SEM_BUSY (1 << 14) 140 #define SRBM_STATUS__RLC_BUSY (1 << 15) 141 #define PDMA_BUSY (1 << 16) 142 #define IH_BUSY (1 << 17) 143 #define CSC_BUSY (1 << 20) 144 #define CMC7_BUSY (1 << 21) 145 #define CMC6_BUSY (1 << 22) 146 #define CMC5_BUSY (1 << 23) 147 #define CMC4_BUSY (1 << 24) 148 #define CMC3_BUSY (1 << 25) 149 #define CMC2_BUSY (1 << 26) 150 #define CMC1_BUSY (1 << 27) 151 #define CMC0_BUSY (1 << 28) 152 #define BIF_BUSY (1 << 29) 153 #define IDCT_BUSY (1 << 30) 154 #define SRBM_SOFT_RESET 0x0E60 155 #define SOFT_RESET_CP (1 << 0) 156 #define SOFT_RESET_CB (1 << 1) 157 #define SOFT_RESET_CR (1 << 2) 158 #define SOFT_RESET_DB (1 << 3) 159 #define SOFT_RESET_GDS (1 << 4) 160 #define SOFT_RESET_PA (1 << 5) 161 #define SOFT_RESET_SC (1 << 6) 162 #define SOFT_RESET_SMX (1 << 7) 163 #define SOFT_RESET_SPI (1 << 8) 164 #define SOFT_RESET_SH (1 << 9) 165 #define SOFT_RESET_SX (1 << 10) 166 #define SOFT_RESET_TC (1 << 11) 167 #define SOFT_RESET_TA (1 << 12) 168 #define SOFT_RESET_VC (1 << 13) 169 #define SOFT_RESET_VGT (1 << 14) 170 #define SOFT_RESET_IA (1 << 15) 171 172 173 status_t radeon_gpu_reset(); 174 void radeon_gpu_mc_halt(struct gpu_state *gpuState); 175 void radeon_gpu_mc_resume(struct gpu_state *gpuState); 176 status_t radeon_gpu_mc_idlewait(); 177 status_t radeon_gpu_mc_setup(); 178 status_t radeon_gpu_irq_setup(); 179 status_t radeon_gpu_ss_disable(); 180 181 182 #endif 183