1 /* 2 * Copyright 2006-2011, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Alexander von Gluck, kallisti5@unixzen.com 7 */ 8 9 /* 10 * It's dangerous to go alone, take this! 11 * framebuffer -> crtc -> encoder -> transmitter -> connector -> monitor 12 */ 13 14 15 #include "display.h" 16 17 #include <stdlib.h> 18 #include <string.h> 19 20 #include "accelerant.h" 21 #include "accelerant_protos.h" 22 #include "bios.h" 23 #include "connector.h" 24 #include "encoder.h" 25 26 27 #define TRACE_DISPLAY 28 #ifdef TRACE_DISPLAY 29 extern "C" void _sPrintf(const char* format, ...); 30 # define TRACE(x...) _sPrintf("radeon_hd: " x) 31 #else 32 # define TRACE(x...) ; 33 #endif 34 35 #define ERROR(x...) _sPrintf("radeon_hd: " x) 36 37 38 /*! Populate regs with device dependant register locations */ 39 status_t 40 init_registers(register_info* regs, uint8 crtcID) 41 { 42 memset(regs, 0, sizeof(register_info)); 43 44 radeon_shared_info &info = *gInfo->shared_info; 45 46 if (info.chipsetID >= RADEON_CEDAR) { 47 // Evergreen 48 uint32 offset = 0; 49 50 switch (crtcID) { 51 case 0: 52 offset = EVERGREEN_CRTC0_REGISTER_OFFSET; 53 regs->vgaControl = AVIVO_D1VGA_CONTROL; 54 break; 55 case 1: 56 offset = EVERGREEN_CRTC1_REGISTER_OFFSET; 57 regs->vgaControl = AVIVO_D2VGA_CONTROL; 58 break; 59 case 2: 60 offset = EVERGREEN_CRTC2_REGISTER_OFFSET; 61 regs->vgaControl = EVERGREEN_D3VGA_CONTROL; 62 break; 63 case 3: 64 offset = EVERGREEN_CRTC3_REGISTER_OFFSET; 65 regs->vgaControl = EVERGREEN_D4VGA_CONTROL; 66 break; 67 case 4: 68 offset = EVERGREEN_CRTC4_REGISTER_OFFSET; 69 regs->vgaControl = EVERGREEN_D5VGA_CONTROL; 70 break; 71 case 5: 72 offset = EVERGREEN_CRTC5_REGISTER_OFFSET; 73 regs->vgaControl = EVERGREEN_D6VGA_CONTROL; 74 break; 75 default: 76 ERROR("%s: Unknown CRTC %" B_PRIu32 "\n", 77 __func__, crtcID); 78 return B_ERROR; 79 } 80 81 regs->crtcOffset = offset; 82 83 regs->grphEnable = EVERGREEN_GRPH_ENABLE + offset; 84 regs->grphControl = EVERGREEN_GRPH_CONTROL + offset; 85 regs->grphSwapControl = EVERGREEN_GRPH_SWAP_CONTROL + offset; 86 87 regs->grphPrimarySurfaceAddr 88 = EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + offset; 89 regs->grphSecondarySurfaceAddr 90 = EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + offset; 91 regs->grphPrimarySurfaceAddrHigh 92 = EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + offset; 93 regs->grphSecondarySurfaceAddrHigh 94 = EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + offset; 95 96 regs->grphPitch = EVERGREEN_GRPH_PITCH + offset; 97 regs->grphSurfaceOffsetX 98 = EVERGREEN_GRPH_SURFACE_OFFSET_X + offset; 99 regs->grphSurfaceOffsetY 100 = EVERGREEN_GRPH_SURFACE_OFFSET_Y + offset; 101 regs->grphXStart = EVERGREEN_GRPH_X_START + offset; 102 regs->grphYStart = EVERGREEN_GRPH_Y_START + offset; 103 regs->grphXEnd = EVERGREEN_GRPH_X_END + offset; 104 regs->grphYEnd = EVERGREEN_GRPH_Y_END + offset; 105 regs->modeDesktopHeight = EVERGREEN_DESKTOP_HEIGHT + offset; 106 regs->modeDataFormat = EVERGREEN_DATA_FORMAT + offset; 107 regs->viewportStart = EVERGREEN_VIEWPORT_START + offset; 108 regs->viewportSize = EVERGREEN_VIEWPORT_SIZE + offset; 109 110 } else if (info.chipsetID >= RADEON_RV770) { 111 // R700 series 112 uint32 offset = 0; 113 114 switch (crtcID) { 115 case 0: 116 offset = R600_CRTC0_REGISTER_OFFSET; 117 regs->vgaControl = AVIVO_D1VGA_CONTROL; 118 regs->grphPrimarySurfaceAddrHigh 119 = D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH; 120 break; 121 case 1: 122 offset = R600_CRTC1_REGISTER_OFFSET; 123 regs->vgaControl = AVIVO_D2VGA_CONTROL; 124 regs->grphPrimarySurfaceAddrHigh 125 = D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH; 126 break; 127 default: 128 ERROR("%s: Unknown CRTC %" B_PRIu32 "\n", 129 __func__, crtcID); 130 return B_ERROR; 131 } 132 133 regs->crtcOffset = offset; 134 135 regs->grphEnable = AVIVO_D1GRPH_ENABLE + offset; 136 regs->grphControl = AVIVO_D1GRPH_CONTROL + offset; 137 regs->grphSwapControl = D1GRPH_SWAP_CNTL + offset; 138 139 regs->grphPrimarySurfaceAddr 140 = D1GRPH_PRIMARY_SURFACE_ADDRESS + offset; 141 regs->grphSecondarySurfaceAddr 142 = D1GRPH_SECONDARY_SURFACE_ADDRESS + offset; 143 144 regs->grphPitch = AVIVO_D1GRPH_PITCH + offset; 145 regs->grphSurfaceOffsetX = AVIVO_D1GRPH_SURFACE_OFFSET_X + offset; 146 regs->grphSurfaceOffsetY = AVIVO_D1GRPH_SURFACE_OFFSET_Y + offset; 147 regs->grphXStart = AVIVO_D1GRPH_X_START + offset; 148 regs->grphYStart = AVIVO_D1GRPH_Y_START + offset; 149 regs->grphXEnd = AVIVO_D1GRPH_X_END + offset; 150 regs->grphYEnd = AVIVO_D1GRPH_Y_END + offset; 151 152 regs->modeDesktopHeight = AVIVO_D1MODE_DESKTOP_HEIGHT + offset; 153 regs->modeDataFormat = AVIVO_D1MODE_DATA_FORMAT + offset; 154 regs->viewportStart = AVIVO_D1MODE_VIEWPORT_START + offset; 155 regs->viewportSize = AVIVO_D1MODE_VIEWPORT_SIZE + offset; 156 157 } else if (info.chipsetID >= RADEON_RS600) { 158 // Avivo+ 159 uint32 offset = 0; 160 161 switch (crtcID) { 162 case 0: 163 offset = R600_CRTC0_REGISTER_OFFSET; 164 regs->vgaControl = AVIVO_D1VGA_CONTROL; 165 break; 166 case 1: 167 offset = R600_CRTC1_REGISTER_OFFSET; 168 regs->vgaControl = AVIVO_D2VGA_CONTROL; 169 break; 170 default: 171 ERROR("%s: Unknown CRTC %" B_PRIu32 "\n", 172 __func__, crtcID); 173 return B_ERROR; 174 } 175 176 regs->crtcOffset = offset; 177 178 regs->grphEnable = AVIVO_D1GRPH_ENABLE + offset; 179 regs->grphControl = AVIVO_D1GRPH_CONTROL + offset; 180 regs->grphSwapControl = D1GRPH_SWAP_CNTL + offset; 181 182 regs->grphPrimarySurfaceAddr 183 = D1GRPH_PRIMARY_SURFACE_ADDRESS + offset; 184 regs->grphSecondarySurfaceAddr 185 = D1GRPH_SECONDARY_SURFACE_ADDRESS + offset; 186 187 // Surface Address high only used on r700 and higher 188 regs->grphPrimarySurfaceAddrHigh = 0xDEAD; 189 regs->grphSecondarySurfaceAddrHigh = 0xDEAD; 190 191 regs->grphPitch = AVIVO_D1GRPH_PITCH + offset; 192 regs->grphSurfaceOffsetX = AVIVO_D1GRPH_SURFACE_OFFSET_X + offset; 193 regs->grphSurfaceOffsetY = AVIVO_D1GRPH_SURFACE_OFFSET_Y + offset; 194 regs->grphXStart = AVIVO_D1GRPH_X_START + offset; 195 regs->grphYStart = AVIVO_D1GRPH_Y_START + offset; 196 regs->grphXEnd = AVIVO_D1GRPH_X_END + offset; 197 regs->grphYEnd = AVIVO_D1GRPH_Y_END + offset; 198 199 regs->modeDesktopHeight = AVIVO_D1MODE_DESKTOP_HEIGHT + offset; 200 regs->modeDataFormat = AVIVO_D1MODE_DATA_FORMAT + offset; 201 regs->viewportStart = AVIVO_D1MODE_VIEWPORT_START + offset; 202 regs->viewportSize = AVIVO_D1MODE_VIEWPORT_SIZE + offset; 203 } else { 204 // this really shouldn't happen unless a driver PCIID chipset is wrong 205 TRACE("%s, unknown Radeon chipset: %s\n", __func__, 206 info.chipsetName); 207 return B_ERROR; 208 } 209 210 TRACE("%s, registers for ATI chipset %s crt #%d loaded\n", __func__, 211 info.chipsetName, crtcID); 212 213 return B_OK; 214 } 215 216 217 status_t 218 detect_crt_ranges(uint32 crtid) 219 { 220 edid1_info* edid = &gDisplay[crtid]->edidData; 221 222 // Scan each display EDID description for monitor ranges 223 for (uint32 index = 0; index < EDID1_NUM_DETAILED_MONITOR_DESC; index++) { 224 225 edid1_detailed_monitor* monitor 226 = &edid->detailed_monitor[index]; 227 228 if (monitor->monitor_desc_type 229 == EDID1_MONITOR_RANGES) { 230 edid1_monitor_range range = monitor->data.monitor_range; 231 gDisplay[crtid]->vfreqMin = range.min_v; /* in Hz */ 232 gDisplay[crtid]->vfreqMax = range.max_v; 233 gDisplay[crtid]->hfreqMin = range.min_h; /* in kHz */ 234 gDisplay[crtid]->hfreqMax = range.max_h; 235 return B_OK; 236 } 237 } 238 239 return B_ERROR; 240 } 241 242 243 status_t 244 detect_displays() 245 { 246 // reset known displays 247 for (uint32 id = 0; id < MAX_DISPLAY; id++) { 248 gDisplay[id]->attached = false; 249 gDisplay[id]->powered = false; 250 gDisplay[id]->foundRanges = false; 251 } 252 253 uint32 displayIndex = 0; 254 for (uint32 id = 0; id < ATOM_MAX_SUPPORTED_DEVICE; id++) { 255 if (gConnector[id]->valid == false) 256 continue; 257 if (displayIndex >= MAX_DISPLAY) 258 continue; 259 260 // TODO: As DP aux transactions don't work yet, just use LVDS as a hack 261 #if 0 262 if (gConnector[id]->encoderExternal.isDPBridge == true) { 263 // If this is a DisplayPort Bridge, setup ddc on bus 264 // TRAVIS (LVDS) or NUTMEG (VGA) 265 TRACE("%s: is bridge, performing bridge DDC setup\n", __func__); 266 encoder_external_setup(id, 23860, 267 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP); 268 gDisplay[displayIndex]->attached = true; 269 } else if (gConnector[id]->type == VIDEO_CONNECTOR_LVDS) { 270 #endif 271 if (gConnector[id]->type == VIDEO_CONNECTOR_LVDS) { 272 // If plain (non-DP) laptop LVDS, read mode info from AtomBIOS 273 //TRACE("%s: non-DP laptop LVDS detected\n", __func__); 274 gDisplay[displayIndex]->attached 275 = connector_read_mode_lvds(id, 276 &gDisplay[displayIndex]->preferredMode); 277 } 278 279 // If no display found yet, try more standard detection methods 280 if (gDisplay[displayIndex]->attached == false) { 281 TRACE("%s: bit-banging ddc for EDID on connector %" B_PRIu32 "\n", 282 __func__, id); 283 284 // Lets try bit-banging edid from connector 285 gDisplay[displayIndex]->attached 286 = connector_read_edid(id, &gDisplay[displayIndex]->edidData); 287 288 // Since DVI-I shows up as two connectors, and there is only one 289 // edid channel, we have to make *sure* the edid data received is 290 // valid for te connector. 291 292 // Found EDID data? 293 if (gDisplay[displayIndex]->attached) { 294 TRACE("%s: found EDID data on connector %" B_PRIu32 "\n", 295 __func__, id); 296 297 bool analogEncoder 298 = gConnector[id]->encoder.type == VIDEO_ENCODER_TVDAC 299 || gConnector[id]->encoder.type == VIDEO_ENCODER_DAC; 300 301 edid1_info* edid = &gDisplay[displayIndex]->edidData; 302 if (!edid->display.input_type && analogEncoder) { 303 // If non-digital EDID + the encoder is analog... 304 TRACE("%s: connector %" B_PRIu32 " has non-digital EDID " 305 "and a analog encoder.\n", __func__, id); 306 gDisplay[displayIndex]->attached 307 = encoder_analog_load_detect(id); 308 } else if (edid->display.input_type && !analogEncoder) { 309 // If EDID is digital, we make an assumption here. 310 TRACE("%s: connector %" B_PRIu32 " has digital EDID " 311 "and is not a analog encoder.\n", __func__, id); 312 } else { 313 // ???, shouldn't happen... I think. 314 TRACE("%s: Warning: connector %" B_PRIu32 " has neither " 315 "digital EDID nor is an analog encoder?\n", 316 __func__, id); 317 } 318 } 319 } 320 321 if (gDisplay[displayIndex]->attached != true) { 322 // Nothing interesting here, move along 323 continue; 324 } 325 326 // We found a valid / attached display 327 328 gDisplay[displayIndex]->connectorIndex = id; 329 // Populate physical connector index from gConnector 330 331 init_registers(gDisplay[displayIndex]->regs, displayIndex); 332 333 if (gDisplay[displayIndex]->preferredMode.virtual_width > 0) { 334 // Found a single preferred mode 335 gDisplay[displayIndex]->foundRanges = false; 336 } else { 337 // Use edid data and pull ranges 338 if (detect_crt_ranges(displayIndex) == B_OK) 339 gDisplay[displayIndex]->foundRanges = true; 340 } 341 342 displayIndex++; 343 } 344 345 // fallback if no attached monitors were found 346 if (displayIndex == 0) { 347 // This is a hack, however as we don't support HPD just yet, 348 // it tries to prevent a "no displays" situation. 349 ERROR("%s: ERROR: 0 attached monitors were found on display connectors." 350 " Injecting first connector as a last resort.\n", __func__); 351 for (uint32 id = 0; id < ATOM_MAX_SUPPORTED_DEVICE; id++) { 352 // skip TV DAC connectors as likely fallback isn't for TV 353 if (gConnector[id]->encoder.type == VIDEO_ENCODER_TVDAC) 354 continue; 355 gDisplay[0]->attached = true; 356 gDisplay[0]->connectorIndex = id; 357 init_registers(gDisplay[0]->regs, 0); 358 if (detect_crt_ranges(0) == B_OK) 359 gDisplay[0]->foundRanges = true; 360 break; 361 } 362 } 363 364 // Initial boot state is the first two crtc's powered 365 if (gDisplay[0]->attached == true) 366 gDisplay[0]->powered = true; 367 if (gDisplay[1]->attached == true) 368 gDisplay[1]->powered = true; 369 370 return B_OK; 371 } 372 373 374 void 375 debug_displays() 376 { 377 TRACE("Currently detected monitors===============\n"); 378 for (uint32 id = 0; id < MAX_DISPLAY; id++) { 379 ERROR("Display #%" B_PRIu32 " attached = %s\n", 380 id, gDisplay[id]->attached ? "true" : "false"); 381 382 uint32 connectorIndex = gDisplay[id]->connectorIndex; 383 384 if (gDisplay[id]->attached) { 385 uint32 connectorType = gConnector[connectorIndex]->type; 386 uint32 encoderType = gConnector[connectorIndex]->encoder.type; 387 ERROR(" + connector ID: %" B_PRIu32 "\n", connectorIndex); 388 ERROR(" + connector type: %s\n", get_connector_name(connectorType)); 389 ERROR(" + encoder type: %s\n", get_encoder_name(encoderType)); 390 ERROR(" + limits: Vert Min/Max: %" B_PRIu32 "/%" B_PRIu32"\n", 391 gDisplay[id]->vfreqMin, gDisplay[id]->vfreqMax); 392 ERROR(" + limits: Horz Min/Max: %" B_PRIu32 "/%" B_PRIu32"\n", 393 gDisplay[id]->hfreqMin, gDisplay[id]->hfreqMax); 394 } 395 } 396 TRACE("==========================================\n"); 397 } 398 399 400 uint32 401 display_get_encoder_mode(uint32 connectorIndex) 402 { 403 // Is external DisplayPort Bridge? 404 if (gConnector[connectorIndex]->encoderExternal.valid == true 405 && gConnector[connectorIndex]->encoderExternal.isDPBridge == true) { 406 return ATOM_ENCODER_MODE_DP; 407 } 408 409 // DVO Encoders (should be bridges) 410 switch (gConnector[connectorIndex]->encoder.objectID) { 411 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 412 case ENCODER_OBJECT_ID_INTERNAL_DDI: 413 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 414 return ATOM_ENCODER_MODE_DVO; 415 } 416 417 // Find crtc for connector so we can identify source of edid data 418 int32 crtc = -1; 419 for (int32 id = 0; id < MAX_DISPLAY; id++) { 420 if (gDisplay[id]->connectorIndex == connectorIndex) { 421 crtc = id; 422 break; 423 } 424 } 425 bool edidDigital = false; 426 if (crtc == -1) { 427 ERROR("%s: BUG: executed on connector without crtc!\n", __func__); 428 } else { 429 edid1_info* edid = &gDisplay[crtc]->edidData; 430 edidDigital = edid->display.input_type ? true : false; 431 } 432 433 // Normal encoder situations 434 switch (gConnector[connectorIndex]->type) { 435 case VIDEO_CONNECTOR_DVII: 436 case VIDEO_CONNECTOR_HDMIB: /* HDMI-B is DL-DVI; analog works fine */ 437 // TODO: if audio detected on edid and DCE4, ATOM_ENCODER_MODE_DVI 438 // if audio detected on edid not DCE4, ATOM_ENCODER_MODE_HDMI 439 if (edidDigital) 440 return ATOM_ENCODER_MODE_DVI; 441 else 442 return ATOM_ENCODER_MODE_CRT; 443 break; 444 case VIDEO_CONNECTOR_DVID: 445 case VIDEO_CONNECTOR_HDMIA: 446 default: 447 // TODO: if audio detected on edid and DCE4, ATOM_ENCODER_MODE_DVI 448 // if audio detected on edid not DCE4, ATOM_ENCODER_MODE_HDMI 449 return ATOM_ENCODER_MODE_DVI; 450 case VIDEO_CONNECTOR_LVDS: 451 return ATOM_ENCODER_MODE_LVDS; 452 case VIDEO_CONNECTOR_DP: 453 // dig_connector = radeon_connector->con_priv; 454 // if ((dig_connector->dp_sink_type 455 // == CONNECTOR_OBJECT_ID_DISPLAYPORT) 456 // || (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 457 // return ATOM_ENCODER_MODE_DP; 458 // } 459 // TODO: if audio detected on edid and DCE4, ATOM_ENCODER_MODE_DVI 460 // if audio detected on edid not DCE4, ATOM_ENCODER_MODE_HDMI 461 return ATOM_ENCODER_MODE_DP; 462 case VIDEO_CONNECTOR_EDP: 463 return ATOM_ENCODER_MODE_DP; 464 case VIDEO_CONNECTOR_DVIA: 465 case VIDEO_CONNECTOR_VGA: 466 return ATOM_ENCODER_MODE_CRT; 467 case VIDEO_CONNECTOR_COMPOSITE: 468 case VIDEO_CONNECTOR_SVIDEO: 469 case VIDEO_CONNECTOR_9DIN: 470 return ATOM_ENCODER_MODE_TV; 471 } 472 } 473 474 475 void 476 display_crtc_lock(uint8 crtcID, int command) 477 { 478 TRACE("%s\n", __func__); 479 480 ENABLE_CRTC_PS_ALLOCATION args; 481 int index 482 = GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); 483 484 memset(&args, 0, sizeof(args)); 485 486 args.ucCRTC = crtcID; 487 args.ucEnable = command; 488 489 atom_execute_table(gAtomContext, index, (uint32*)&args); 490 } 491 492 493 void 494 display_crtc_blank(uint8 crtcID, int command) 495 { 496 TRACE("%s\n", __func__); 497 498 BLANK_CRTC_PS_ALLOCATION args; 499 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); 500 501 memset(&args, 0, sizeof(args)); 502 503 args.ucCRTC = crtcID; 504 args.ucBlanking = command; 505 506 args.usBlackColorRCr = 0; 507 args.usBlackColorGY = 0; 508 args.usBlackColorBCb = 0; 509 510 atom_execute_table(gAtomContext, index, (uint32*)&args); 511 } 512 513 514 void 515 display_crtc_scale(uint8 crtcID, display_mode* mode) 516 { 517 TRACE("%s\n", __func__); 518 ENABLE_SCALER_PS_ALLOCATION args; 519 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); 520 521 memset(&args, 0, sizeof(args)); 522 523 args.ucScaler = crtcID; 524 args.ucEnable = ATOM_SCALER_DISABLE; 525 526 atom_execute_table(gAtomContext, index, (uint32*)&args); 527 } 528 529 530 void 531 display_crtc_dpms(uint8 crtcID, int mode) 532 { 533 534 radeon_shared_info &info = *gInfo->shared_info; 535 536 switch (mode) { 537 case B_DPMS_ON: 538 TRACE("%s: crtc %" B_PRIu8 " dpms powerup\n", __func__, crtcID); 539 if (gDisplay[crtcID]->attached == false) 540 return; 541 gDisplay[crtcID]->powered = true; 542 display_crtc_power(crtcID, ATOM_ENABLE); 543 if (info.dceMajor >= 3) 544 display_crtc_memreq(crtcID, ATOM_ENABLE); 545 display_crtc_blank(crtcID, ATOM_BLANKING_OFF); 546 break; 547 case B_DPMS_STAND_BY: 548 case B_DPMS_SUSPEND: 549 case B_DPMS_OFF: 550 TRACE("%s: crtc %" B_PRIu8 " dpms powerdown\n", __func__, crtcID); 551 if (gDisplay[crtcID]->attached == false) 552 return; 553 if (gDisplay[crtcID]->powered == true) 554 display_crtc_blank(crtcID, ATOM_BLANKING); 555 if (info.dceMajor >= 3) 556 display_crtc_memreq(crtcID, ATOM_DISABLE); 557 display_crtc_power(crtcID, ATOM_DISABLE); 558 gDisplay[crtcID]->powered = false; 559 } 560 } 561 562 563 void 564 display_crtc_fb_set(uint8 crtcID, display_mode* mode) 565 { 566 radeon_shared_info &info = *gInfo->shared_info; 567 register_info* regs = gDisplay[crtcID]->regs; 568 569 uint32 fbSwap; 570 if (info.dceMajor >= 4) 571 fbSwap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); 572 else 573 fbSwap = R600_D1GRPH_SWAP_ENDIAN_NONE; 574 575 uint32 fbFormat; 576 577 uint32 bytesPerPixel; 578 uint32 bitsPerPixel; 579 580 switch (mode->space) { 581 case B_CMAP8: 582 bytesPerPixel = 1; 583 bitsPerPixel = 8; 584 if (info.dceMajor >= 4) { 585 fbFormat = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) 586 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); 587 } else { 588 fbFormat = AVIVO_D1GRPH_CONTROL_DEPTH_8BPP 589 | AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; 590 } 591 break; 592 case B_RGB15_LITTLE: 593 bytesPerPixel = 2; 594 bitsPerPixel = 15; 595 if (info.dceMajor >= 4) { 596 fbFormat = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) 597 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); 598 } else { 599 fbFormat = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP 600 | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; 601 } 602 break; 603 case B_RGB16_LITTLE: 604 bytesPerPixel = 2; 605 bitsPerPixel = 16; 606 607 if (info.dceMajor >= 4) { 608 fbFormat = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) 609 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); 610 #ifdef __POWERPC__ 611 fbSwap 612 = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 613 #endif 614 } else { 615 fbFormat = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP 616 | AVIVO_D1GRPH_CONTROL_16BPP_RGB565; 617 #ifdef __POWERPC__ 618 fbSwap = R600_D1GRPH_SWAP_ENDIAN_16BIT; 619 #endif 620 } 621 break; 622 case B_RGB24_LITTLE: 623 case B_RGB32_LITTLE: 624 default: 625 bytesPerPixel = 4; 626 bitsPerPixel = 32; 627 if (info.dceMajor >= 4) { 628 fbFormat = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) 629 | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); 630 #ifdef __POWERPC__ 631 fbSwap 632 = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 633 #endif 634 } else { 635 fbFormat = AVIVO_D1GRPH_CONTROL_DEPTH_32BPP 636 | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; 637 #ifdef __POWERPC__ 638 fbSwap = R600_D1GRPH_SWAP_ENDIAN_32BIT; 639 #endif 640 } 641 break; 642 } 643 644 Write32(OUT, regs->vgaControl, 0); 645 646 uint64 fbAddress = gInfo->fb.vramStart; 647 648 TRACE("%s: Framebuffer at: 0x%" B_PRIX64 "\n", __func__, fbAddress); 649 650 if (info.chipsetID >= RADEON_RV770) { 651 TRACE("%s: Set SurfaceAddress High: 0x%" B_PRIX32 "\n", 652 __func__, (fbAddress >> 32) & 0xf); 653 654 Write32(OUT, regs->grphPrimarySurfaceAddrHigh, 655 (fbAddress >> 32) & 0xf); 656 Write32(OUT, regs->grphSecondarySurfaceAddrHigh, 657 (fbAddress >> 32) & 0xf); 658 } 659 660 TRACE("%s: Set SurfaceAddress: 0x%" B_PRIX32 "\n", 661 __func__, (fbAddress & 0xFFFFFFFF)); 662 663 Write32(OUT, regs->grphPrimarySurfaceAddr, (fbAddress & 0xFFFFFFFF)); 664 Write32(OUT, regs->grphSecondarySurfaceAddr, (fbAddress & 0xFFFFFFFF)); 665 666 if (info.chipsetID >= RADEON_R600) { 667 Write32(CRT, regs->grphControl, fbFormat); 668 Write32(CRT, regs->grphSwapControl, fbSwap); 669 } 670 671 // Align our framebuffer width 672 uint32 widthAligned = mode->virtual_width; 673 uint32 pitchMask = 0; 674 675 switch (bytesPerPixel) { 676 case 1: 677 pitchMask = 255; 678 break; 679 case 2: 680 pitchMask = 127; 681 break; 682 case 3: 683 case 4: 684 pitchMask = 63; 685 break; 686 } 687 widthAligned += pitchMask; 688 widthAligned &= ~pitchMask; 689 690 TRACE("%s: fb: %" B_PRIu32 "x%" B_PRIu32 " (%" B_PRIu32 " bpp)\n", __func__, 691 mode->virtual_width, mode->virtual_height, bitsPerPixel); 692 TRACE("%s: fb pitch: %" B_PRIu32 " \n", __func__, 693 widthAligned * bytesPerPixel / 4); 694 TRACE("%s: fb width aligned: %" B_PRIu32 "\n", __func__, 695 widthAligned); 696 697 Write32(CRT, regs->grphSurfaceOffsetX, 0); 698 Write32(CRT, regs->grphSurfaceOffsetY, 0); 699 Write32(CRT, regs->grphXStart, 0); 700 Write32(CRT, regs->grphYStart, 0); 701 Write32(CRT, regs->grphXEnd, mode->virtual_width); 702 Write32(CRT, regs->grphYEnd, mode->virtual_height); 703 Write32(CRT, regs->grphPitch, widthAligned * bytesPerPixel / 4); 704 705 Write32(CRT, regs->grphEnable, 1); 706 // Enable Frame buffer 707 708 Write32(CRT, regs->modeDesktopHeight, mode->virtual_height); 709 710 uint32 viewportWidth = mode->timing.h_display; 711 uint32 viewportHeight = (mode->timing.v_display + 1) & ~1; 712 713 Write32(CRT, regs->viewportStart, 0); 714 Write32(CRT, regs->viewportSize, 715 (viewportWidth << 16) | viewportHeight); 716 717 // Pageflip setup 718 if (info.dceMajor >= 4) { 719 uint32 tmp 720 = Read32(OUT, EVERGREEN_GRPH_FLIP_CONTROL + regs->crtcOffset); 721 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN; 722 Write32(OUT, EVERGREEN_GRPH_FLIP_CONTROL + regs->crtcOffset, tmp); 723 724 Write32(OUT, EVERGREEN_MASTER_UPDATE_MODE + regs->crtcOffset, 0); 725 // Pageflip to happen anywhere in vblank 726 727 } else { 728 uint32 tmp = Read32(OUT, AVIVO_D1GRPH_FLIP_CONTROL + regs->crtcOffset); 729 tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN; 730 Write32(OUT, AVIVO_D1GRPH_FLIP_CONTROL + regs->crtcOffset, tmp); 731 732 Write32(OUT, AVIVO_D1MODE_MASTER_UPDATE_MODE + regs->crtcOffset, 0); 733 // Pageflip to happen anywhere in vblank 734 } 735 736 // update shared info 737 gInfo->shared_info->bytes_per_row = widthAligned * bytesPerPixel; 738 gInfo->shared_info->current_mode = *mode; 739 gInfo->shared_info->bits_per_pixel = bitsPerPixel; 740 } 741 742 743 void 744 display_crtc_set(uint8 crtcID, display_mode* mode) 745 { 746 display_timing& displayTiming = mode->timing; 747 748 TRACE("%s called to do %dx%d\n", 749 __func__, displayTiming.h_display, displayTiming.v_display); 750 751 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args; 752 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); 753 uint16 misc = 0; 754 755 memset(&args, 0, sizeof(args)); 756 757 args.usH_Total = B_HOST_TO_LENDIAN_INT16(displayTiming.h_total); 758 args.usH_Disp = B_HOST_TO_LENDIAN_INT16(displayTiming.h_display); 759 args.usH_SyncStart = B_HOST_TO_LENDIAN_INT16(displayTiming.h_sync_start); 760 args.usH_SyncWidth = B_HOST_TO_LENDIAN_INT16(displayTiming.h_sync_end 761 - displayTiming.h_sync_start); 762 763 args.usV_Total = B_HOST_TO_LENDIAN_INT16(displayTiming.v_total); 764 args.usV_Disp = B_HOST_TO_LENDIAN_INT16(displayTiming.v_display); 765 args.usV_SyncStart = B_HOST_TO_LENDIAN_INT16(displayTiming.v_sync_start); 766 args.usV_SyncWidth = B_HOST_TO_LENDIAN_INT16(displayTiming.v_sync_end 767 - displayTiming.v_sync_start); 768 769 args.ucOverscanRight = 0; 770 args.ucOverscanLeft = 0; 771 args.ucOverscanBottom = 0; 772 args.ucOverscanTop = 0; 773 774 if ((displayTiming.flags & B_POSITIVE_HSYNC) == 0) 775 misc |= ATOM_HSYNC_POLARITY; 776 if ((displayTiming.flags & B_POSITIVE_VSYNC) == 0) 777 misc |= ATOM_VSYNC_POLARITY; 778 779 args.susModeMiscInfo.usAccess = B_HOST_TO_LENDIAN_INT16(misc); 780 args.ucCRTC = crtcID; 781 782 atom_execute_table(gAtomContext, index, (uint32*)&args); 783 } 784 785 786 void 787 display_crtc_set_dtd(uint8 crtcID, display_mode* mode) 788 { 789 display_timing& displayTiming = mode->timing; 790 791 TRACE("%s called to do %dx%d\n", 792 __func__, displayTiming.h_display, displayTiming.v_display); 793 794 SET_CRTC_USING_DTD_TIMING_PARAMETERS args; 795 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); 796 uint16 misc = 0; 797 798 memset(&args, 0, sizeof(args)); 799 800 uint16 blankStart 801 = MIN(displayTiming.h_sync_start, displayTiming.h_display); 802 uint16 blankEnd 803 = MAX(displayTiming.h_sync_end, displayTiming.h_total); 804 args.usH_Size = B_HOST_TO_LENDIAN_INT16(displayTiming.h_display); 805 args.usH_Blanking_Time = B_HOST_TO_LENDIAN_INT16(blankEnd - blankStart); 806 807 blankStart = MIN(displayTiming.v_sync_start, displayTiming.v_display); 808 blankEnd = MAX(displayTiming.v_sync_end, displayTiming.v_total); 809 args.usV_Size = B_HOST_TO_LENDIAN_INT16(displayTiming.v_display); 810 args.usV_Blanking_Time = B_HOST_TO_LENDIAN_INT16(blankEnd - blankStart); 811 812 args.usH_SyncOffset = B_HOST_TO_LENDIAN_INT16(displayTiming.h_sync_start 813 - displayTiming.h_display); 814 args.usH_SyncWidth = B_HOST_TO_LENDIAN_INT16(displayTiming.h_sync_end 815 - displayTiming.h_sync_start); 816 817 args.usV_SyncOffset = B_HOST_TO_LENDIAN_INT16(displayTiming.v_sync_start 818 - displayTiming.v_display); 819 args.usV_SyncWidth = B_HOST_TO_LENDIAN_INT16(displayTiming.v_sync_end 820 - displayTiming.v_sync_start); 821 822 args.ucH_Border = 0; 823 args.ucV_Border = 0; 824 825 if ((displayTiming.flags & B_POSITIVE_HSYNC) == 0) 826 misc |= ATOM_HSYNC_POLARITY; 827 if ((displayTiming.flags & B_POSITIVE_VSYNC) == 0) 828 misc |= ATOM_VSYNC_POLARITY; 829 830 args.susModeMiscInfo.usAccess = B_HOST_TO_LENDIAN_INT16(misc); 831 args.ucCRTC = crtcID; 832 833 atom_execute_table(gAtomContext, index, (uint32*)&args); 834 } 835 836 837 void 838 display_crtc_ss(uint8 crtcID, int command) 839 { 840 TRACE("%s\n", __func__); 841 radeon_shared_info &info = *gInfo->shared_info; 842 843 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); 844 845 if (command != ATOM_DISABLE) { 846 ERROR("%s: TODO: SS was enabled, however functionality incomplete\n", 847 __func__); 848 command = ATOM_DISABLE; 849 } 850 851 union enableSS { 852 ENABLE_LVDS_SS_PARAMETERS lvds_ss; 853 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2; 854 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; 855 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2; 856 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; 857 }; 858 859 union enableSS args; 860 memset(&args, 0, sizeof(args)); 861 862 uint32 connectorIndex = gDisplay[crtcID]->connectorIndex; 863 pll_info* pll = &gConnector[connectorIndex]->encoder.pll; 864 865 if (info.dceMajor >= 5) { 866 args.v3.usSpreadSpectrumAmountFrac = B_HOST_TO_LENDIAN_INT16(0); 867 args.v3.ucSpreadSpectrumType 868 = pll->ssType & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 869 switch (pll->id) { 870 case ATOM_PPLL1: 871 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; 872 args.v3.usSpreadSpectrumAmount 873 = B_HOST_TO_LENDIAN_INT16(pll->ssAmount); 874 args.v3.usSpreadSpectrumStep 875 = B_HOST_TO_LENDIAN_INT16(pll->ssStep); 876 break; 877 case ATOM_PPLL2: 878 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; 879 args.v3.usSpreadSpectrumAmount 880 = B_HOST_TO_LENDIAN_INT16(pll->ssAmount); 881 args.v3.usSpreadSpectrumStep 882 = B_HOST_TO_LENDIAN_INT16(pll->ssStep); 883 break; 884 case ATOM_DCPLL: 885 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; 886 args.v3.usSpreadSpectrumAmount = B_HOST_TO_LENDIAN_INT16(0); 887 args.v3.usSpreadSpectrumStep = B_HOST_TO_LENDIAN_INT16(0); 888 break; 889 default: 890 ERROR("%s: BUG: Invalid PLL ID!\n", __func__); 891 return; 892 } 893 if (pll->ssPercentage == 0 894 || ((pll->ssType & ATOM_EXTERNAL_SS_MASK) != 0)) { 895 command = ATOM_DISABLE; 896 } 897 args.v3.ucEnable = command; 898 } else if (info.dceMajor >= 4) { 899 args.v2.usSpreadSpectrumPercentage 900 = B_HOST_TO_LENDIAN_INT16(pll->ssPercentage); 901 args.v2.ucSpreadSpectrumType 902 = pll->ssType & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 903 switch (pll->id) { 904 case ATOM_PPLL1: 905 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL; 906 args.v2.usSpreadSpectrumAmount 907 = B_HOST_TO_LENDIAN_INT16(pll->ssAmount); 908 args.v2.usSpreadSpectrumStep 909 = B_HOST_TO_LENDIAN_INT16(pll->ssStep); 910 break; 911 case ATOM_PPLL2: 912 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; 913 args.v2.usSpreadSpectrumAmount 914 = B_HOST_TO_LENDIAN_INT16(pll->ssAmount); 915 args.v2.usSpreadSpectrumStep 916 = B_HOST_TO_LENDIAN_INT16(pll->ssStep); 917 break; 918 case ATOM_DCPLL: 919 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; 920 args.v2.usSpreadSpectrumAmount = B_HOST_TO_LENDIAN_INT16(0); 921 args.v2.usSpreadSpectrumStep = B_HOST_TO_LENDIAN_INT16(0); 922 break; 923 default: 924 ERROR("%s: BUG: Invalid PLL ID!\n", __func__); 925 return; 926 } 927 if (pll->ssPercentage == 0 928 || ((pll->ssType & ATOM_EXTERNAL_SS_MASK) != 0) 929 || (info.chipsetFlags & CHIP_APU) != 0 ) { 930 command = ATOM_DISABLE; 931 } 932 args.v2.ucEnable = command; 933 } else if (info.dceMajor >= 3) { 934 args.v1.usSpreadSpectrumPercentage 935 = B_HOST_TO_LENDIAN_INT16(pll->ssPercentage); 936 args.v1.ucSpreadSpectrumType 937 = pll->ssType & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 938 args.v1.ucSpreadSpectrumStep = pll->ssStep; 939 args.v1.ucSpreadSpectrumDelay = pll->ssDelay; 940 args.v1.ucSpreadSpectrumRange = pll->ssRange; 941 args.v1.ucPpll = pll->id; 942 args.v1.ucEnable = command; 943 } else if (info.dceMajor >= 2) { 944 if ((command == ATOM_DISABLE) || (pll->ssPercentage == 0) 945 || (pll->ssType & ATOM_EXTERNAL_SS_MASK)) { 946 // TODO: gpu_ss_disable needs pll id 947 radeon_gpu_ss_disable(); 948 return; 949 } 950 args.lvds_ss_2.usSpreadSpectrumPercentage 951 = B_HOST_TO_LENDIAN_INT16(pll->ssPercentage); 952 args.lvds_ss_2.ucSpreadSpectrumType 953 = pll->ssType & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 954 args.lvds_ss_2.ucSpreadSpectrumStep = pll->ssStep; 955 args.lvds_ss_2.ucSpreadSpectrumDelay = pll->ssDelay; 956 args.lvds_ss_2.ucSpreadSpectrumRange = pll->ssRange; 957 args.lvds_ss_2.ucEnable = command; 958 } else { 959 ERROR("%s: TODO: Old card SS control\n", __func__); 960 return; 961 } 962 963 atom_execute_table(gAtomContext, index, (uint32*)&args); 964 } 965 966 967 void 968 display_crtc_power(uint8 crtcID, int command) 969 { 970 TRACE("%s\n", __func__); 971 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); 972 ENABLE_CRTC_PS_ALLOCATION args; 973 974 memset(&args, 0, sizeof(args)); 975 976 args.ucCRTC = crtcID; 977 args.ucEnable = command; 978 979 atom_execute_table(gAtomContext, index, (uint32*)&args); 980 } 981 982 983 void 984 display_crtc_memreq(uint8 crtcID, int command) 985 { 986 TRACE("%s\n", __func__); 987 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); 988 ENABLE_CRTC_PS_ALLOCATION args; 989 990 memset(&args, 0, sizeof(args)); 991 992 args.ucCRTC = crtcID; 993 args.ucEnable = command; 994 995 atom_execute_table(gAtomContext, index, (uint32*)&args); 996 } 997