1 /* 2 * Copyright 2006-2011, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 * Alexander von Gluck, kallisti5@unixzen.com 8 */ 9 #ifndef RADEON_HD_ACCELERANT_H 10 #define RADEON_HD_ACCELERANT_H 11 12 13 #include "atom.h" 14 #include "encoder.h" 15 #include "mode.h" 16 #include "radeon_hd.h" 17 #include "pll.h" 18 19 20 #include <ByteOrder.h> 21 #include <edid.h> 22 23 24 #define MAX_DISPLAY 2 25 // Maximum displays (more then two requires AtomBIOS) 26 27 28 struct gpu_state_info { 29 uint32 d1vga_control; 30 uint32 d2vga_control; 31 uint32 vga_render_control; 32 uint32 vga_hdp_control; 33 uint32 d1crtc_control; 34 uint32 d2crtc_control; 35 }; 36 37 38 struct mc_info { 39 bool valid; 40 uint64 vramStart; 41 uint64 vramEnd; 42 uint64 vramSize; 43 }; 44 45 46 struct accelerant_info { 47 vuint8 *regs; 48 area_id regs_area; 49 50 radeon_shared_info *shared_info; 51 area_id shared_info_area; 52 53 display_mode *mode_list; // cloned list of standard display modes 54 area_id mode_list_area; 55 56 uint8* rom; 57 area_id rom_area; 58 59 edid1_info edid_info; 60 bool has_edid; 61 62 int device; 63 bool is_clone; 64 65 struct gpu_state_info gpu_info; // used for last known gpu state 66 struct mc_info mc; // used for memory controller info 67 68 volatile uint32 dpms_mode; // current driver dpms mode 69 70 // LVDS panel mode passed from the bios/startup. 71 display_mode lvds_panel_mode; 72 }; 73 74 75 struct register_info { 76 uint16 crtcOffset; 77 uint16 vgaControl; 78 uint16 grphEnable; 79 uint16 grphControl; 80 uint16 grphSwapControl; 81 uint16 grphPrimarySurfaceAddr; 82 uint16 grphSecondarySurfaceAddr; 83 uint16 grphPrimarySurfaceAddrHigh; 84 uint16 grphSecondarySurfaceAddrHigh; 85 uint16 grphPitch; 86 uint16 grphSurfaceOffsetX; 87 uint16 grphSurfaceOffsetY; 88 uint16 grphXStart; 89 uint16 grphYStart; 90 uint16 grphXEnd; 91 uint16 grphYEnd; 92 uint16 modeDesktopHeight; 93 uint16 modeDataFormat; 94 uint16 viewportStart; 95 uint16 viewportSize; 96 }; 97 98 99 typedef struct { 100 bool valid; 101 102 bool hw_capable; 103 uint32 hw_line; 104 105 uint32 mask_scl_reg; 106 uint32 mask_sda_reg; 107 uint32 mask_scl_mask; 108 uint32 mask_sda_mask; 109 110 uint32 en_scl_reg; 111 uint32 en_sda_reg; 112 uint32 en_scl_mask; 113 uint32 en_sda_mask; 114 115 uint32 y_scl_reg; 116 uint32 y_sda_reg; 117 uint32 y_scl_mask; 118 uint32 y_sda_mask; 119 120 uint32 a_scl_reg; 121 uint32 a_sda_reg; 122 uint32 a_scl_mask; 123 uint32 a_sda_mask; 124 } gpio_info; 125 126 127 struct encoder_info { 128 bool valid; 129 uint16 objectID; 130 uint32 type; 131 uint32 flags; 132 bool isExternal; 133 bool isHDMI; 134 bool isTV; 135 struct pll_info pll; 136 }; 137 138 139 typedef struct { 140 bool valid; 141 uint16 objectID; 142 uint32 type; 143 uint32 flags; 144 uint16 gpioID; 145 struct encoder_info encoder; 146 // TODO struct radeon_hpd hpd; 147 } connector_info; 148 149 150 typedef struct { 151 bool active; 152 uint32 connectorIndex; // matches connector id in connector_info 153 register_info *regs; 154 bool found_ranges; 155 uint32 vfreq_max; 156 uint32 vfreq_min; 157 uint32 hfreq_max; 158 uint32 hfreq_min; 159 edid1_info edid_info; 160 } display_info; 161 162 163 // register MMIO modes 164 #define OUT 0x1 // Direct MMIO calls 165 #define CRT 0x2 // Crt controller calls 166 #define VGA 0x3 // Vga calls 167 #define PLL 0x4 // PLL calls 168 #define MC 0x5 // Memory controller calls 169 170 171 extern accelerant_info *gInfo; 172 extern atom_context *gAtomContext; 173 extern display_info *gDisplay[MAX_DISPLAY]; 174 extern connector_info *gConnector[ATOM_MAX_SUPPORTED_DEVICE]; 175 extern gpio_info *gGPIOInfo[ATOM_MAX_SUPPORTED_DEVICE]; 176 177 178 // register access 179 180 inline uint32 181 _read32(uint32 offset) 182 { 183 return *(volatile uint32 *)(gInfo->regs + offset); 184 } 185 186 187 inline void 188 _write32(uint32 offset, uint32 value) 189 { 190 *(volatile uint32 *)(gInfo->regs + offset) = value; 191 } 192 193 194 // AtomBIOS cail register calls (are *4... no clue why) 195 inline uint32 196 Read32Cail(uint32 offset) 197 { 198 return _read32(offset * 4); 199 } 200 201 202 inline void 203 Write32Cail(uint32 offset, uint32 value) 204 { 205 _write32(offset * 4, value); 206 } 207 208 209 inline uint32 210 Read32(uint32 subsystem, uint32 offset) 211 { 212 switch (subsystem) { 213 default: 214 case OUT: 215 case VGA: 216 case CRT: 217 case PLL: 218 return _read32(offset); 219 case MC: 220 return _read32(offset); 221 }; 222 } 223 224 225 inline void 226 Write32(uint32 subsystem, uint32 offset, uint32 value) 227 { 228 switch (subsystem) { 229 default: 230 case OUT: 231 case VGA: 232 case CRT: 233 case PLL: 234 _write32(offset, value); 235 return; 236 case MC: 237 _write32(offset, value); 238 return; 239 }; 240 } 241 242 243 inline void 244 Write32Mask(uint32 subsystem, uint32 offset, uint32 value, uint32 mask) 245 { 246 uint32 temp; 247 switch (subsystem) { 248 default: 249 case OUT: 250 case VGA: 251 case MC: 252 temp = _read32(offset); 253 break; 254 case CRT: 255 temp = _read32(offset); 256 break; 257 case PLL: 258 temp = _read32(offset); 259 //temp = _read32PLL(offset); 260 break; 261 }; 262 263 // only effect mask 264 temp &= ~mask; 265 temp |= value & mask; 266 267 switch (subsystem) { 268 default: 269 case OUT: 270 case VGA: 271 case MC: 272 _write32(offset, temp); 273 return; 274 case CRT: 275 _write32(offset, temp); 276 return; 277 case PLL: 278 _write32(offset, temp); 279 //_write32PLL(offset, temp); 280 return; 281 }; 282 } 283 284 285 #endif /* RADEON_HD_ACCELERANT_H */ 286