1 /* 2 * Copyright 2006-2011, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 * Alexander von Gluck, kallisti5@unixzen.com 8 */ 9 #ifndef RADEON_HD_ACCELERANT_H 10 #define RADEON_HD_ACCELERANT_H 11 12 13 #include "atom.h" 14 #include "encoder.h" 15 #include "mode.h" 16 #include "radeon_hd.h" 17 #include "pll.h" 18 19 20 #include <ByteOrder.h> 21 #include <edid.h> 22 23 24 #define MAX_DISPLAY 2 25 // Maximum displays (more then two requires AtomBIOS) 26 27 28 typedef struct { 29 uint32 d1vga_control; 30 uint32 d2vga_control; 31 uint32 vga_render_control; 32 uint32 vga_hdp_control; 33 uint32 d1crtc_control; 34 uint32 d2crtc_control; 35 } gpu_mc_info; 36 37 38 struct accelerant_info { 39 vuint8 *regs; 40 area_id regs_area; 41 42 radeon_shared_info *shared_info; 43 area_id shared_info_area; 44 45 display_mode *mode_list; // cloned list of standard display modes 46 area_id mode_list_area; 47 48 uint8* rom; 49 area_id rom_area; 50 51 edid1_info edid_info; 52 bool has_edid; 53 54 int device; 55 bool is_clone; 56 57 gpu_mc_info *mc_info; // used for last known mc state 58 59 volatile uint32 dpms_mode; // current driver dpms mode 60 61 // LVDS panel mode passed from the bios/startup. 62 display_mode lvds_panel_mode; 63 }; 64 65 66 struct register_info { 67 uint16 vgaControl; 68 uint16 grphEnable; 69 uint16 grphUpdate; 70 uint16 grphControl; 71 uint16 grphSwapControl; 72 uint16 grphPrimarySurfaceAddr; 73 uint16 grphSecondarySurfaceAddr; 74 uint16 grphPrimarySurfaceAddrHigh; 75 uint16 grphSecondarySurfaceAddrHigh; 76 uint16 grphPitch; 77 uint16 grphSurfaceOffsetX; 78 uint16 grphSurfaceOffsetY; 79 uint16 grphXStart; 80 uint16 grphYStart; 81 uint16 grphXEnd; 82 uint16 grphYEnd; 83 uint16 crtControl; 84 uint16 crtCountControl; 85 uint16 crtInterlace; 86 uint16 crtHPolarity; 87 uint16 crtVPolarity; 88 uint16 crtHSync; 89 uint16 crtVSync; 90 uint16 crtHBlank; 91 uint16 crtVBlank; 92 uint16 crtHTotal; 93 uint16 crtVTotal; 94 uint16 crtcOffset; 95 uint16 modeDesktopHeight; 96 uint16 modeDataFormat; 97 uint16 modeCenter; 98 uint16 viewportStart; 99 uint16 viewportSize; 100 uint16 sclUpdate; 101 uint16 sclEnable; 102 uint16 sclTapControl; 103 }; 104 105 106 typedef struct { 107 bool valid; 108 109 bool hw_capable; 110 uint32 hw_line; 111 112 uint32 mask_scl_reg; 113 uint32 mask_sda_reg; 114 uint32 mask_scl_mask; 115 uint32 mask_sda_mask; 116 117 uint32 en_scl_reg; 118 uint32 en_sda_reg; 119 uint32 en_scl_mask; 120 uint32 en_sda_mask; 121 122 uint32 y_scl_reg; 123 uint32 y_sda_reg; 124 uint32 y_scl_mask; 125 uint32 y_sda_mask; 126 127 uint32 a_scl_reg; 128 uint32 a_sda_reg; 129 uint32 a_scl_mask; 130 uint32 a_sda_mask; 131 } gpio_info; 132 133 134 struct encoder_info { 135 bool valid; 136 uint16 objectID; 137 uint32 type; 138 uint32 flags; 139 bool isExternal; 140 bool isHDMI; 141 bool isTV; 142 struct pll_info pll; 143 }; 144 145 146 typedef struct { 147 bool valid; 148 uint16 objectID; 149 uint32 type; 150 uint32 flags; 151 uint16 gpioID; 152 struct encoder_info encoder; 153 // TODO struct radeon_hpd hpd; 154 } connector_info; 155 156 157 typedef struct { 158 bool active; 159 uint32 connectorIndex; // matches connector id in connector_info 160 register_info *regs; 161 bool found_ranges; 162 uint32 vfreq_max; 163 uint32 vfreq_min; 164 uint32 hfreq_max; 165 uint32 hfreq_min; 166 edid1_info edid_info; 167 } display_info; 168 169 170 // register MMIO modes 171 #define OUT 0x1 // Direct MMIO calls 172 #define CRT 0x2 // Crt controller calls 173 #define VGA 0x3 // Vga calls 174 #define PLL 0x4 // PLL calls 175 #define MC 0x5 // Memory controller calls 176 177 178 extern accelerant_info *gInfo; 179 extern atom_context *gAtomContext; 180 extern display_info *gDisplay[MAX_DISPLAY]; 181 extern connector_info *gConnector[ATOM_MAX_SUPPORTED_DEVICE]; 182 extern gpio_info *gGPIOInfo[ATOM_MAX_SUPPORTED_DEVICE]; 183 184 185 // register access 186 187 inline uint32 188 _read32(uint32 offset) 189 { 190 return *(volatile uint32 *)(gInfo->regs + offset); 191 } 192 193 194 inline void 195 _write32(uint32 offset, uint32 value) 196 { 197 *(volatile uint32 *)(gInfo->regs + offset) = value; 198 } 199 200 201 // AtomBIOS cail register calls (are *4... no clue why) 202 inline uint32 203 Read32Cail(uint32 offset) 204 { 205 return _read32(offset * 4); 206 } 207 208 209 inline void 210 Write32Cail(uint32 offset, uint32 value) 211 { 212 _write32(offset * 4, value); 213 } 214 215 216 inline uint32 217 Read32(uint32 subsystem, uint32 offset) 218 { 219 switch (subsystem) { 220 default: 221 case OUT: 222 case VGA: 223 case CRT: 224 case PLL: 225 return _read32(offset); 226 case MC: 227 return _read32(offset); 228 }; 229 } 230 231 232 inline void 233 Write32(uint32 subsystem, uint32 offset, uint32 value) 234 { 235 switch (subsystem) { 236 default: 237 case OUT: 238 case VGA: 239 case CRT: 240 case PLL: 241 _write32(offset, value); 242 return; 243 case MC: 244 _write32(offset, value); 245 return; 246 }; 247 } 248 249 250 inline void 251 Write32Mask(uint32 subsystem, uint32 offset, uint32 value, uint32 mask) 252 { 253 uint32 temp; 254 switch (subsystem) { 255 default: 256 case OUT: 257 case VGA: 258 case MC: 259 temp = _read32(offset); 260 break; 261 case CRT: 262 temp = _read32(offset); 263 break; 264 case PLL: 265 temp = _read32(offset); 266 //temp = _read32PLL(offset); 267 break; 268 }; 269 270 // only effect mask 271 temp &= ~mask; 272 temp |= value & mask; 273 274 switch (subsystem) { 275 default: 276 case OUT: 277 case VGA: 278 case MC: 279 _write32(offset, temp); 280 return; 281 case CRT: 282 _write32(offset, temp); 283 return; 284 case PLL: 285 _write32(offset, temp); 286 //_write32PLL(offset, temp); 287 return; 288 }; 289 } 290 291 292 #endif /* RADEON_HD_ACCELERANT_H */ 293