1 /* 2 * Copyright 2006-2011, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 * Alexander von Gluck, kallisti5@unixzen.com 8 */ 9 #ifndef RADEON_HD_ACCELERANT_H 10 #define RADEON_HD_ACCELERANT_H 11 12 13 #include <ByteOrder.h> 14 #include <edid.h> 15 16 #include "atom.h" 17 #include "dp.h" 18 #include "encoder.h" 19 #include "mode.h" 20 #include "pll.h" 21 #include "radeon_hd.h" 22 #include "ringqueue.h" 23 24 25 #define MAX_DISPLAY 2 26 // Maximum displays (more then two requires AtomBIOS) 27 28 29 struct gpu_state { 30 uint32 d1vgaControl; 31 uint32 d2vgaControl; 32 uint32 vgaRenderControl; 33 uint32 vgaHdpControl; 34 uint32 d1crtcControl; 35 uint32 d2crtcControl; 36 }; 37 38 39 struct fb_info { 40 bool valid; 41 uint64 vramStart; 42 uint64 vramEnd; 43 uint64 vramSize; 44 45 uint64 gartStart; 46 uint64 gartEnd; 47 uint64 gartSize; 48 uint64 agpBase; 49 }; 50 51 52 struct accelerant_info { 53 vuint8* regs; 54 area_id regs_area; 55 56 radeon_shared_info* shared_info; 57 area_id shared_info_area; 58 59 display_mode* mode_list; // cloned list of standard display modes 60 area_id mode_list_area; 61 62 uint8* rom; 63 area_id rom_area; 64 65 edid1_info edid_info; 66 bool has_edid; 67 68 int device; 69 bool is_clone; 70 71 struct fb_info fb; // used for frame buffer info within MC 72 73 volatile uint32 dpms_mode; // current driver dpms mode 74 75 uint16 maximumPixelClock; 76 uint32 displayClockFrequency; 77 uint32 dpExternalClock; 78 79 uint32 lvdsSpreadSpectrumID; 80 81 RingQueue* ringQueue[RADEON_QUEUE_MAX]; // Ring buffer command processor 82 }; 83 84 85 struct register_info { 86 uint16 crtcOffset; 87 uint16 vgaControl; 88 uint16 grphEnable; 89 uint16 grphControl; 90 uint16 grphSwapControl; 91 uint16 grphPrimarySurfaceAddr; 92 uint16 grphSecondarySurfaceAddr; 93 uint16 grphPrimarySurfaceAddrHigh; 94 uint16 grphSecondarySurfaceAddrHigh; 95 uint16 grphPitch; 96 uint16 grphSurfaceOffsetX; 97 uint16 grphSurfaceOffsetY; 98 uint16 grphXStart; 99 uint16 grphYStart; 100 uint16 grphXEnd; 101 uint16 grphYEnd; 102 uint16 modeDesktopHeight; 103 uint16 modeDataFormat; 104 uint16 viewportStart; 105 uint16 viewportSize; 106 }; 107 108 109 typedef struct { 110 bool valid; 111 112 uint32 hwPin; // GPIO hardware pin on GPU 113 bool hwCapable; // can do hw assisted i2c 114 115 uint32 sclMaskReg; 116 uint32 sdaMaskReg; 117 uint32 sclMask; 118 uint32 sdaMask; 119 120 uint32 sclEnReg; 121 uint32 sdaEnReg; 122 uint32 sclEnMask; 123 uint32 sdaEnMask; 124 125 uint32 sclYReg; 126 uint32 sdaYReg; 127 uint32 sclYMask; 128 uint32 sdaYMask; 129 130 uint32 sclAReg; 131 uint32 sdaAReg; 132 uint32 sclAMask; 133 uint32 sdaAMask; 134 } gpio_info; 135 136 137 struct encoder_info { 138 bool valid; 139 uint16 objectID; 140 uint32 type; 141 uint32 flags; 142 uint32 linkEnumeration; // ex. linkb == GRAPH_OBJECT_ENUM_ID2 143 bool isExternal; 144 bool isDPBridge; 145 struct pll_info pll; 146 }; 147 148 149 typedef struct { 150 bool valid; 151 uint16 objectID; 152 uint32 type; 153 uint32 flags; 154 uint32 lvdsFlags; 155 uint16 gpioID; 156 struct encoder_info encoder; 157 struct encoder_info encoderExternal; 158 // TODO struct radeon_hpd hpd; 159 dp_info dpInfo; 160 } connector_info; 161 162 163 typedef struct { 164 bool attached; 165 bool powered; 166 uint32 connectorIndex; // matches connector id in connector_info 167 register_info* regs; 168 bool foundRanges; 169 uint32 vfreqMax; 170 uint32 vfreqMin; 171 uint32 hfreqMax; 172 uint32 hfreqMin; 173 edid1_info edidData; 174 display_mode preferredMode; 175 } display_info; 176 177 178 // register MMIO modes 179 #define OUT 0x1 // Direct MMIO calls 180 #define CRT 0x2 // Crt controller calls 181 #define VGA 0x3 // Vga calls 182 #define PLL 0x4 // PLL calls 183 #define MC 0x5 // Memory controller calls 184 185 186 extern accelerant_info* gInfo; 187 extern atom_context* gAtomContext; 188 extern display_info* gDisplay[MAX_DISPLAY]; 189 extern connector_info* gConnector[ATOM_MAX_SUPPORTED_DEVICE]; 190 extern gpio_info* gGPIOInfo[ATOM_MAX_SUPPORTED_DEVICE]; 191 192 193 // register access 194 195 inline uint32 196 _read32(uint32 offset) 197 { 198 return *(volatile uint32*)(gInfo->regs + offset); 199 } 200 201 202 inline void 203 _write32(uint32 offset, uint32 value) 204 { 205 *(volatile uint32 *)(gInfo->regs + offset) = value; 206 } 207 208 209 // AtomBIOS cail register calls (are *4... no clue why) 210 inline uint32 211 Read32Cail(uint32 offset) 212 { 213 return _read32(offset * 4); 214 } 215 216 217 inline void 218 Write32Cail(uint32 offset, uint32 value) 219 { 220 _write32(offset * 4, value); 221 } 222 223 224 inline uint32 225 Read32(uint32 subsystem, uint32 offset) 226 { 227 switch (subsystem) { 228 default: 229 case OUT: 230 case VGA: 231 case CRT: 232 case PLL: 233 return _read32(offset); 234 case MC: 235 return _read32(offset); 236 }; 237 } 238 239 240 inline void 241 Write32(uint32 subsystem, uint32 offset, uint32 value) 242 { 243 switch (subsystem) { 244 default: 245 case OUT: 246 case VGA: 247 case CRT: 248 case PLL: 249 _write32(offset, value); 250 return; 251 case MC: 252 _write32(offset, value); 253 return; 254 }; 255 } 256 257 258 inline void 259 Write32Mask(uint32 subsystem, uint32 offset, uint32 value, uint32 mask) 260 { 261 uint32 temp; 262 switch (subsystem) { 263 default: 264 case OUT: 265 case VGA: 266 case MC: 267 temp = _read32(offset); 268 break; 269 case CRT: 270 temp = _read32(offset); 271 break; 272 case PLL: 273 temp = _read32(offset); 274 //temp = _read32PLL(offset); 275 break; 276 }; 277 278 // only effect mask 279 temp &= ~mask; 280 temp |= value & mask; 281 282 switch (subsystem) { 283 default: 284 case OUT: 285 case VGA: 286 case MC: 287 _write32(offset, temp); 288 return; 289 case CRT: 290 _write32(offset, temp); 291 return; 292 case PLL: 293 _write32(offset, temp); 294 //_write32PLL(offset, temp); 295 return; 296 }; 297 } 298 299 300 #endif /* RADEON_HD_ACCELERANT_H */ 301