1 /* 2 * Copyright 2006-2011, Haiku, Inc. All Rights Reserved. 3 * Distributed under the terms of the MIT License. 4 * 5 * Authors: 6 * Axel Dörfler, axeld@pinc-software.de 7 * Alexander von Gluck, kallisti5@unixzen.com 8 */ 9 #ifndef RADEON_HD_ACCELERANT_H 10 #define RADEON_HD_ACCELERANT_H 11 12 13 #include <ByteOrder.h> 14 #include <edid.h> 15 16 #include "atom.h" 17 #include "dp.h" 18 #include "encoder.h" 19 #include "mode.h" 20 #include "pll.h" 21 #include "radeon_hd.h" 22 #include "ringqueue.h" 23 24 25 #define MAX_DISPLAY 2 26 // Maximum displays (more then two requires AtomBIOS) 27 28 29 struct gpu_state { 30 uint32 d1vgaControl; 31 uint32 d2vgaControl; 32 uint32 vgaRenderControl; 33 uint32 vgaHdpControl; 34 uint32 d1crtcControl; 35 uint32 d2crtcControl; 36 }; 37 38 39 struct fb_info { 40 bool valid; 41 uint64 vramStart; 42 uint64 vramEnd; 43 uint64 vramSize; 44 45 uint64 gartStart; 46 uint64 gartEnd; 47 uint64 gartSize; 48 uint64 agpBase; 49 }; 50 51 52 struct accelerant_info { 53 vuint8* regs; 54 area_id regs_area; 55 56 radeon_shared_info* shared_info; 57 area_id shared_info_area; 58 59 display_mode* mode_list; // cloned list of standard display modes 60 area_id mode_list_area; 61 62 uint8* rom; 63 area_id rom_area; 64 65 edid1_info edid_info; 66 bool has_edid; 67 68 int device; 69 bool is_clone; 70 71 struct fb_info fb; // used for frame buffer info within MC 72 73 volatile uint32 dpms_mode; // current driver dpms mode 74 75 RingQueue* ringQueue[RADEON_QUEUE_MAX]; // Ring buffer command processor 76 }; 77 78 79 struct register_info { 80 uint16 crtcOffset; 81 uint16 vgaControl; 82 uint16 grphEnable; 83 uint16 grphControl; 84 uint16 grphSwapControl; 85 uint16 grphPrimarySurfaceAddr; 86 uint16 grphSecondarySurfaceAddr; 87 uint16 grphPrimarySurfaceAddrHigh; 88 uint16 grphSecondarySurfaceAddrHigh; 89 uint16 grphPitch; 90 uint16 grphSurfaceOffsetX; 91 uint16 grphSurfaceOffsetY; 92 uint16 grphXStart; 93 uint16 grphYStart; 94 uint16 grphXEnd; 95 uint16 grphYEnd; 96 uint16 modeDesktopHeight; 97 uint16 modeDataFormat; 98 uint16 viewportStart; 99 uint16 viewportSize; 100 }; 101 102 103 typedef struct { 104 bool valid; 105 106 uint32 hwPin; // GPIO hardware pin on GPU 107 bool hwCapable; // can do hw assisted i2c 108 109 uint32 sclMaskReg; 110 uint32 sdaMaskReg; 111 uint32 sclMask; 112 uint32 sdaMask; 113 114 uint32 sclEnReg; 115 uint32 sdaEnReg; 116 uint32 sclEnMask; 117 uint32 sdaEnMask; 118 119 uint32 sclYReg; 120 uint32 sdaYReg; 121 uint32 sclYMask; 122 uint32 sdaYMask; 123 124 uint32 sclAReg; 125 uint32 sdaAReg; 126 uint32 sclAMask; 127 uint32 sdaAMask; 128 } gpio_info; 129 130 131 struct encoder_info { 132 bool valid; 133 uint16 objectID; 134 uint32 type; 135 uint32 flags; 136 uint32 linkEnumeration; // ex. linkb == GRAPH_OBJECT_ENUM_ID2 137 bool isExternal; 138 bool isDPBridge; 139 struct pll_info pll; 140 }; 141 142 143 typedef struct { 144 bool valid; 145 uint16 objectID; 146 uint32 type; 147 uint32 flags; 148 uint32 lvdsFlags; 149 uint16 gpioID; 150 struct encoder_info encoder; 151 struct encoder_info encoderExternal; 152 // TODO struct radeon_hpd hpd; 153 dp_info dpInfo; 154 } connector_info; 155 156 157 typedef struct { 158 bool attached; 159 bool powered; 160 uint32 connectorIndex; // matches connector id in connector_info 161 register_info* regs; 162 bool foundRanges; 163 uint32 vfreqMax; 164 uint32 vfreqMin; 165 uint32 hfreqMax; 166 uint32 hfreqMin; 167 edid1_info edidData; 168 display_mode preferredMode; 169 } display_info; 170 171 172 // register MMIO modes 173 #define OUT 0x1 // Direct MMIO calls 174 #define CRT 0x2 // Crt controller calls 175 #define VGA 0x3 // Vga calls 176 #define PLL 0x4 // PLL calls 177 #define MC 0x5 // Memory controller calls 178 179 180 extern accelerant_info* gInfo; 181 extern atom_context* gAtomContext; 182 extern display_info* gDisplay[MAX_DISPLAY]; 183 extern connector_info* gConnector[ATOM_MAX_SUPPORTED_DEVICE]; 184 extern gpio_info* gGPIOInfo[ATOM_MAX_SUPPORTED_DEVICE]; 185 186 187 // register access 188 189 inline uint32 190 _read32(uint32 offset) 191 { 192 return *(volatile uint32*)(gInfo->regs + offset); 193 } 194 195 196 inline void 197 _write32(uint32 offset, uint32 value) 198 { 199 *(volatile uint32 *)(gInfo->regs + offset) = value; 200 } 201 202 203 // AtomBIOS cail register calls (are *4... no clue why) 204 inline uint32 205 Read32Cail(uint32 offset) 206 { 207 return _read32(offset * 4); 208 } 209 210 211 inline void 212 Write32Cail(uint32 offset, uint32 value) 213 { 214 _write32(offset * 4, value); 215 } 216 217 218 inline uint32 219 Read32(uint32 subsystem, uint32 offset) 220 { 221 switch (subsystem) { 222 default: 223 case OUT: 224 case VGA: 225 case CRT: 226 case PLL: 227 return _read32(offset); 228 case MC: 229 return _read32(offset); 230 }; 231 } 232 233 234 inline void 235 Write32(uint32 subsystem, uint32 offset, uint32 value) 236 { 237 switch (subsystem) { 238 default: 239 case OUT: 240 case VGA: 241 case CRT: 242 case PLL: 243 _write32(offset, value); 244 return; 245 case MC: 246 _write32(offset, value); 247 return; 248 }; 249 } 250 251 252 inline void 253 Write32Mask(uint32 subsystem, uint32 offset, uint32 value, uint32 mask) 254 { 255 uint32 temp; 256 switch (subsystem) { 257 default: 258 case OUT: 259 case VGA: 260 case MC: 261 temp = _read32(offset); 262 break; 263 case CRT: 264 temp = _read32(offset); 265 break; 266 case PLL: 267 temp = _read32(offset); 268 //temp = _read32PLL(offset); 269 break; 270 }; 271 272 // only effect mask 273 temp &= ~mask; 274 temp |= value & mask; 275 276 switch (subsystem) { 277 default: 278 case OUT: 279 case VGA: 280 case MC: 281 _write32(offset, temp); 282 return; 283 case CRT: 284 _write32(offset, temp); 285 return; 286 case PLL: 287 _write32(offset, temp); 288 //_write32PLL(offset, temp); 289 return; 290 }; 291 } 292 293 294 #endif /* RADEON_HD_ACCELERANT_H */ 295