1 /* 2 Copyright (c) 2002-2004, Thomas Kurschel 3 4 5 Part of Radeon accelerant 6 7 Flat panel support 8 */ 9 10 #include "radeon_accelerant.h" 11 #include "mmio.h" 12 #include "fp_regs.h" 13 #include "memcntrl_regs.h" 14 #include "utils.h" 15 #include "set_mode.h" 16 #include "pll_regs.h" 17 #include "pll_access.h" 18 19 20 void Radeon_ReadRMXRegisters( 21 accelerator_info *ai, fp_regs *values ) 22 { 23 vuint8 *regs = ai->regs; 24 25 values->fp_horz_stretch = INREG( regs, RADEON_FP_HORZ_STRETCH ); 26 values->fp_vert_stretch = INREG( regs, RADEON_FP_VERT_STRETCH ); 27 } 28 29 void Radeon_CalcRMXRegisters( 30 fp_info *flatpanel, display_mode *mode, bool use_rmx, fp_regs *values ) 31 { 32 uint xres = mode->timing.h_display; 33 uint yres = mode->timing.v_display; 34 uint64 Hratio, Vratio; 35 36 if( !use_rmx ) { 37 // disable RMX unit if requested 38 values->fp_horz_stretch &= 39 ~(RADEON_HORZ_STRETCH_BLEND | 40 RADEON_HORZ_STRETCH_ENABLE); 41 42 values->fp_vert_stretch &= 43 ~(RADEON_VERT_STRETCH_ENABLE | 44 RADEON_VERT_STRETCH_BLEND); 45 46 return; 47 } 48 49 // RMX unit can only upscale, not downscale 50 if( xres > flatpanel->panel_xres ) 51 xres = flatpanel->panel_xres; 52 if( yres > flatpanel->panel_yres ) 53 yres = flatpanel->panel_yres; 54 55 Hratio = FIX_SCALE * (uint32)xres / flatpanel->panel_xres; 56 Vratio = FIX_SCALE * (uint32)yres / flatpanel->panel_yres; 57 58 // save it for overlay unit (overlays must be vertically scaled manually) 59 flatpanel->h_ratio = Hratio; 60 flatpanel->v_ratio = Vratio; 61 62 values->fp_horz_stretch = flatpanel->panel_xres << RADEON_HORZ_PANEL_SIZE_SHIFT; 63 64 if( Hratio == FIX_SCALE ) { 65 values->fp_horz_stretch &= 66 ~(RADEON_HORZ_STRETCH_BLEND | 67 RADEON_HORZ_STRETCH_ENABLE); 68 } else { 69 uint32 stretch; 70 71 stretch = (uint32)((Hratio * RADEON_HORZ_STRETCH_RATIO_MAX + 72 FIX_SCALE / 2) >> FIX_SHIFT) & RADEON_HORZ_STRETCH_RATIO_MASK; 73 74 values->fp_horz_stretch = stretch 75 | (values->fp_horz_stretch & (RADEON_HORZ_PANEL_SIZE | 76 RADEON_HORZ_FP_LOOP_STRETCH | 77 RADEON_HORZ_AUTO_RATIO_INC)); 78 values->fp_horz_stretch |= 79 RADEON_HORZ_STRETCH_BLEND | 80 RADEON_HORZ_STRETCH_ENABLE; 81 } 82 values->fp_horz_stretch &= ~RADEON_HORZ_AUTO_RATIO; 83 84 values->fp_vert_stretch = flatpanel->panel_yres << RADEON_VERT_PANEL_SIZE_SHIFT; 85 86 if( Vratio == FIX_SCALE ) { 87 values->fp_vert_stretch &= 88 ~(RADEON_VERT_STRETCH_ENABLE | 89 RADEON_VERT_STRETCH_BLEND); 90 } else { 91 uint32 stretch; 92 93 stretch = (uint32)((Vratio * RADEON_VERT_STRETCH_RATIO_MAX + 94 FIX_SCALE / 2) >> FIX_SHIFT) & RADEON_VERT_STRETCH_RATIO_MASK; 95 96 values->fp_vert_stretch = stretch 97 | (values->fp_vert_stretch & (RADEON_VERT_PANEL_SIZE | 98 RADEON_VERT_STRETCH_RESERVED)); 99 values->fp_vert_stretch |= 100 RADEON_VERT_STRETCH_ENABLE | 101 RADEON_VERT_STRETCH_BLEND; 102 } 103 values->fp_vert_stretch &= ~RADEON_VERT_AUTO_RATIO_EN; 104 } 105 106 // write RMX registers 107 void Radeon_ProgramRMXRegisters( 108 accelerator_info *ai, fp_regs *values ) 109 { 110 vuint8 *regs = ai->regs; 111 112 OUTREG( regs, RADEON_FP_HORZ_STRETCH, values->fp_horz_stretch ); 113 OUTREG( regs, RADEON_FP_VERT_STRETCH, values->fp_vert_stretch ); 114 } 115 116 117 void Radeon_ReadFPRegisters( 118 accelerator_info *ai, fp_regs *values ) 119 { 120 vuint8 *regs = ai->regs; 121 122 values->fp_gen_cntl = INREG( regs, RADEON_FP_GEN_CNTL ); 123 values->fp2_gen_cntl = INREG( regs, RADEON_FP2_GEN_CNTL ); 124 values->lvds_gen_cntl = INREG( regs, RADEON_LVDS_GEN_CNTL ); 125 values->fp_h_sync_strt_wid = INREG( regs, RADEON_FP_H_SYNC_STRT_WID ); 126 values->fp_v_sync_strt_wid = INREG( regs, RADEON_FP_V_SYNC_STRT_WID ); 127 values->fp2_h_sync_strt_wid = INREG( regs, RADEON_FP_H2_SYNC_STRT_WID ); 128 values->fp2_v_sync_strt_wid = INREG( regs, RADEON_FP_V2_SYNC_STRT_WID ); 129 130 SHOW_FLOW( 2, "before: fp_gen_cntl=%08lx, horz=%08lx, vert=%08lx, lvds_gen_cntl=%08lx", 131 values->fp_gen_cntl, values->fp_horz_stretch, values->fp_vert_stretch, 132 values->lvds_gen_cntl ); 133 } 134 135 // calculcate flat panel crtc registers; 136 // must be called after normal CRTC registers are determined 137 void Radeon_CalcFPRegisters( 138 accelerator_info *ai, crtc_info *crtc, 139 fp_info *fp_port, crtc_regs *crtc_values, fp_regs *values ) 140 { 141 // setup synchronization position 142 // (most values are ignored according to fp_gen_cntl, but at least polarity 143 // and pixel precise horizontal sync position are always used) 144 if( fp_port->is_fp2 ) { 145 values->fp2_h_sync_strt_wid = crtc_values->crtc_h_sync_strt_wid; 146 values->fp2_v_sync_strt_wid = crtc_values->crtc_v_sync_strt_wid; 147 } else { 148 values->fp_h_sync_strt_wid = crtc_values->crtc_h_sync_strt_wid; 149 values->fp_v_sync_strt_wid = crtc_values->crtc_v_sync_strt_wid; 150 } 151 152 if( fp_port->is_fp2 ) 153 values->fp2_gen_cntl = 0; 154 else { 155 // setup magic CRTC shadowing 156 values->fp_gen_cntl &= 157 ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN | 158 RADEON_FP_DFP_SYNC_SEL | 159 RADEON_FP_CRT_SYNC_SEL | 160 RADEON_FP_CRTC_LOCK_8DOT | 161 RADEON_FP_USE_SHADOW_EN | 162 RADEON_FP_CRTC_USE_SHADOW_VEND | 163 RADEON_FP_CRT_SYNC_ALT); 164 values->fp_gen_cntl |= 165 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 166 RADEON_FP_CRTC_DONT_SHADOW_HEND; 167 } 168 169 // enable proper transmitter 170 if( (crtc->chosen_displays & dd_lvds) != 0 ) { 171 // using LVDS means there cannot be a DVI monitor 172 values->lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_BLON); 173 values->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); 174 175 } else if( !fp_port->is_fp2 ) { 176 // DVI on internal transmitter 177 values->fp_gen_cntl |= RADEON_FP_FPON | RADEON_FP_TMDS_EN; 178 // enabling 8 bit data may be dangerous; BIOS should have taken care of that 179 values->fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; 180 181 } else { 182 // DVI on external transmitter 183 values->fp2_gen_cntl |= RADEON_FP2_FPON | RADEON_FP_PANEL_FORMAT; 184 values->fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN; 185 186 if( ai->si->asic >= rt_r200 ) 187 values->fp2_gen_cntl |= RADEON_FP2_DV0_EN; 188 } 189 190 SHOW_FLOW( 2, "after: fp_gen_cntl=%08lx, horz=%08lx, vert=%08lx, lvds_gen_cntl=%08lx", 191 values->fp_gen_cntl, values->fp_horz_stretch, values->fp_vert_stretch, 192 values->lvds_gen_cntl ); 193 } 194 195 196 // write flat panel registers 197 void Radeon_ProgramFPRegisters( 198 accelerator_info *ai, crtc_info *crtc, 199 fp_info *fp_port, fp_regs *values ) 200 { 201 shared_info *si = ai->si; 202 vuint8 *regs = ai->regs; 203 204 SHOW_FLOW0( 2, "" ); 205 206 OUTREGP( regs, RADEON_FP_GEN_CNTL, values->fp_gen_cntl, RADEON_FP_SEL_CRTC2 ); 207 208 if( fp_port->is_fp2 ) { 209 OUTREGP( regs, RADEON_FP2_GEN_CNTL, values->fp2_gen_cntl, 210 RADEON_FP2_SOURCE_SEL_CRTC2 | RADEON_FP2_SRC_SEL_CRTC2 ); 211 OUTREG( regs, RADEON_FP_H2_SYNC_STRT_WID, values->fp2_h_sync_strt_wid ); 212 OUTREG( regs, RADEON_FP_V2_SYNC_STRT_WID, values->fp2_v_sync_strt_wid ); 213 } else { 214 OUTREG( regs, RADEON_FP_H_SYNC_STRT_WID, values->fp_h_sync_strt_wid ); 215 OUTREG( regs, RADEON_FP_V_SYNC_STRT_WID, values->fp_v_sync_strt_wid ); 216 } 217 218 // workaround for old AIW Radeon having display buffer underflow 219 // in conjunction with DVI 220 if( si->asic == rt_r100 ) { 221 OUTREG( regs, RADEON_GRPH_BUFFER_CNTL, 222 INREG( regs, RADEON_GRPH_BUFFER_CNTL) & ~0x7f0000); 223 } 224 225 if( (crtc->chosen_displays & dd_lvds) != 0 ) { 226 OUTREGP( regs, RADEON_LVDS_GEN_CNTL, values->lvds_gen_cntl, 227 RADEON_LVDS_ON | RADEON_LVDS_BLON ); 228 } 229 } 230