xref: /haiku/src/add-ons/accelerants/nvidia/engine/nv_proto.h (revision 81f5654c124bf46fba0fd251f208e2d88d81e1ce)
1 /*general card functions*/
2 status_t nv_general_powerup(void);
3 status_t nv_set_cas_latency(void);
4 void setup_virtualized_heads(bool);
5 void set_crtc_owner(bool);
6 status_t nv_general_output_select(bool);
7 status_t nv_general_head_select(bool);
8 status_t nv_general_wait_retrace(void);
9 status_t nv_general_validate_pic_size (display_mode *target, uint32 *bytes_per_row, bool *acc_mode);
10 
11 /* apsed: logging macros */
12 #define MSG(args) do { /* if needed or si->settings with si NULL */ \
13 	nv_log args; \
14 } while (0)
15 #define LOG(level_bit, args) do { \
16 	uint32 mod = (si->settings.logmask &  0xfffffff0) & MODULE_BIT; \
17 	uint32 lev = (si->settings.logmask & ~0xfffffff0) & level_bit; \
18 	if (mod && lev) nv_log args; \
19 } while (0)
20 
21 /*support functions*/
22 void delay(bigtime_t i);
23 void nv_log(char *format, ...);
24 
25 /*i2c maven functions*/
26 int i2c_maven_read(unsigned char address);
27 void i2c_maven_write(unsigned char address, unsigned char data);
28 status_t i2c_init(void);
29 status_t i2c_maven_probe(void);
30 
31 /*card info functions*/
32 status_t parse_pins(void);
33 void get_panel_modes(display_mode *p1, display_mode *p2, bool *pan1, bool *pan2);
34 void fake_pins(void);
35 void dump_pins(void);
36 
37 /* DAC functions */
38 bool nv_dac_crt_connected(void);
39 status_t nv_dac_mode(int,float);
40 status_t nv_dac_palette(uint8*,uint8*,uint8*);
41 status_t nv_dac_pix_pll_find(display_mode target,float * result,uint8 *,uint8 *,uint8 *, uint8);
42 status_t nv_dac_set_pix_pll(display_mode target);
43 status_t g400_dac_set_sys_pll(void);
44 
45 /* DAC2 functions */
46 bool nv_dac2_crt_connected(void);
47 status_t nv_dac2_mode(int,float);
48 status_t nv_dac2_palette(uint8*,uint8*,uint8*);
49 status_t nv_dac2_pix_pll_find(display_mode target,float * result,uint8 *,uint8 *,uint8 *, uint8);
50 status_t nv_dac2_set_pix_pll(display_mode target);
51 
52 /*MAVENTV functions*/
53 status_t g100_g400max_maventv_vid_pll_find(
54 	display_mode target, unsigned int * ht_new, unsigned int * ht_last_line,
55 	uint8 * m_result, uint8 * n_result, uint8 * p_result);
56 int maventv_init(display_mode target);
57 
58 /* CRTC1 functions */
59 status_t nv_crtc_validate_timing(
60 	uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht,
61 	uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt
62 );
63 status_t nv_crtc_set_timing(display_mode target);
64 status_t nv_crtc_depth(int mode);
65 status_t nv_crtc_set_display_start(uint32 startadd,uint8 bpp);
66 status_t nv_crtc_set_display_pitch(void);
67 
68 status_t nv_crtc_dpms(bool, bool, bool);
69 status_t nv_crtc_dpms_fetch(bool*, bool*, bool*);
70 status_t nv_crtc_mem_priority(uint8);
71 
72 status_t nv_crtc_cursor_init(void); /*Yes, cursor follows CRTC1 - not the DAC!*/
73 status_t nv_crtc_cursor_define(uint8*,uint8*);
74 status_t nv_crtc_cursor_position(uint16 x ,uint16 y);
75 status_t nv_crtc_cursor_show(void);
76 status_t nv_crtc_cursor_hide(void);
77 
78 /* CRTC2 functions */
79 status_t nv_crtc2_validate_timing(
80 	uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht,
81 	uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt
82 );
83 status_t nv_crtc2_set_timing(display_mode target);
84 status_t nv_crtc2_depth(int mode);
85 status_t nv_crtc2_set_display_start(uint32 startadd,uint8 bpp);
86 status_t nv_crtc2_set_display_pitch(void);
87 
88 status_t nv_crtc2_dpms(bool, bool, bool);
89 status_t nv_crtc2_dpms_fetch(bool*, bool*, bool*);
90 status_t nv_crtc2_mem_priority(uint8);
91 
92 status_t nv_crtc2_cursor_init(void); /*Yes, cursor follows CRTC1 - not the DAC!*/
93 status_t nv_crtc2_cursor_define(uint8*,uint8*);
94 status_t nv_crtc2_cursor_position(uint16 x ,uint16 y);
95 status_t nv_crtc2_cursor_show(void);
96 status_t nv_crtc2_cursor_hide(void);
97 
98 /*acceleration functions*/
99 status_t check_acc_capability(uint32 feature);
100 status_t nv_acc_init(void);
101 status_t nv_acc_setup_blit(void);
102 status_t nv_acc_blit(uint16,uint16,uint16, uint16,uint16,uint16 );
103 status_t nv_acc_setup_rectangle(uint32 color);
104 status_t nv_acc_rectangle(uint32 xs,uint32 xe,uint32 ys,uint32 yl);
105 status_t nv_acc_setup_rect_invert(void);
106 status_t nv_acc_rectangle_invert(uint32 xs,uint32 xe,uint32 ys,uint32 yl);
107 status_t nv_acc_transparent_blit(uint16,uint16,uint16, uint16,uint16,uint16, uint32);
108 status_t nv_acc_video_blit(uint16 xs,uint16 ys,uint16 ws, uint16 hs,
109 	uint16 xd,uint16 yd,uint16 wd,uint16 hd);
110 status_t nv_acc_wait_idle(void);
111 
112 /*backend scaler functions*/
113 status_t check_overlay_capability(uint32 feature);
114 void nv_bes_move_overlay(void);
115 status_t nv_bes_to_crtc(bool crtc);
116 status_t nv_bes_init(void);
117 status_t nv_configure_bes
118 	(const overlay_buffer *ob, const overlay_window *ow,const overlay_view *ov, int offset);
119 status_t nv_release_bes(void);
120 
121 /* I2C functions */
122 status_t i2c_sec_tv_adapter(void);
123 
124 /*driver structures and enums*/
125 enum{BPP8=0,BPP15=1,BPP16=2,BPP24=3,BPP32=4};
126 enum{DS_CRTC1DAC_CRTC2MAVEN, DS_CRTC1MAVEN_CRTC2DAC, DS_CRTC1CON1_CRTC2CON2, DS_CRTC1CON2_CRTC2CON1};
127