xref: /haiku/src/add-ons/accelerants/nvidia/engine/nv_proto.h (revision 2f470aec1c92ce6917b8a903e343795dc77af41f)
1 /* general card functions */
2 status_t nv_general_powerup(void);
3 status_t nv_set_cas_latency(void);
4 void setup_virtualized_heads(bool);
5 void set_crtc_owner(bool);
6 status_t nv_general_output_select(bool);
7 status_t nv_general_head_select(bool);
8 status_t nv_general_validate_pic_size (display_mode *target, uint32 *bytes_per_row, bool *acc_mode);
9 
10 /* AGP functions */
11 status_t nv_agp_setup(bool enable_agp);
12 
13 /* apsed: logging macros */
14 #define MSG(args) do { /* if needed or si->settings with si NULL */ \
15 	nv_log args; \
16 } while (0)
17 #define LOG(level_bit, args) do { \
18 	uint32 mod = (si->settings.logmask &  0xfffffff0) & MODULE_BIT; \
19 	uint32 lev = (si->settings.logmask & ~0xfffffff0) & level_bit; \
20 	if (mod && lev) nv_log args; \
21 } while (0)
22 
23 /* support functions */
24 void delay(bigtime_t i);
25 void nv_log(char *format, ...);
26 
27 /* i2c functions */
28 status_t i2c_sec_tv_adapter(void);
29 char i2c_flag_error (char ErrNo);
30 void i2c_bstart (uint8 BusNR);
31 void i2c_bstop (uint8 BusNR);
32 uint8 i2c_readbyte(uint8 BusNR, bool Ack);
33 bool i2c_writebyte (uint8 BusNR, uint8 byte);
34 void i2c_readbuffer (uint8 BusNR, uint8* buf, uint8 size);
35 void i2c_writebuffer (uint8 BusNR, uint8* buf, uint8 size);
36 status_t i2c_init(void);
37 
38 /* card info functions */
39 status_t parse_pins(void);
40 void set_pll(uint32 reg, uint32 clk);
41 void get_panel_modes(display_mode *p1, display_mode *p2, bool *pan1, bool *pan2);
42 void fake_panel_start(void);
43 void set_specs(void);
44 void dump_pins(void);
45 
46 /* DAC functions */
47 bool nv_dac_crt_connected(void);
48 status_t nv_dac_mode(int,float);
49 status_t nv_dac_palette(uint8*,uint8*,uint8*);
50 status_t nv_dac_pix_pll_find(display_mode target,float * result,uint8 *,uint8 *,uint8 *, uint8);
51 status_t nv_dac_set_pix_pll(display_mode target);
52 status_t nv_dac_sys_pll_find(float, float*, uint8*, uint8*, uint8*, uint8);
53 
54 /* DAC2 functions */
55 bool nv_dac2_crt_connected(void);
56 status_t nv_dac2_mode(int,float);
57 status_t nv_dac2_palette(uint8*,uint8*,uint8*);
58 status_t nv_dac2_pix_pll_find(display_mode target,float * result,uint8 *,uint8 *,uint8 *, uint8);
59 status_t nv_dac2_set_pix_pll(display_mode target);
60 
61 /* Brooktree TV functions */
62 bool BT_probe(void);
63 uint8 BT_dpms(bool display);
64 uint8 BT_check_tvmode(display_mode target);
65 status_t BT_stop_tvout(void);
66 status_t BT_setmode(display_mode target);
67 
68 /* CRTC1 functions */
69 status_t nv_crtc_interrupt_enable(bool);
70 status_t nv_crtc_update_fifo(void);
71 status_t nv_crtc_validate_timing(
72 	uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht,
73 	uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt);
74 status_t nv_crtc_set_timing(display_mode target);
75 status_t nv_crtc_depth(int mode);
76 status_t nv_crtc_set_display_start(uint32 startadd,uint8 bpp);
77 status_t nv_crtc_set_display_pitch(void);
78 status_t nv_crtc_dpms(bool, bool, bool, bool);
79 status_t nv_crtc_mem_priority(uint8);
80 status_t nv_crtc_cursor_init(void);
81 status_t nv_crtc_cursor_define(uint8*,uint8*);
82 status_t nv_crtc_cursor_position(uint16 x ,uint16 y);
83 status_t nv_crtc_cursor_show(void);
84 status_t nv_crtc_cursor_hide(void);
85 status_t nv_crtc_stop_tvout(void);
86 status_t nv_crtc_start_tvout(void);
87 
88 /* CRTC2 functions */
89 status_t nv_crtc2_interrupt_enable(bool);
90 status_t nv_crtc2_update_fifo(void);
91 status_t nv_crtc2_validate_timing(
92 	uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht,
93 	uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt);
94 status_t nv_crtc2_set_timing(display_mode target);
95 status_t nv_crtc2_depth(int mode);
96 status_t nv_crtc2_set_display_start(uint32 startadd,uint8 bpp);
97 status_t nv_crtc2_set_display_pitch(void);
98 status_t nv_crtc2_dpms(bool, bool, bool, bool);
99 status_t nv_crtc2_mem_priority(uint8);
100 status_t nv_crtc2_cursor_init(void);
101 status_t nv_crtc2_cursor_define(uint8*,uint8*);
102 status_t nv_crtc2_cursor_position(uint16 x ,uint16 y);
103 status_t nv_crtc2_cursor_show(void);
104 status_t nv_crtc2_cursor_hide(void);
105 status_t nv_crtc2_stop_tvout(void);
106 status_t nv_crtc2_start_tvout(void);
107 
108 /* acceleration functions */
109 status_t check_acc_capability(uint32 feature);
110 status_t nv_acc_init(void);
111 void nv_acc_assert_fifo(void);
112 status_t nv_acc_setup_blit(void);
113 status_t nv_acc_blit(uint16,uint16,uint16, uint16,uint16,uint16 );
114 status_t nv_acc_setup_rectangle(uint32 color);
115 status_t nv_acc_rectangle(uint32 xs,uint32 xe,uint32 ys,uint32 yl);
116 status_t nv_acc_setup_rect_invert(void);
117 status_t nv_acc_rectangle_invert(uint32 xs,uint32 xe,uint32 ys,uint32 yl);
118 status_t nv_acc_transparent_blit(uint16,uint16,uint16, uint16,uint16,uint16, uint32);
119 status_t nv_acc_video_blit(uint16 xs,uint16 ys,uint16 ws, uint16 hs,
120 	uint16 xd,uint16 yd,uint16 wd,uint16 hd);
121 status_t nv_acc_wait_idle(void);
122 /* DMA versions */
123 status_t nv_acc_wait_idle_dma(void);
124 status_t nv_acc_init_dma(void);
125 void nv_acc_assert_fifo_dma(void);
126 void SCREEN_TO_SCREEN_BLIT_DMA(engine_token *et, blit_params *list, uint32 count);
127 void SCREEN_TO_SCREEN_TRANSPARENT_BLIT_DMA(engine_token *et, uint32 transparent_colour, blit_params *list, uint32 count);
128 void SCREEN_TO_SCREEN_SCALED_FILTERED_BLIT_DMA(engine_token *et, scaled_blit_params *list, uint32 count);
129 void FILL_RECTANGLE_DMA(engine_token *et, uint32 color, fill_rect_params *list, uint32 count);
130 void INVERT_RECTANGLE_DMA(engine_token *et, fill_rect_params *list, uint32 count);
131 void FILL_SPAN_DMA(engine_token *et, uint32 color, uint16 *list, uint32 count);
132 
133 /* backend scaler functions */
134 status_t check_overlay_capability(uint32 feature);
135 void nv_bes_move_overlay(void);
136 status_t nv_bes_to_crtc(bool crtc);
137 status_t nv_bes_init(void);
138 status_t nv_configure_bes
139 	(const overlay_buffer *ob, const overlay_window *ow,const overlay_view *ov, int offset);
140 status_t nv_release_bes(void);
141 
142 /* driver structures and enums */
143 enum{BPP8 = 0, BPP15 = 1, BPP16 = 2, BPP24 = 3, BPP32 = 4};
144