1 /* Read initialisation information from card */ 2 /* some bits are hacks, where PINS is not known */ 3 /* Author: 4 Rudolf Cornelissen 7/2003-11/2009 5 */ 6 7 #define MODULE_BIT 0x00002000 8 9 #include "nv_std.h" 10 11 /* pins V5.16 and up ROM infoblock stuff */ 12 typedef struct { 13 uint16 InitScriptTablePtr; /* ptr to list of ptrs to scripts to exec */ 14 uint16 MacroIndexTablePtr; /* ptr to list with indexes and sizes of items in MacroTable */ 15 uint16 MacroTablePtr; /* ptr to list with items containing multiple 32bit reg writes */ 16 uint16 ConditionTablePtr; /* ptr to list of PCI regs and bits to tst for exec mode */ 17 uint16 IOConditionTablePtr; /* ptr to list of ISA regs and bits to tst for exec mode */ 18 uint16 IOFlagConditionTablePtr;/* ptr to list of ISA regs and bits to tst, ref'd to a matrix, for exec mode */ 19 uint16 InitFunctionTablePtr; /* ptr to list of startadresses of fixed ROM init routines */ 20 } PinsTables; 21 22 static void detect_panels(void); 23 static void setup_output_matrix(void); 24 static void pinsnv4_fake(void); 25 static void pinsnv5_nv5m64_fake(void); 26 static void pinsnv6_fake(void); 27 static void pinsnv10_arch_fake(void); 28 static void pinsnv20_arch_fake(void); 29 static void pinsnv30_arch_fake(void); 30 static void getRAMsize_arch_nv4(void); 31 static void getstrap_arch_nv4(void); 32 static void getRAMsize_arch_nv10_20_30_40(void); 33 static void getstrap_arch_nv10_20_30_40(void); 34 static status_t pins2_read(uint8 *rom, uint32 offset); 35 static status_t pins3_5_read(uint8 *rom, uint32 offset); 36 static status_t coldstart_card(uint8* rom, uint16 init1, uint16 init2, uint16 init_size, uint16 ram_tab); 37 static status_t coldstart_card_516_up(uint8* rom, PinsTables tabs, uint16 ram_tab); 38 static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 ram_tab); 39 static status_t exec_type2_script(uint8* rom, uint16 adress, int16* size, PinsTables tabs, uint16 ram_tab); 40 static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, PinsTables tabs, uint16 ram_tab, bool* exec); 41 static void exec_cmd_39_type2(uint8* rom, uint32 data, PinsTables tabs, bool* exec); 42 static void log_pll(uint32 reg, uint32 freq); 43 static void setup_ram_config(uint8* rom, uint16 ram_tab); 44 static void setup_ram_config_nv10_up(uint8* rom); 45 static void setup_ram_config_nv28(uint8* rom); 46 static status_t translate_ISA_PCI(uint32* reg); 47 static status_t nv_crtc_setup_fifo(void); 48 49 /* Parse the BIOS PINS structure if there */ 50 status_t parse_pins () 51 { 52 uint8 *rom; 53 uint8 chksum = 0; 54 int i; 55 uint32 offset; 56 status_t result = B_ERROR; 57 58 /* preset PINS read status to failed */ 59 si->ps.pins_status = B_ERROR; 60 61 /* check the validity of PINS */ 62 LOG(2,("INFO: Reading PINS info\n")); 63 rom = (uint8 *) si->rom_mirror; 64 /* check BIOS signature - this is defined in the PCI standard */ 65 if (rom[0]!=0x55 || rom[1]!=0xaa) 66 { 67 LOG(8,("INFO: BIOS signature not found\n")); 68 return B_ERROR; 69 } 70 LOG(2,("INFO: BIOS signature $AA55 found OK\n")); 71 72 /* find the PINS struct adress */ 73 for (offset = 0; offset < 65536; offset++) 74 { 75 if (rom[offset ] != 0xff) continue; 76 if (rom[offset + 1] != 0x7f) continue; 77 if (rom[offset + 2] != 0x4e) continue; /* N */ 78 if (rom[offset + 3] != 0x56) continue; /* V */ 79 if (rom[offset + 4] != 0x00) continue; 80 81 LOG(8,("INFO: PINS signature found\n")); 82 break; 83 } 84 85 if (offset > 65535) 86 { 87 LOG(8,("INFO: PINS signature not found\n")); 88 return B_ERROR; 89 } 90 91 /* verify PINS checksum */ 92 for (i = 0; i < 8; i++) 93 { 94 chksum += rom[offset + i]; 95 } 96 if (chksum) 97 { 98 LOG(8,("INFO: PINS checksum error\n")); 99 return B_ERROR; 100 } 101 102 /* checkout PINS struct version */ 103 LOG(2,("INFO: PINS checksum is OK; PINS version is %d.%d\n", 104 rom[offset + 5], rom[offset + 6])); 105 106 /* update the si->ps struct as far as is possible and coldstart card */ 107 //fixme: NV40 and up(?) nolonger use this system... 108 switch (rom[offset + 5]) 109 { 110 case 2: 111 result = pins2_read(rom, offset); 112 break; 113 case 3: 114 case 4: 115 case 5: 116 result = pins3_5_read(rom, offset); 117 break; 118 default: 119 LOG(8,("INFO: unknown PINS version\n")); 120 return B_ERROR; 121 break; 122 } 123 124 /* check PINS read result */ 125 if (result == B_ERROR) 126 { 127 LOG(8,("INFO: PINS read/decode/execute error\n")); 128 return B_ERROR; 129 } 130 /* PINS scan succeeded */ 131 si->ps.pins_status = B_OK; 132 LOG(2,("INFO: PINS scan completed succesfully\n")); 133 return B_OK; 134 } 135 136 static status_t pins2_read(uint8 *rom, uint32 offset) 137 { 138 uint16 init1 = rom[offset + 18] + (rom[offset + 19] * 256); 139 uint16 init2 = rom[offset + 20] + (rom[offset + 21] * 256); 140 uint16 init_size = rom[offset + 22] + (rom[offset + 23] * 256) + 1; 141 /* confirmed by comparing cards */ 142 uint16 ram_tab = init1 - 0x0010; 143 /* fixme: PPC BIOSes (might) return NULL pointers for messages here */ 144 char* signon_msg = &(rom[(rom[offset + 24] + (rom[offset + 25] * 256))]); 145 char* vendor_name = &(rom[(rom[offset + 40] + (rom[offset + 41] * 256))]); 146 char* product_name = &(rom[(rom[offset + 42] + (rom[offset + 43] * 256))]); 147 char* product_rev = &(rom[(rom[offset + 44] + (rom[offset + 45] * 256))]); 148 149 LOG(8,("INFO: cmdlist 1: $%04x, 2: $%04x, max. size $%04x\n", init1, init2, init_size)); 150 LOG(8,("INFO: signon msg:\n%s\n", signon_msg)); 151 LOG(8,("INFO: vendor name: %s\n", vendor_name)); 152 LOG(8,("INFO: product name: %s\n", product_name)); 153 LOG(8,("INFO: product rev: %s\n", product_rev)); 154 155 return coldstart_card(rom, init1, init2, init_size, ram_tab); 156 } 157 158 static status_t pins3_5_read(uint8 *rom, uint32 offset) 159 { 160 uint16 init1 = rom[offset + 18] + (rom[offset + 19] * 256); 161 uint16 init2 = rom[offset + 20] + (rom[offset + 21] * 256); 162 uint16 init_size = rom[offset + 22] + (rom[offset + 23] * 256) + 1; 163 /* confirmed on a TNT2-M64 with pins V5.1 */ 164 uint16 ram_tab = rom[offset + 24] + (rom[offset + 25] * 256); 165 /* fixme: PPC BIOSes (might) return NULL pointers for messages here */ 166 char* signon_msg = &(rom[(rom[offset + 30] + (rom[offset + 31] * 256))]); 167 char* vendor_name = &(rom[(rom[offset + 46] + (rom[offset + 47] * 256))]); 168 char* product_name = &(rom[(rom[offset + 48] + (rom[offset + 49] * 256))]); 169 char* product_rev = &(rom[(rom[offset + 50] + (rom[offset + 51] * 256))]); 170 171 LOG(8,("INFO: pre PINS 5.16 cmdlist 1: $%04x, 2: $%04x, max. size $%04x\n", init1, init2, init_size)); 172 LOG(8,("INFO: signon msg:\n%s\n", signon_msg)); 173 LOG(8,("INFO: vendor name: %s\n", vendor_name)); 174 LOG(8,("INFO: product name: %s\n", product_name)); 175 LOG(8,("INFO: product rev: %s\n", product_rev)); 176 177 /* pins 5.06 and higher has VCO range info */ 178 if (((rom[offset + 5]) == 5) && ((rom[offset + 6]) >= 0x06)) 179 { 180 /* get PLL VCO range info */ 181 uint32 fvco_max = *((uint32*)(&(rom[offset + 67]))); 182 uint32 fvco_min = *((uint32*)(&(rom[offset + 71]))); 183 184 LOG(8,("INFO: PLL VCO range is %dkHz - %dkHz\n", fvco_min, fvco_max)); 185 186 /* modify presets to reflect card capability */ 187 si->ps.min_system_vco = fvco_min / 1000; 188 si->ps.max_system_vco = fvco_max / 1000; 189 //fixme: enable and modify PLL code... 190 //si->ps.min_pixel_vco = fvco_min / 1000; 191 //si->ps.max_pixel_vco = fvco_max / 1000; 192 //si->ps.min_video_vco = fvco_min / 1000; 193 //si->ps.max_video_vco = fvco_max / 1000; 194 } 195 196 //fixme: add 'parsing scripts while not actually executing' as warmstart method, 197 // instead of not parsing at all: this will update the driver's speeds 198 // as below, while logging the scripts as well (for our learning pleasure :) 199 200 /* pins 5.16 and higher is more extensive, and works differently from before */ 201 if (((rom[offset + 5]) == 5) && ((rom[offset + 6]) >= 0x10)) 202 { 203 /* pins 5.16 and up have a more extensive command list table, and have more 204 * commands to choose from as well. */ 205 PinsTables tabs; 206 tabs.InitScriptTablePtr = rom[offset + 75] + (rom[offset + 76] * 256); 207 tabs.MacroIndexTablePtr = rom[offset + 77] + (rom[offset + 78] * 256); 208 tabs.MacroTablePtr = rom[offset + 79] + (rom[offset + 80] * 256); 209 tabs.ConditionTablePtr = rom[offset + 81] + (rom[offset + 82] * 256); 210 tabs.IOConditionTablePtr = rom[offset + 83] + (rom[offset + 84] * 256); 211 tabs.IOFlagConditionTablePtr = rom[offset + 85] + (rom[offset + 86] * 256); 212 tabs.InitFunctionTablePtr = rom[offset + 87] + (rom[offset + 88] * 256); 213 214 LOG(8,("INFO: PINS 5.16 and later cmdlist pointers:\n")); 215 LOG(8,("INFO: InitScriptTablePtr: $%04x\n", tabs.InitScriptTablePtr)); 216 LOG(8,("INFO: MacroIndexTablePtr: $%04x\n", tabs.MacroIndexTablePtr)); 217 LOG(8,("INFO: MacroTablePtr: $%04x\n", tabs.MacroTablePtr)); 218 LOG(8,("INFO: ConditionTablePtr: $%04x\n", tabs.ConditionTablePtr)); 219 LOG(8,("INFO: IOConditionTablePtr: $%04x\n", tabs.IOConditionTablePtr)); 220 LOG(8,("INFO: IOFlagConditionTablePtr: $%04x\n", tabs.IOFlagConditionTablePtr)); 221 LOG(8,("INFO: InitFunctionTablePtr: $%04x\n", tabs.InitFunctionTablePtr)); 222 223 return coldstart_card_516_up(rom, tabs, ram_tab); 224 } 225 else 226 { 227 /* pre 'pins 5.16' still uses the 'old' method in which the command list 228 * table always has two entries. */ 229 return coldstart_card(rom, init1, init2, init_size, ram_tab); 230 } 231 } 232 233 static status_t coldstart_card(uint8* rom, uint16 init1, uint16 init2, uint16 init_size, uint16 ram_tab) 234 { 235 status_t result = B_OK; 236 int16 size = init_size; 237 238 LOG(8,("INFO: now executing coldstart...\n")); 239 240 /* select colormode CRTC registers base adresses */ 241 NV_REG8(NV8_MISCW) = 0xcb; 242 243 /* unknown.. */ 244 NV_REG8(NV8_VSE2) = 0x01; 245 246 /* enable access to primary head */ 247 set_crtc_owner(0); 248 /* unlock head's registers for R/W access */ 249 CRTCW(LOCK, 0x57); 250 CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); 251 /* disable RMA as it's not used */ 252 /* (RMA is the cmd register for the 32bit port in the GPU to access 32bit registers 253 * and framebuffer via legacy ISA I/O space.) */ 254 CRTCW(RMA, 0x00); 255 256 if (si->ps.secondary_head) 257 { 258 /* enable access to secondary head */ 259 set_crtc_owner(1); 260 /* unlock head's registers for R/W access */ 261 CRTC2W(LOCK, 0x57); 262 CRTC2W(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); 263 } 264 265 /* turn off both displays and the hardcursors (also disables transfers) */ 266 nv_crtc_dpms(false, false, false, true); 267 nv_crtc_cursor_hide(); 268 if (si->ps.secondary_head) 269 { 270 nv_crtc2_dpms(false, false, false, true); 271 nv_crtc2_cursor_hide(); 272 } 273 274 /* execute BIOS coldstart script(s) */ 275 if (init1 || init2) 276 { 277 if (init1) 278 if (exec_type1_script(rom, init1, &size, ram_tab) != B_OK) result = B_ERROR; 279 if (init2 && (result == B_OK)) 280 if (exec_type1_script(rom, init2, &size, ram_tab) != B_OK) result = B_ERROR; 281 282 /* now enable ROM shadow or the card will remain shut-off! */ 283 CFGW(ROMSHADOW, (CFGR(ROMSHADOW) |= 0x00000001)); 284 285 //temporary: should be called from setmode probably.. 286 nv_crtc_setup_fifo(); 287 } 288 else 289 { 290 result = B_ERROR; 291 } 292 293 if (result != B_OK) 294 LOG(8,("INFO: coldstart failed.\n")); 295 else 296 LOG(8,("INFO: coldstart execution completed OK.\n")); 297 298 return result; 299 } 300 301 static status_t coldstart_card_516_up(uint8* rom, PinsTables tabs, uint16 ram_tab) 302 { 303 status_t result = B_OK; 304 uint16 adress; 305 uint32 fb_mrs1 = 0; 306 uint32 fb_mrs2 = 0; 307 308 LOG(8,("INFO: now executing coldstart...\n")); 309 310 /* get some strapinfo(?) for NV28 framebuffer access */ 311 //fixme?: works on at least one NV28... how about other cards? 312 if (si->ps.card_type == NV28) 313 { 314 fb_mrs2 = NV_REG32(NV32_FB_MRS2); 315 fb_mrs1 = NV_REG32(NV32_FB_MRS1); 316 } 317 318 /* select colormode CRTC registers base adresses */ 319 NV_REG8(NV8_MISCW) = 0xcb; 320 321 /* unknown.. */ 322 NV_REG8(NV8_VSE2) = 0x01; 323 324 /* enable access to primary head */ 325 set_crtc_owner(0); 326 /* unlock head's registers for R/W access */ 327 CRTCW(LOCK, 0x57); 328 CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); 329 /* disable RMA as it's not used */ 330 /* (RMA is the cmd register for the 32bit port in the GPU to access 32bit registers 331 * and framebuffer via legacy ISA I/O space.) */ 332 CRTCW(RMA, 0x00); 333 334 if (si->ps.secondary_head) 335 { 336 /* enable access to secondary head */ 337 set_crtc_owner(1); 338 /* unlock head's registers for R/W access */ 339 CRTC2W(LOCK, 0x57); 340 CRTC2W(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); 341 } 342 343 /* turn off both displays and the hardcursors (also disables transfers) */ 344 nv_crtc_dpms(false, false, false, true); 345 nv_crtc_cursor_hide(); 346 if (si->ps.secondary_head) 347 { 348 nv_crtc2_dpms(false, false, false, true); 349 nv_crtc2_cursor_hide(); 350 } 351 352 /* execute all BIOS coldstart script(s) */ 353 if (tabs.InitScriptTablePtr) 354 { 355 /* size is nolonger used, keeping it anyway for testing purposes :) */ 356 int16 size = 32767; 357 uint16 index = tabs.InitScriptTablePtr; 358 359 adress = *((uint16*)(&(rom[index]))); 360 if (!adress) 361 { 362 LOG(8,("INFO: no cmdlist found!\n")); 363 result = B_ERROR; 364 } 365 366 while (adress && (result == B_OK)) 367 { 368 result = exec_type2_script(rom, adress, &size, tabs, ram_tab); 369 /* next command script, please */ 370 index += 2; 371 adress = *((uint16*)(&(rom[index]))); 372 } 373 374 /* do some NV28 specific extra stuff */ 375 //fixme: NV28 only?? 376 if (si->ps.card_type == NV28) 377 { 378 /* setup PTIMER */ 379 ACCW(PT_NUMERATOR, (si->ps.std_engine_clock * 20)); 380 ACCW(PT_DENOMINATR, 0x00000271); 381 382 /* get NV28 RAM access up and running */ 383 //fixme?: works on at least one NV28... how about other cards? 384 NV_REG32(NV32_FB_MRS2) = fb_mrs2; 385 NV_REG32(NV32_FB_MRS1) = fb_mrs1; 386 } 387 388 /* now enable ROM shadow or the card will remain shut-off! */ 389 CFGW(ROMSHADOW, (CFGR(ROMSHADOW) |= 0x00000001)); 390 391 //temporary: should be called from setmode probably.. 392 nv_crtc_setup_fifo(); 393 } 394 else 395 { 396 result = B_ERROR; 397 } 398 399 if (result != B_OK) 400 LOG(8,("INFO: coldstart failed.\n")); 401 else 402 LOG(8,("INFO: coldstart execution completed OK.\n")); 403 404 return result; 405 } 406 407 /* This routine is complete, and is used for pre-NV10 cards. It's tested on a Elsa 408 * Erazor III with TNT2 (NV05) and on two no-name TNT2-M64's. All cards coldstart 409 * perfectly. */ 410 static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 ram_tab) 411 { 412 status_t result = B_OK; 413 bool end = false; 414 bool exec = true; 415 uint8 index, byte; 416 uint32 reg, data, data2, and_out, or_in; 417 418 LOG(8,("\nINFO: executing type1 script at adress $%04x...\n", adress)); 419 LOG(8,("INFO: ---Executing following command(s):\n")); 420 421 while (!end) 422 { 423 LOG(8,("INFO: $%04x ($%02x); ", adress, rom[adress])); 424 425 switch (rom[adress]) 426 { 427 case 0x59: 428 *size -= 7; 429 if (*size < 0) 430 { 431 LOG(8,("script size error, aborting!\n\n")); 432 end = true; 433 result = B_ERROR; 434 break; 435 } 436 437 /* execute */ 438 adress += 1; 439 reg = *((uint32*)(&(rom[adress]))); 440 adress += 4; 441 data = *((uint16*)(&(rom[adress]))); 442 adress += 2; 443 data2 = *((uint16*)(&(rom[data]))); 444 LOG(8,("cmd 'calculate indirect and set PLL 32bit reg $%08x for %.3fMHz'\n", 445 reg, ((float)data2))); 446 if (exec) 447 { 448 float calced_clk; 449 uint8 m, n, p; 450 nv_dac_sys_pll_find(((float)data2), &calced_clk, &m, &n, &p, 0); 451 NV_REG32(reg) = ((p << 16) | (n << 8) | m); 452 } 453 log_pll(reg, data2); 454 break; 455 case 0x5a: 456 *size -= 7; 457 if (*size < 0) 458 { 459 LOG(8,("script size error, aborting!\n\n")); 460 end = true; 461 result = B_ERROR; 462 break; 463 } 464 465 /* execute */ 466 adress += 1; 467 reg = *((uint32*)(&(rom[adress]))); 468 adress += 4; 469 data = *((uint16*)(&(rom[adress]))); 470 adress += 2; 471 data2 = *((uint32*)(&(rom[data]))); 472 LOG(8,("cmd 'WR indirect 32bit reg' $%08x = $%08x\n", reg, data2)); 473 if (exec) NV_REG32(reg) = data2; 474 break; 475 case 0x63: 476 *size -= 1; 477 if (*size < 0) 478 { 479 LOG(8,("script size error, aborting!\n\n")); 480 end = true; 481 result = B_ERROR; 482 break; 483 } 484 485 /* execute */ 486 adress += 1; 487 LOG(8,("cmd 'setup RAM config' (always done)\n")); 488 /* always done */ 489 setup_ram_config(rom, ram_tab); 490 break; 491 case 0x65: 492 *size -= 13; 493 if (*size < 0) 494 { 495 LOG(8,("script size error, aborting!\n\n")); 496 end = true; 497 result = B_ERROR; 498 break; 499 } 500 501 /* execute */ 502 adress += 1; 503 reg = *((uint32*)(&(rom[adress]))); 504 adress += 4; 505 data = *((uint32*)(&(rom[adress]))); 506 adress += 4; 507 data2 = *((uint32*)(&(rom[adress]))); 508 adress += 4; 509 LOG(8,("cmd 'WR 32bit reg $%08x = $%08x, then = $%08x' (always done)\n", 510 reg, data, data2)); 511 /* always done */ 512 NV_REG32(reg) = data; 513 NV_REG32(reg) = data2; 514 CFGW(ROMSHADOW, (CFGR(ROMSHADOW) & 0xfffffffe)); 515 break; 516 case 0x69: 517 *size -= 5; 518 if (*size < 0) 519 { 520 LOG(8,("script size error, aborting!\n\n")); 521 end = true; 522 result = B_ERROR; 523 break; 524 } 525 526 /* execute */ 527 adress += 1; 528 reg = *((uint16*)(&(rom[adress]))); 529 adress += 2; 530 and_out = *((uint8*)(&(rom[adress]))); 531 adress += 1; 532 or_in = *((uint8*)(&(rom[adress]))); 533 adress += 1; 534 LOG(8,("cmd 'RD 8bit ISA reg $%04x, AND-out = $%02x, OR-in = $%02x, WR-bk'\n", 535 reg, and_out, or_in)); 536 if (exec) 537 { 538 translate_ISA_PCI(®); 539 byte = NV_REG8(reg); 540 byte &= (uint8)and_out; 541 byte |= (uint8)or_in; 542 NV_REG8(reg) = byte; 543 } 544 break; 545 case 0x6d: 546 *size -= 3; 547 if (*size < 0) 548 { 549 LOG(8,("script size error, aborting!\n\n")); 550 end = true; 551 result = B_ERROR; 552 break; 553 } 554 555 /* execute */ 556 adress += 1; 557 data = NV_REG32(NV32_NV4STRAPINFO); 558 and_out = *((uint8*)(&(rom[adress]))); 559 adress += 1; 560 byte = *((uint8*)(&(rom[adress]))); 561 adress += 1; 562 data &= (uint32)and_out; 563 LOG(8,("cmd 'CHK bits AND-out $%02x RAMCFG for $%02x'\n", 564 and_out, byte)); 565 if (((uint8)data) != byte) 566 { 567 LOG(8,("INFO: ---No match: not executing following command(s):\n")); 568 exec = false; 569 } 570 else 571 { 572 LOG(8,("INFO: ---Match, so this cmd has no effect.\n")); 573 } 574 break; 575 case 0x6e: 576 *size -= 13; 577 if (*size < 0) 578 { 579 LOG(8,("script size error, aborting!\n\n")); 580 end = true; 581 result = B_ERROR; 582 break; 583 } 584 585 /* execute */ 586 adress += 1; 587 reg = *((uint32*)(&(rom[adress]))); 588 adress += 4; 589 and_out = *((uint32*)(&(rom[adress]))); 590 adress += 4; 591 or_in = *((uint32*)(&(rom[adress]))); 592 adress += 4; 593 LOG(8,("cmd 'RD 32bit reg $%08x, AND-out = $%08x, OR-in = $%08x, WR-bk'\n", 594 reg, and_out, or_in)); 595 if (exec) 596 { 597 data = NV_REG32(reg); 598 data &= and_out; 599 data |= or_in; 600 NV_REG32(reg) = data; 601 } 602 break; 603 case 0x71: 604 LOG(8,("cmd 'END', execution completed.\n\n")); 605 end = true; 606 607 *size -= 1; 608 if (*size < 0) 609 { 610 LOG(8,("script size error!\n\n")); 611 result = B_ERROR; 612 } 613 break; 614 case 0x72: 615 *size -= 1; 616 if (*size < 0) 617 { 618 LOG(8,("script size error!\n\n")); 619 result = B_ERROR; 620 } 621 622 /* execute */ 623 adress += 1; 624 LOG(8,("cmd 'PGM commands'\n")); 625 LOG(8,("INFO: ---Executing following command(s):\n")); 626 exec = true; 627 break; 628 case 0x73: 629 *size -= 9; 630 if (*size < 0) 631 { 632 LOG(8,("script size error, aborting!\n\n")); 633 end = true; 634 result = B_ERROR; 635 break; 636 } 637 638 /* execute */ 639 adress += 1; 640 data = NV_REG32(NV32_NVSTRAPINFO2); 641 and_out = *((uint32*)(&(rom[adress]))); 642 adress += 4; 643 data2 = *((uint32*)(&(rom[adress]))); 644 adress += 4; 645 data &= and_out; 646 LOG(8,("cmd 'CHK bits AND-out $%08x STRAPCFG2 for $%08x'\n", 647 and_out, data2)); 648 if (data != data2) 649 { 650 LOG(8,("INFO: ---No match: not executing following command(s):\n")); 651 exec = false; 652 } 653 else 654 { 655 LOG(8,("INFO: ---Match, so this cmd has no effect.\n")); 656 } 657 break; 658 case 0x74: 659 *size -= 3; 660 if (*size < 0) 661 { 662 LOG(8,("script size error, aborting!\n\n")); 663 end = true; 664 result = B_ERROR; 665 break; 666 } 667 668 /* execute */ 669 adress += 1; 670 data = *((uint16*)(&(rom[adress]))); 671 adress += 2; 672 LOG(8,("cmd 'SNOOZE for %d ($%04x) microSeconds' (always done)\n", data, data)); 673 /* always done */ 674 snooze(data); 675 break; 676 case 0x77: 677 *size -= 7; 678 if (*size < 0) 679 { 680 LOG(8,("script size error, aborting!\n\n")); 681 end = true; 682 result = B_ERROR; 683 break; 684 } 685 686 /* execute */ 687 adress += 1; 688 reg = *((uint32*)(&(rom[adress]))); 689 adress += 4; 690 data = *((uint16*)(&(rom[adress]))); 691 adress += 2; 692 LOG(8,("cmd 'WR 32bit reg' $%08x = $%08x (b31-16 = '0', b15-0 = data)\n", 693 reg, data)); 694 if (exec) NV_REG32(reg) = data; 695 break; 696 case 0x78: 697 *size -= 6; 698 if (*size < 0) 699 { 700 LOG(8,("script size error, aborting!\n\n")); 701 end = true; 702 result = B_ERROR; 703 break; 704 } 705 706 /* execute */ 707 adress += 1; 708 reg = *((uint16*)(&(rom[adress]))); 709 adress += 2; 710 index = *((uint8*)(&(rom[adress]))); 711 adress += 1; 712 and_out = *((uint8*)(&(rom[adress]))); 713 adress += 1; 714 or_in = *((uint8*)(&(rom[adress]))); 715 adress += 1; 716 LOG(8,("cmd 'RD idx ISA reg $%02x via $%04x, AND-out = $%02x, OR-in = $%02x, WR-bk'\n", 717 index, reg, and_out, or_in)); 718 if (exec) 719 { 720 translate_ISA_PCI(®); 721 NV_REG8(reg) = index; 722 byte = NV_REG8(reg + 1); 723 byte &= (uint8)and_out; 724 byte |= (uint8)or_in; 725 NV_REG8(reg + 1) = byte; 726 } 727 break; 728 case 0x79: 729 *size -= 7; 730 if (*size < 0) 731 { 732 LOG(8,("script size error, aborting!\n\n")); 733 end = true; 734 result = B_ERROR; 735 break; 736 } 737 738 /* execute */ 739 adress += 1; 740 reg = *((uint32*)(&(rom[adress]))); 741 adress += 4; 742 data = *((uint16*)(&(rom[adress]))); 743 adress += 2; 744 LOG(8,("cmd 'calculate and set PLL 32bit reg $%08x for %.3fMHz'\n", reg, (data / 100.0))); 745 if (exec) 746 { 747 float calced_clk; 748 uint8 m, n, p; 749 nv_dac_sys_pll_find((data / 100.0), &calced_clk, &m, &n, &p, 0); 750 NV_REG32(reg) = ((p << 16) | (n << 8) | m); 751 } 752 log_pll(reg, (data / 100)); 753 break; 754 case 0x7a: 755 *size -= 9; 756 if (*size < 0) 757 { 758 LOG(8,("script size error, aborting!\n\n")); 759 end = true; 760 result = B_ERROR; 761 break; 762 } 763 764 /* execute */ 765 adress += 1; 766 reg = *((uint32*)(&(rom[adress]))); 767 adress += 4; 768 data = *((uint32*)(&(rom[adress]))); 769 adress += 4; 770 LOG(8,("cmd 'WR 32bit reg' $%08x = $%08x\n", reg, data)); 771 if (exec) NV_REG32(reg) = data; 772 break; 773 default: 774 LOG(8,("unknown cmd, aborting!\n\n")); 775 end = true; 776 result = B_ERROR; 777 break; 778 } 779 } 780 781 return result; 782 } 783 784 static void log_pll(uint32 reg, uint32 freq) 785 { 786 if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) 787 LOG(8,("INFO: ---WARNING: check/update PLL programming script code!!!\n")); 788 switch (reg) 789 { 790 case NV32_MEMPLL: 791 LOG(8,("INFO: ---Memory PLL accessed.\n")); 792 /* update the card's specs */ 793 si->ps.std_memory_clock = freq; 794 break; 795 case NV32_COREPLL: 796 LOG(8,("INFO: ---Core PLL accessed.\n")); 797 /* update the card's specs */ 798 si->ps.std_engine_clock = freq; 799 break; 800 case NVDAC_PIXPLLC: 801 LOG(8,("INFO: ---DAC1 PLL accessed.\n")); 802 break; 803 case NVDAC2_PIXPLLC: 804 LOG(8,("INFO: ---DAC2 PLL accessed.\n")); 805 break; 806 /* unexpected cases, here for learning goals... */ 807 case NV32_MEMPLL2: 808 LOG(8,("INFO: ---NV31/NV36 extension to memory PLL accessed only!\n")); 809 break; 810 case NV32_COREPLL2: 811 LOG(8,("INFO: ---NV31/NV36 extension to core PLL accessed only!\n")); 812 break; 813 case NVDAC_PIXPLLC2: 814 LOG(8,("INFO: ---NV31/NV36 extension to DAC1 PLL accessed only!\n")); 815 break; 816 case NVDAC2_PIXPLLC2: 817 LOG(8,("INFO: ---NV31/NV36 extension to DAC2 PLL accessed only!\n")); 818 break; 819 default: 820 LOG(8,("INFO: ---Unknown PLL accessed!\n")); 821 break; 822 } 823 } 824 825 static void setup_ram_config(uint8* rom, uint16 ram_tab) 826 { 827 uint32 ram_cfg, data; 828 uint8 cnt; 829 830 /* set MRS = 256 */ 831 NV_REG32(NV32_PFB_DEBUG_0) &= 0xffffffef; 832 /* read RAM config hardware(?) strap */ 833 ram_cfg = ((NV_REG32(NV32_NVSTRAPINFO2) >> 2) & 0x0000000f); 834 LOG(8,("INFO: ---RAM config strap is $%01x\n", ram_cfg)); 835 /* use it as a pointer in a BIOS table for prerecorded RAM configurations */ 836 ram_cfg = *((uint16*)(&(rom[(ram_tab + (ram_cfg * 2))]))); 837 /* log info */ 838 switch (ram_cfg & 0x00000003) 839 { 840 case 0: 841 LOG(8,("INFO: ---32Mb RAM should be connected\n")); 842 break; 843 case 1: 844 LOG(8,("INFO: ---4Mb RAM should be connected\n")); 845 break; 846 case 2: 847 LOG(8,("INFO: ---8Mb RAM should be connected\n")); 848 break; 849 case 3: 850 LOG(8,("INFO: ---16Mb RAM should be connected\n")); 851 break; 852 } 853 if (ram_cfg & 0x00000004) 854 LOG(8,("INFO: ---RAM should be 128bits wide\n")); 855 else 856 LOG(8,("INFO: ---RAM should be 64bits wide\n")); 857 switch ((ram_cfg & 0x00000038) >> 3) 858 { 859 case 0: 860 LOG(8,("INFO: ---RAM type: 8Mbit SGRAM\n")); 861 break; 862 case 1: 863 LOG(8,("INFO: ---RAM type: 16Mbit SGRAM\n")); 864 break; 865 case 2: 866 LOG(8,("INFO: ---RAM type: 4 banks of 16Mbit SGRAM\n")); 867 break; 868 case 3: 869 LOG(8,("INFO: ---RAM type: 16Mbit SDRAM\n")); 870 break; 871 case 4: 872 LOG(8,("INFO: ---RAM type: 64Mbit SDRAM\n")); 873 break; 874 case 5: 875 LOG(8,("INFO: ---RAM type: 64Mbit x16 SDRAM\n")); 876 break; 877 } 878 /* set RAM amount, width and type */ 879 data = (NV_REG32(NV32_NV4STRAPINFO) & 0xffffffc0); 880 NV_REG32(NV32_NV4STRAPINFO) = (data | (ram_cfg & 0x0000003f)); 881 /* setup write to read delay (?) */ 882 data = (NV_REG32(NV32_PFB_CONFIG_1) & 0xff8ffffe); 883 data |= ((ram_cfg & 0x00000700) << 12); 884 /* force update via b0 = 0... */ 885 NV_REG32(NV32_PFB_CONFIG_1) = data; 886 /* ... followed by b0 = 1(?) */ 887 NV_REG32(NV32_PFB_CONFIG_1) = (data | 0x00000001); 888 889 /* do RAM width test to confirm RAM width set to be correct */ 890 /* write testpattern to first 128 bits of graphics memory... */ 891 data = 0x4e563541; 892 for (cnt = 0; cnt < 4; cnt++) 893 ((volatile uint32 *)si->framebuffer)[cnt] = data; 894 /* ... if second 64 bits does not contain the testpattern we are apparantly 895 * set to 128bits width while we should be set to 64bits width, so correct. */ 896 if (((volatile uint32 *)si->framebuffer)[3] != data) 897 { 898 LOG(8,("INFO: ---RAM width tested: width is 64bits, correcting settings.\n")); 899 NV_REG32(NV32_NV4STRAPINFO) &= ~0x00000004; 900 } 901 else 902 { 903 LOG(8,("INFO: ---RAM width tested: access is OK.\n")); 904 } 905 906 /* do RAM size test to confirm RAM size set to be correct */ 907 ram_cfg = (NV_REG32(NV32_NV4STRAPINFO) & 0x00000003); 908 data = 0x4e563542; 909 /* first check for 32Mb... */ 910 if (!ram_cfg) 911 { 912 /* write testpattern to just above the 16Mb boundary */ 913 ((volatile uint32 *)si->framebuffer)[(16 * 1024 * 1024) >> 2] = data; 914 /* check if pattern reads back */ 915 if (((volatile uint32 *)si->framebuffer)[(16 * 1024 * 1024) >> 2] == data) 916 { 917 /* write second testpattern to base adress */ 918 data = 0x4135564e; 919 ((volatile uint32 *)si->framebuffer)[0] = data; 920 if (((volatile uint32 *)si->framebuffer)[0] == data) 921 { 922 LOG(8,("INFO: ---RAM size tested: size was set OK (32Mb).\n")); 923 return; 924 } 925 } 926 /* one of the two tests for 32Mb failed, we must have 16Mb */ 927 ram_cfg = 0x00000003; 928 LOG(8,("INFO: ---RAM size tested: size is 16Mb, correcting settings.\n")); 929 NV_REG32(NV32_NV4STRAPINFO) = 930 (((NV_REG32(NV32_NV4STRAPINFO)) & 0xfffffffc) | ram_cfg); 931 return; 932 } 933 /* ... now check for 16Mb... */ 934 if (ram_cfg == 0x00000003) 935 { 936 /* increment testpattern */ 937 data++; 938 /* write testpattern to just above the 8Mb boundary */ 939 ((volatile uint32 *)si->framebuffer)[(8 * 1024 * 1024) >> 2] = data; 940 /* check if pattern reads back */ 941 if (((volatile uint32 *)si->framebuffer)[(8 * 1024 * 1024) >> 2] == data) 942 { 943 LOG(8,("INFO: ---RAM size tested: size was set OK (16Mb).\n")); 944 return; 945 } 946 else 947 { 948 /* assuming 8Mb: retesting below! */ 949 ram_cfg = 0x00000002; 950 LOG(8,("INFO: ---RAM size tested: size is NOT 16Mb, testing for 8Mb...\n")); 951 NV_REG32(NV32_NV4STRAPINFO) = 952 (((NV_REG32(NV32_NV4STRAPINFO)) & 0xfffffffc) | ram_cfg); 953 } 954 } 955 /* ... and now check for 8Mb! (ram_cfg will be 'pre'set to 4Mb or 8Mb here) */ 956 { 957 /* increment testpattern (again) */ 958 data++; 959 /* write testpattern to just above the 4Mb boundary */ 960 ((volatile uint32 *)si->framebuffer)[(4 * 1024 * 1024) >> 2] = data; 961 /* check if pattern reads back */ 962 if (((volatile uint32 *)si->framebuffer)[(4 * 1024 * 1024) >> 2] == data) 963 { 964 /* we have 8Mb, make sure this is set. */ 965 ram_cfg = 0x00000002; 966 LOG(8,("INFO: ---RAM size tested: size is 8Mb, setting 8Mb.\n")); 967 /* fixme? assuming this should be done here! */ 968 NV_REG32(NV32_NV4STRAPINFO) = 969 (((NV_REG32(NV32_NV4STRAPINFO)) & 0xfffffffc) | ram_cfg); 970 return; 971 } 972 else 973 { 974 /* we must have 4Mb, make sure this is set. */ 975 ram_cfg = 0x00000001; 976 LOG(8,("INFO: ---RAM size tested: size is 4Mb, setting 4Mb.\n")); 977 NV_REG32(NV32_NV4STRAPINFO) = 978 (((NV_REG32(NV32_NV4STRAPINFO)) & 0xfffffffc) | ram_cfg); 979 return; 980 } 981 } 982 } 983 984 /* this routine is used for NV10 and later */ 985 static status_t exec_type2_script(uint8* rom, uint16 adress, int16* size, PinsTables tabs, uint16 ram_tab) 986 { 987 bool exec = true; 988 989 LOG(8,("\nINFO: executing type2 script at adress $%04x...\n", adress)); 990 LOG(8,("INFO: ---Executing following command(s):\n")); 991 992 return exec_type2_script_mode(rom, &adress, size, tabs, ram_tab, &exec); 993 } 994 995 /* this routine is used for NV10 and later. It's tested on a GeForce2 MX400 (NV11), 996 * GeForce4 MX440 (NV18), GeForce4 Ti4200 (NV28) and a GeForceFX 5200 (NV34). 997 * These cards coldstart perfectly. */ 998 static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, PinsTables tabs, uint16 ram_tab, bool* exec) 999 { 1000 status_t result = B_OK; 1001 bool end = false; 1002 uint8 index, byte, byte2, shift; 1003 uint32 reg, reg2, data, data2, and_out, and_out2, or_in, or_in2, safe32, offset32, size32; 1004 1005 while (!end) 1006 { 1007 LOG(8,("INFO: $%04x ($%02x); ", *adress, rom[*adress])); 1008 1009 /* all commands are here (verified NV11 and NV28) */ 1010 switch (rom[*adress]) 1011 { 1012 case 0x31: /* new */ 1013 *size -= (15 + ((*((uint8*)(&(rom[(*adress + 10)])))) << 2)); 1014 if (*size < 0) 1015 { 1016 LOG(8,("script size error, aborting!\n\n")); 1017 end = true; 1018 result = B_ERROR; 1019 break; 1020 } 1021 1022 /* execute */ 1023 *adress += 1; 1024 reg = *((uint32*)(&(rom[*adress]))); 1025 *adress += 4; 1026 and_out = *((uint32*)(&(rom[*adress]))); 1027 *adress += 4; 1028 shift = *((uint8*)(&(rom[*adress]))); 1029 *adress += 1; 1030 size32 = ((*((uint8*)(&(rom[*adress])))) << 2); 1031 *adress += 1; 1032 reg2 = *((uint32*)(&(rom[*adress]))); 1033 *adress += 4; 1034 LOG(8,("cmd 'RD 32bit reg $%08x, AND-out = $%08x, shift-right = $%02x,\n", 1035 reg, and_out, shift)); 1036 LOG(8,("INFO: (cont.) RD 32bit data from subtable with size $%04x, at offset (result << 2),\n", 1037 size32)); 1038 LOG(8,("INFO: (cont.) then WR result data to 32bit reg $%08x'\n", reg2)); 1039 if (*exec && reg2) 1040 { 1041 data = NV_REG32(reg); 1042 data &= and_out; 1043 data >>= shift; 1044 data2 = *((uint32*)(&(rom[(*adress + (data << 2))]))); 1045 NV_REG32(reg2) = data2; 1046 } 1047 *adress += size32; 1048 break; 1049 case 0x32: /* new */ 1050 *size -= (11 + ((*((uint8*)(&(rom[(*adress + 6)])))) << 2)); 1051 if (*size < 0) 1052 { 1053 LOG(8,("script size error, aborting!\n\n")); 1054 end = true; 1055 result = B_ERROR; 1056 break; 1057 } 1058 1059 /* execute */ 1060 *adress += 1; 1061 reg = *((uint16*)(&(rom[*adress]))); 1062 *adress += 2; 1063 index = *((uint8*)(&(rom[*adress]))); 1064 *adress += 1; 1065 and_out = *((uint8*)(&(rom[*adress]))); 1066 *adress += 1; 1067 byte2 = *((uint8*)(&(rom[*adress]))); 1068 *adress += 1; 1069 size32 = ((*((uint8*)(&(rom[*adress])))) << 2); 1070 *adress += 1; 1071 reg2 = *((uint32*)(&(rom[*adress]))); 1072 *adress += 4; 1073 LOG(8,("cmd 'RD idx ISA reg $%02x via $%04x, AND-out = $%02x, shift-right = $%02x,\n", 1074 index, reg, and_out, byte2)); 1075 LOG(8,("INFO: (cont.) RD 32bit data from subtable with size $%04x, at offset (result << 2),\n", 1076 size32)); 1077 LOG(8,("INFO: (cont.) then WR result data to 32bit reg $%08x'\n", reg2)); 1078 if (*exec && reg2) 1079 { 1080 translate_ISA_PCI(®); 1081 NV_REG8(reg) = index; 1082 byte = NV_REG8(reg + 1); 1083 byte &= (uint8)and_out; 1084 byte >>= byte2; 1085 offset32 = (byte << 2); 1086 data = *((uint32*)(&(rom[(*adress + offset32)]))); 1087 NV_REG32(reg2) = data; 1088 } 1089 *adress += size32; 1090 break; 1091 case 0x33: /* new */ 1092 *size -= 2; 1093 if (*size < 0) 1094 { 1095 LOG(8,("script size error, aborting!\n\n")); 1096 end = true; 1097 result = B_ERROR; 1098 break; 1099 } 1100 1101 /* execute */ 1102 *adress += 1; 1103 size32 = *((uint8*)(&(rom[*adress]))); 1104 *adress += 1; 1105 /* executed 1-256 times */ 1106 if (!size32) size32 = 256; 1107 /* remember where to start each time */ 1108 safe32 = *adress; 1109 LOG(8,("cmd 'execute following part of this script $%03x times' (always done)\n", size32)); 1110 for (offset32 = 0; offset32 < size32; offset32++) 1111 { 1112 LOG(8,("\nINFO: (#$%02x) executing part of type2 script at adress $%04x...\n", 1113 offset32, *adress)); 1114 LOG(8,("INFO: ---Not touching 'execution' mode at this time:\n")); 1115 *adress = safe32; 1116 result = exec_type2_script_mode(rom, adress, size, tabs, ram_tab, exec); 1117 } 1118 LOG(8,("INFO: ---Continuing script:\n")); 1119 break; 1120 case 0x34: /* new */ 1121 *size -= (12 + ((*((uint8*)(&(rom[(*adress + 7)])))) << 1)); 1122 if (*size < 0) 1123 { 1124 LOG(8,("script size error, aborting!\n\n")); 1125 end = true; 1126 result = B_ERROR; 1127 break; 1128 } 1129 1130 /* execute */ 1131 *adress += 1; 1132 reg = *((uint16*)(&(rom[*adress]))); 1133 *adress += 2; 1134 index = *((uint8*)(&(rom[*adress]))); 1135 *adress += 1; 1136 and_out = *((uint8*)(&(rom[*adress]))); 1137 *adress += 1; 1138 shift = *((uint8*)(&(rom[*adress]))); 1139 *adress += 1; 1140 offset32 = *((uint8*)(&(rom[*adress]))); 1141 *adress += 1; 1142 size32 = ((*((uint8*)(&(rom[*adress])))) << 1); 1143 *adress += 1; 1144 reg2 = *((uint32*)(&(rom[*adress]))); 1145 *adress += 4; 1146 LOG(8,("cmd 'RD idx ISA reg $%02x via $%04x, AND-out = $%02x, shift-right = $%02x,\n", 1147 index, reg, and_out, shift)); 1148 LOG(8,("INFO: (cont.) RD 16bit PLL frequency to pgm from subtable with size $%04x, at offset (result << 1),\n", 1149 size32)); 1150 LOG(8,("INFO: (cont.) RD table-index ($%02x) for cmd $39'\n", 1151 offset32)); 1152 translate_ISA_PCI(®); 1153 NV_REG8(reg) = index; 1154 byte = NV_REG8(reg + 1); 1155 byte &= (uint8)and_out; 1156 data = (byte >> shift); 1157 data <<= 1; 1158 data2 = *((uint16*)(&(rom[(*adress + data)]))); 1159 if (offset32 < 0x80) 1160 { 1161 bool double_f = true; 1162 LOG(8,("INFO: Do subcmd ($39); ")); 1163 exec_cmd_39_type2(rom, offset32, tabs, &double_f); 1164 LOG(8,("INFO: (cont. cmd $34) Doubling PLL frequency to be set for cmd $34.\n")); 1165 if (double_f) data2 <<= 1; 1166 LOG(8,("INFO: ---Reverting to pre-subcmd ($39) 'execution' mode.\n")); 1167 } 1168 else 1169 { 1170 LOG(8,("INFO: table index is negative, not executing subcmd ($39).\n")); 1171 } 1172 LOG(8,("INFO: (cont.) 'calc and set PLL 32bit reg $%08x for %.3fMHz'\n", 1173 reg2, (data2 / 100.0))); 1174 if (*exec && reg2) 1175 { 1176 float calced_clk; 1177 uint8 m, n, p; 1178 nv_dac_sys_pll_find((data2 / 100.0), &calced_clk, &m, &n, &p, 0); 1179 /* programming the PLL needs to be done in steps! (confirmed NV28) */ 1180 data = NV_REG32(reg2); 1181 NV_REG32(reg2) = ((data & 0xffff0000) | (n << 8) | m); 1182 data = NV_REG32(reg2); 1183 NV_REG32(reg2) = ((p << 16) | (n << 8) | m); 1184 //fixme? 1185 /* program 2nd set N and M scalers if they exist (b31=1 enables them) */ 1186 // if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) 1187 // DACW(PIXPLLC2, 0x80000401); 1188 } 1189 log_pll(reg2, (data2 / 100)); 1190 *adress += size32; 1191 break; 1192 case 0x35: /* new */ 1193 *size -= 2; 1194 if (*size < 0) 1195 { 1196 LOG(8,("script size error, aborting!\n\n")); 1197 end = true; 1198 result = B_ERROR; 1199 break; 1200 } 1201 1202 /* execute */ 1203 *adress += 1; 1204 byte = *((uint8*)(&(rom[*adress]))); 1205 *adress += 1; 1206 offset32 = (byte << 1); 1207 offset32 += tabs.InitFunctionTablePtr; 1208 LOG(8,("cmd 'execute fixed VGA BIOS routine #$%02x at adress $%04x'\n", 1209 byte, offset32)); 1210 /* note: 1211 * This command is BIOS/'pins' version specific. Confirmed a NV28 having NO 1212 * entries at all in InitFunctionTable! 1213 * (BIOS version 4.28.20.05.11; 'pins' version 5.21) */ 1214 //fixme: impl. if it turns out this cmd is used.. (didn't see that yet) 1215 if (*exec) 1216 { 1217 //fixme: add BIOS/'pins' version dependancy... 1218 switch(byte) 1219 { 1220 default: 1221 LOG(8,("\n\nINFO: WARNING: function not implemented, skipping!\n\n")); 1222 break; 1223 } 1224 } 1225 break; 1226 case 0x37: /* new */ 1227 *size -= 11; 1228 if (*size < 0) 1229 { 1230 LOG(8,("script size error, aborting!\n\n")); 1231 end = true; 1232 result = B_ERROR; 1233 break; 1234 } 1235 1236 /* execute */ 1237 *adress += 1; 1238 reg = *((uint32*)(&(rom[*adress]))); 1239 *adress += 4; 1240 byte2 = *((uint8*)(&(rom[*adress]))); 1241 *adress += 1; 1242 and_out = *((uint8*)(&(rom[*adress]))); 1243 *adress += 1; 1244 reg2 = *((uint16*)(&(rom[*adress]))); 1245 *adress += 2; 1246 index = *((uint8*)(&(rom[*adress]))); 1247 *adress += 1; 1248 and_out2 = *((uint8*)(&(rom[*adress]))); 1249 *adress += 1; 1250 LOG(8,("cmd 'RD 32bit reg $%08x, shift-right = $%02x, AND-out lsb = $%02x,\n", 1251 reg, byte2, and_out)); 1252 LOG(8,("INFO: (cont.) RD 8bit ISA reg $%02x via $%04x, AND-out = $%02x, OR-in lsb result 32bit, WR-bk'\n", 1253 index, reg2, and_out2)); 1254 if (*exec) 1255 { 1256 data = NV_REG32(reg); 1257 if (byte2 < 0x80) 1258 { 1259 data >>= byte2; 1260 } 1261 else 1262 { 1263 data <<= (0x0100 - byte2); 1264 } 1265 data &= and_out; 1266 translate_ISA_PCI(®2); 1267 NV_REG8(reg2) = index; 1268 byte = NV_REG8(reg2 + 1); 1269 byte &= (uint8)and_out2; 1270 byte |= (uint8)data; 1271 NV_REG8(reg2 + 1) = byte; 1272 } 1273 break; 1274 case 0x38: /* new */ 1275 *size -= 1; 1276 if (*size < 0) 1277 { 1278 LOG(8,("script size error, aborting!\n\n")); 1279 end = true; 1280 result = B_ERROR; 1281 break; 1282 } 1283 1284 /* execute */ 1285 *adress += 1; 1286 LOG(8,("cmd 'invert current mode'\n")); 1287 *exec = !(*exec); 1288 if (*exec) 1289 LOG(8,("INFO: ---Executing following command(s):\n")); 1290 else 1291 LOG(8,("INFO: ---Not executing following command(s):\n")); 1292 break; 1293 case 0x39: /* new */ 1294 *size -= 2; 1295 if (*size < 0) 1296 { 1297 LOG(8,("script size error, aborting!\n\n")); 1298 end = true; 1299 result = B_ERROR; 1300 break; 1301 } 1302 1303 /* execute */ 1304 *adress += 1; 1305 data = *((uint8*)(&(rom[*adress]))); 1306 *adress += 1; 1307 exec_cmd_39_type2(rom, data, tabs, exec); 1308 break; 1309 case 0x49: /* new */ 1310 size32 = *((uint8*)(&(rom[*adress + 17]))); 1311 if (!size32) size32 = 256; 1312 *size -= (18 + (size32 << 1)); 1313 if (*size < 0) 1314 { 1315 LOG(8,("script size error, aborting!\n\n")); 1316 end = true; 1317 result = B_ERROR; 1318 break; 1319 } 1320 1321 /* execute */ 1322 *adress += 1; 1323 reg = *((uint32*)(&(rom[*adress]))); 1324 *adress += 4; 1325 reg2 = *((uint32*)(&(rom[*adress]))); 1326 *adress += 4; 1327 and_out = *((uint32*)(&(rom[*adress]))); 1328 *adress += 4; 1329 or_in = *((uint32*)(&(rom[*adress]))); 1330 *adress += 4; 1331 size32 = *((uint8*)(&(rom[*adress]))); 1332 if (!size32) size32 = 256; 1333 *adress += 1; 1334 LOG(8,("cmd 'do following cmd structure $%03x time(s)':\n", size32)); 1335 for (offset32 = 0; offset32 < size32; offset32++) 1336 { 1337 or_in2 = *((uint8*)(&(rom[(*adress + (offset32 << 1))]))); 1338 data2 = *((uint8*)(&(rom[(*adress + (offset32 << 1) + 1)]))); 1339 LOG(8,("INFO (cont.) (#$%02x) cmd 'WR 32bit reg $%08x = $%08x, RD 32bit reg $%08x,\n", 1340 offset32, reg2, data2, reg)); 1341 LOG(8,("INFO (cont.) AND-out $%08x, OR-in $%08x, OR-in $%08x, WR-bk'\n", 1342 and_out, or_in, or_in2)); 1343 } 1344 if (*exec) 1345 { 1346 for (index = 0; index < size32; index++) 1347 { 1348 or_in2 = *((uint8*)(&(rom[*adress]))); 1349 *adress += 1; 1350 data2 = *((uint8*)(&(rom[*adress]))); 1351 *adress += 1; 1352 NV_REG32(reg2) = data2; 1353 data = NV_REG32(reg); 1354 data &= and_out; 1355 data |= or_in; 1356 data |= or_in2; 1357 NV_REG32(reg) = data; 1358 } 1359 } 1360 else 1361 { 1362 *adress += (size32 << 1); 1363 } 1364 break; 1365 case 0x61: /* new */ 1366 *size -= 4; 1367 if (*size < 0) 1368 { 1369 LOG(8,("script size error, aborting!\n\n")); 1370 end = true; 1371 result = B_ERROR; 1372 break; 1373 } 1374 1375 /* execute */ 1376 *adress += 1; 1377 reg = *((uint16*)(&(rom[*adress]))); 1378 *adress += 2; 1379 byte = *((uint8*)(&(rom[*adress]))); 1380 *adress += 1; 1381 LOG(8,("cmd 'WR ISA reg $%04x = $%02x'\n", reg, byte)); 1382 if (*exec) 1383 { 1384 translate_ISA_PCI(®); 1385 NV_REG8(reg) = byte; 1386 } 1387 break; 1388 case 0x62: /* new */ 1389 *size -= 5; 1390 if (*size < 0) 1391 { 1392 LOG(8,("script size error, aborting!\n\n")); 1393 end = true; 1394 result = B_ERROR; 1395 break; 1396 } 1397 1398 /* execute */ 1399 *adress += 1; 1400 reg = *((uint16*)(&(rom[*adress]))); 1401 *adress += 2; 1402 index = *((uint8*)(&(rom[*adress]))); 1403 *adress += 1; 1404 byte = *((uint8*)(&(rom[*adress]))); 1405 *adress += 1; 1406 LOG(8,("cmd 'WR idx ISA reg $%02x via $%04x = $%02x'\n", index, reg, byte)); 1407 if (*exec) 1408 { 1409 translate_ISA_PCI(®); 1410 NV_REG16(reg) = ((((uint16)byte) << 8) | index); 1411 } 1412 break; 1413 case 0x63: /* new setup compared to pre-NV10 version */ 1414 *size -= 1; 1415 if (*size < 0) 1416 { 1417 LOG(8,("script size error, aborting!\n\n")); 1418 end = true; 1419 result = B_ERROR; 1420 break; 1421 } 1422 1423 /* execute */ 1424 *adress += 1; 1425 LOG(8,("cmd 'setup RAM config' (always done)\n")); 1426 /* always done */ 1427 switch (si->ps.card_type) 1428 { 1429 case NV28: 1430 setup_ram_config_nv28(rom); 1431 break; 1432 default: 1433 setup_ram_config_nv10_up(rom); 1434 break; 1435 } 1436 break; 1437 case 0x65: /* identical to type1 */ 1438 *size -= 13; 1439 if (*size < 0) 1440 { 1441 LOG(8,("script size error, aborting!\n\n")); 1442 end = true; 1443 result = B_ERROR; 1444 break; 1445 } 1446 1447 /* execute */ 1448 *adress += 1; 1449 reg = *((uint32*)(&(rom[*adress]))); 1450 *adress += 4; 1451 data = *((uint32*)(&(rom[*adress]))); 1452 *adress += 4; 1453 data2 = *((uint32*)(&(rom[*adress]))); 1454 *adress += 4; 1455 LOG(8,("cmd 'WR 32bit reg $%08x = $%08x, then = $%08x' (always done)\n", 1456 reg, data, data2)); 1457 /* always done */ 1458 NV_REG32(reg) = data; 1459 NV_REG32(reg) = data2; 1460 CFGW(ROMSHADOW, (CFGR(ROMSHADOW) & 0xfffffffe)); 1461 break; 1462 case 0x69: /* identical to type1 */ 1463 *size -= 5; 1464 if (*size < 0) 1465 { 1466 LOG(8,("script size error, aborting!\n\n")); 1467 end = true; 1468 result = B_ERROR; 1469 break; 1470 } 1471 1472 /* execute */ 1473 *adress += 1; 1474 reg = *((uint16*)(&(rom[*adress]))); 1475 *adress += 2; 1476 and_out = *((uint8*)(&(rom[*adress]))); 1477 *adress += 1; 1478 or_in = *((uint8*)(&(rom[*adress]))); 1479 *adress += 1; 1480 LOG(8,("cmd 'RD 8bit ISA reg $%04x, AND-out = $%02x, OR-in = $%02x, WR-bk'\n", 1481 reg, and_out, or_in)); 1482 if (*exec) 1483 { 1484 translate_ISA_PCI(®); 1485 byte = NV_REG8(reg); 1486 byte &= (uint8)and_out; 1487 byte |= (uint8)or_in; 1488 NV_REG8(reg) = byte; 1489 } 1490 break; 1491 case 0x6a: /* new */ 1492 *size -= 2; 1493 if (*size < 0) 1494 { 1495 LOG(8,("script size error, aborting!\n\n")); 1496 end = true; 1497 result = B_ERROR; 1498 break; 1499 } 1500 1501 /* execute */ 1502 *adress += 1; 1503 data = *((uint8*)(&(rom[*adress]))); 1504 *adress += 1; 1505 data2 = *((uint16*)(&(rom[(tabs.InitScriptTablePtr + (data << 1))]))); 1506 LOG(8,("cmd 'jump to script #$%02x at adress $%04x'\n", data, data2)); 1507 if (*exec) 1508 { 1509 *adress = data2; 1510 LOG(8,("INFO: ---Jumping; not touching 'execution' mode.\n")); 1511 } 1512 break; 1513 case 0x6b: /* new */ 1514 *size -= 2; 1515 if (*size < 0) 1516 { 1517 LOG(8,("script size error, aborting!\n\n")); 1518 end = true; 1519 result = B_ERROR; 1520 break; 1521 } 1522 1523 /* execute */ 1524 *adress += 1; 1525 data = *((uint8*)(&(rom[*adress]))); 1526 *adress += 1; 1527 data2 = *((uint16*)(&(rom[(tabs.InitScriptTablePtr + (data << 1))]))); 1528 LOG(8,("cmd 'gosub script #$%02x at adress $%04x'\n", data, data2)); 1529 if (*exec && data2) 1530 { 1531 result = exec_type2_script(rom, data2, size, tabs, ram_tab); 1532 LOG(8,("INFO: ---Reverting to pre-gosub 'execution' mode.\n")); 1533 } 1534 break; 1535 case 0x6e: /* identical to type1 */ 1536 *size -= 13; 1537 if (*size < 0) 1538 { 1539 LOG(8,("script size error, aborting!\n\n")); 1540 end = true; 1541 result = B_ERROR; 1542 break; 1543 } 1544 1545 /* execute */ 1546 *adress += 1; 1547 reg = *((uint32*)(&(rom[*adress]))); 1548 *adress += 4; 1549 and_out = *((uint32*)(&(rom[*adress]))); 1550 *adress += 4; 1551 or_in = *((uint32*)(&(rom[*adress]))); 1552 *adress += 4; 1553 LOG(8,("cmd 'RD 32bit reg $%08x, AND-out = $%08x, OR-in = $%08x, WR-bk'\n", 1554 reg, and_out, or_in)); 1555 if (*exec) 1556 { 1557 data = NV_REG32(reg); 1558 data &= and_out; 1559 data |= or_in; 1560 NV_REG32(reg) = data; 1561 } 1562 break; 1563 case 0x6f: /* new */ 1564 *size -= 2; 1565 if (*size < 0) 1566 { 1567 LOG(8,("script size error, aborting!\n\n")); 1568 end = true; 1569 result = B_ERROR; 1570 break; 1571 } 1572 1573 /* execute */ 1574 *adress += 1; 1575 byte = *((uint8*)(&(rom[*adress]))); 1576 *adress += 1; 1577 data = tabs.MacroIndexTablePtr + (byte << 1); 1578 offset32 = (*((uint8*)(&(rom[data]))) << 3); 1579 size32 = *((uint8*)(&(rom[(data + 1)]))); 1580 offset32 += tabs.MacroTablePtr; 1581 /* note: min 1, max 255 commands can be requested */ 1582 LOG(8,("cmd 'do $%02x time(s) a 32bit reg WR with 32bit data' (MacroIndexTable idx = $%02x):\n", 1583 size32, byte)); 1584 safe32 = 0; 1585 while (safe32 < size32) 1586 { 1587 reg2 = *((uint32*)(&(rom[(offset32 + (safe32 << 3))]))); 1588 data2 = *((uint32*)(&(rom[(offset32 + (safe32 << 3) + 4)]))); 1589 LOG(8,("INFO: (cont.) (#$%02x) cmd 'WR 32bit reg' $%08x = $%08x\n", 1590 safe32, reg2, data2)); 1591 safe32++; 1592 } 1593 if (*exec) 1594 { 1595 safe32 = 0; 1596 while (safe32 < size32) 1597 { 1598 reg2 = *((uint32*)(&(rom[(offset32 + (safe32 << 3))]))); 1599 data2 = *((uint32*)(&(rom[(offset32 + (safe32 << 3) + 4)]))); 1600 NV_REG32(reg2) = data2; 1601 safe32++; 1602 } 1603 } 1604 break; 1605 case 0x36: /* new */ 1606 case 0x66: /* new */ 1607 case 0x67: /* new */ 1608 case 0x68: /* new */ 1609 case 0x6c: /* new */ 1610 case 0x71: /* identical to type1 */ 1611 LOG(8,("cmd 'END', execution completed.\n\n")); 1612 end = true; 1613 1614 *size -= 1; 1615 if (*size < 0) 1616 { 1617 LOG(8,("script size error!\n\n")); 1618 result = B_ERROR; 1619 } 1620 1621 /* execute */ 1622 *adress += 1; /* needed to make cmd #$33 work correctly! */ 1623 break; 1624 case 0x72: /* identical to type1 */ 1625 *size -= 1; 1626 if (*size < 0) 1627 { 1628 LOG(8,("script size error!\n\n")); 1629 result = B_ERROR; 1630 } 1631 1632 /* execute */ 1633 *adress += 1; 1634 LOG(8,("cmd 'PGM commands'\n")); 1635 LOG(8,("INFO: ---Executing following command(s):\n")); 1636 *exec = true; 1637 break; 1638 case 0x74: /* identical to type1 */ 1639 //fixme? on at least NV28 this cmd hammers the CRTC PCI-timeout register 1640 //'data' number of times instead of snoozing. 1641 //Couldn't see any diff in behaviour though! 1642 *size -= 3; 1643 if (*size < 0) 1644 { 1645 LOG(8,("script size error, aborting!\n\n")); 1646 end = true; 1647 result = B_ERROR; 1648 break; 1649 } 1650 1651 /* execute */ 1652 *adress += 1; 1653 data = *((uint16*)(&(rom[*adress]))); 1654 *adress += 2; 1655 LOG(8,("cmd 'SNOOZE for %d ($%04x) microSeconds' (always done)\n", data, data)); 1656 /* always done */ 1657 snooze(data); 1658 break; 1659 case 0x75: /* new */ 1660 *size -= 2; 1661 if (*size < 0) 1662 { 1663 LOG(8,("script size error!\n\n")); 1664 result = B_ERROR; 1665 } 1666 1667 /* execute */ 1668 *adress += 1; 1669 data = *((uint8*)(&(rom[*adress]))); 1670 *adress += 1; 1671 data *= 12; 1672 data += tabs.ConditionTablePtr; 1673 reg = *((uint32*)(&(rom[data]))); 1674 and_out = *((uint32*)(&(rom[(data + 4)]))); 1675 data2 = *((uint32*)(&(rom[(data + 8)]))); 1676 data = NV_REG32(reg); 1677 data &= and_out; 1678 LOG(8,("cmd 'CHK bits AND-out $%08x reg $%08x for $%08x'\n", 1679 and_out, reg, data2)); 1680 if (data != data2) 1681 { 1682 LOG(8,("INFO: ---No match: not executing following command(s):\n")); 1683 *exec = false; 1684 } 1685 else 1686 { 1687 LOG(8,("INFO: ---Match, so this cmd has no effect.\n")); 1688 } 1689 break; 1690 case 0x76: /* new */ 1691 *size -= 2; 1692 if (*size < 0) 1693 { 1694 LOG(8,("script size error!\n\n")); 1695 result = B_ERROR; 1696 } 1697 1698 /* execute */ 1699 *adress += 1; 1700 data = *((uint8*)(&(rom[*adress]))); 1701 *adress += 1; 1702 data *= 5; 1703 data += tabs.IOConditionTablePtr; 1704 reg = *((uint16*)(&(rom[data]))); 1705 index = *((uint8*)(&(rom[(data + 2)]))); 1706 and_out = *((uint8*)(&(rom[(data + 3)]))); 1707 byte2 = *((uint8*)(&(rom[(data + 4)]))); 1708 LOG(8,("cmd 'CHK bits AND-out $%02x idx ISA reg $%02x via $%04x for $%02x'\n", 1709 and_out, index, reg, byte2)); 1710 translate_ISA_PCI(®); 1711 NV_REG8(reg) = index; 1712 byte = NV_REG8(reg + 1); 1713 byte &= (uint8)and_out; 1714 if (byte != byte2) 1715 { 1716 LOG(8,("INFO: ---No match: not executing following command(s):\n")); 1717 *exec = false; 1718 } 1719 else 1720 { 1721 LOG(8,("INFO: ---Match, so this cmd has no effect.\n")); 1722 } 1723 break; 1724 case 0x78: /* identical to type1 */ 1725 *size -= 6; 1726 if (*size < 0) 1727 { 1728 LOG(8,("script size error, aborting!\n\n")); 1729 end = true; 1730 result = B_ERROR; 1731 break; 1732 } 1733 1734 /* execute */ 1735 *adress += 1; 1736 reg = *((uint16*)(&(rom[*adress]))); 1737 *adress += 2; 1738 index = *((uint8*)(&(rom[*adress]))); 1739 *adress += 1; 1740 and_out = *((uint8*)(&(rom[*adress]))); 1741 *adress += 1; 1742 or_in = *((uint8*)(&(rom[*adress]))); 1743 *adress += 1; 1744 LOG(8,("cmd 'RD idx ISA reg $%02x via $%04x, AND-out = $%02x, OR-in = $%02x, WR-bk'\n", 1745 index, reg, and_out, or_in)); 1746 if (*exec) 1747 { 1748 translate_ISA_PCI(®); 1749 NV_REG8(reg) = index; 1750 byte = NV_REG8(reg + 1); 1751 byte &= (uint8)and_out; 1752 byte |= (uint8)or_in; 1753 NV_REG8(reg + 1) = byte; 1754 } 1755 break; 1756 case 0x79: 1757 *size -= 7; 1758 if (*size < 0) 1759 { 1760 LOG(8,("script size error, aborting!\n\n")); 1761 end = true; 1762 result = B_ERROR; 1763 break; 1764 } 1765 1766 /* execute */ 1767 *adress += 1; 1768 reg = *((uint32*)(&(rom[*adress]))); 1769 *adress += 4; 1770 data = *((uint16*)(&(rom[*adress]))); 1771 *adress += 2; 1772 LOG(8,("cmd 'calculate and set PLL 32bit reg $%08x for %.3fMHz'\n", reg, (data / 100.0))); 1773 if (*exec) 1774 { 1775 float calced_clk; 1776 uint8 m, n, p; 1777 nv_dac_sys_pll_find((data / 100.0), &calced_clk, &m, &n, &p, 0); 1778 /* programming the PLL needs to be done in steps! (confirmed NV28) */ 1779 data2 = NV_REG32(reg); 1780 NV_REG32(reg) = ((data2 & 0xffff0000) | (n << 8) | m); 1781 data2 = NV_REG32(reg); 1782 NV_REG32(reg) = ((p << 16) | (n << 8) | m); 1783 //fixme? 1784 /* program 2nd set N and M scalers if they exist (b31=1 enables them) */ 1785 // if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) 1786 // DACW(PIXPLLC2, 0x80000401); 1787 } 1788 log_pll(reg, (data / 100)); 1789 break; 1790 case 0x7a: /* identical to type1 */ 1791 *size -= 9; 1792 if (*size < 0) 1793 { 1794 LOG(8,("script size error, aborting!\n\n")); 1795 end = true; 1796 result = B_ERROR; 1797 break; 1798 } 1799 1800 /* execute */ 1801 *adress += 1; 1802 reg = *((uint32*)(&(rom[*adress]))); 1803 *adress += 4; 1804 data = *((uint32*)(&(rom[*adress]))); 1805 *adress += 4; 1806 LOG(8,("cmd 'WR 32bit reg' $%08x = $%08x\n", reg, data)); 1807 if (*exec) NV_REG32(reg) = data; 1808 break; 1809 default: 1810 LOG(8,("unknown cmd, aborting!\n\n")); 1811 end = true; 1812 result = B_ERROR; 1813 break; 1814 } 1815 } 1816 1817 return result; 1818 } 1819 1820 static void exec_cmd_39_type2(uint8* rom, uint32 data, PinsTables tabs, bool* exec) 1821 { 1822 uint8 index, byte, byte2, safe, shift; 1823 uint32 reg, and_out, and_out2, offset32; 1824 1825 data *= 9; 1826 data += tabs.IOFlagConditionTablePtr; 1827 reg = *((uint16*)(&(rom[data]))); 1828 index = *((uint8*)(&(rom[(data + 2)]))); 1829 and_out = *((uint8*)(&(rom[(data + 3)]))); 1830 shift = *((uint8*)(&(rom[(data + 4)]))); 1831 offset32 = *((uint16*)(&(rom[data + 5]))); 1832 and_out2 = *((uint8*)(&(rom[(data + 7)]))); 1833 byte2 = *((uint8*)(&(rom[(data + 8)]))); 1834 LOG(8,("cmd 'AND-out bits $%02x idx ISA reg $%02x via $%04x, shift-right = $%02x,\n", 1835 and_out, index, reg, shift)); 1836 translate_ISA_PCI(®); 1837 NV_REG8(reg) = index; 1838 byte = NV_REG8(reg + 1); 1839 byte &= (uint8)and_out; 1840 offset32 += (byte >> shift); 1841 safe = byte = *((uint8*)(&(rom[offset32]))); 1842 byte &= (uint8)and_out2; 1843 LOG(8,("INFO: (cont.) use result as index in table to get data $%02x,\n", 1844 safe)); 1845 LOG(8,("INFO: (cont.) then chk bits AND-out $%02x of data for $%02x'\n", 1846 and_out2, byte2)); 1847 if (byte != byte2) 1848 { 1849 LOG(8,("INFO: ---No match: not executing following command(s):\n")); 1850 *exec = false; 1851 } 1852 else 1853 { 1854 LOG(8,("INFO: ---Match, so this cmd has no effect.\n")); 1855 } 1856 } 1857 1858 static void setup_ram_config_nv10_up(uint8* rom) 1859 { 1860 /* note: 1861 * After writing data to RAM a snooze is required to make the test work. 1862 * Confirmed a NV11: without snooze it worked OK on a low-voltage AGP2.0 slot, 1863 * but on a higher-voltage AGP 1.0 slot it failed to identify errors correctly!! 1864 * Adding the snooze fixed that. */ 1865 1866 uint32 data, dummy; 1867 uint8 cnt = 0; 1868 status_t stat = B_ERROR; 1869 1870 /* set 'refctrl is valid' */ 1871 NV_REG32(NV32_PFB_REFCTRL) = 0x80000000; 1872 1873 /* check RAM for 256bits buswidth(?) */ 1874 while ((cnt < 4) && (stat != B_OK)) 1875 { 1876 /* reset RAM bits at offset 224-255 bits four times */ 1877 ((volatile uint32 *)si->framebuffer)[0x07] = 0x00000000; 1878 snooze(10); 1879 ((volatile uint32 *)si->framebuffer)[0x07] = 0x00000000; 1880 snooze(10); 1881 ((volatile uint32 *)si->framebuffer)[0x07] = 0x00000000; 1882 snooze(10); 1883 ((volatile uint32 *)si->framebuffer)[0x07] = 0x00000000; 1884 snooze(10); 1885 /* write testpattern */ 1886 ((volatile uint32 *)si->framebuffer)[0x07] = 0x4e563131; 1887 snooze(10); 1888 /* reset RAM bits at offset 480-511 bits */ 1889 ((volatile uint32 *)si->framebuffer)[0x0f] = 0x00000000; 1890 snooze(10); 1891 /* check testpattern to have survived */ 1892 if (((volatile uint32 *)si->framebuffer)[0x07] == 0x4e563131) stat = B_OK; 1893 cnt++; 1894 } 1895 1896 /* if pattern did not hold modify RAM-type setup */ 1897 if (stat != B_OK) 1898 { 1899 LOG(8,("INFO: ---RAM test #1 done: access errors, modified setup.\n")); 1900 data = NV_REG32(NV32_PFB_CONFIG_0); 1901 if (data & 0x00000010) 1902 { 1903 data &= 0xffffffcf; 1904 } 1905 else 1906 { 1907 data &= 0xffffffcf; 1908 data |= 0x00000020; 1909 } 1910 NV_REG32(NV32_PFB_CONFIG_0) = data; 1911 } 1912 else 1913 { 1914 LOG(8,("INFO: ---RAM test #1 done: access is OK.\n")); 1915 } 1916 1917 /* check RAM bankswitching stuff(?) */ 1918 cnt = 0; 1919 stat = B_ERROR; 1920 while ((cnt < 4) && (stat != B_OK)) 1921 { 1922 /* read RAM size */ 1923 data = NV_REG32(NV32_NV10STRAPINFO); 1924 /* subtract 1MB */ 1925 data -= 0x00100000; 1926 /* write testpattern at generated RAM adress */ 1927 ((volatile uint32 *)si->framebuffer)[(data >> 2)] = 0x4e564441; 1928 snooze(10); 1929 /* reset first RAM adress */ 1930 ((volatile uint32 *)si->framebuffer)[0x00] = 0x00000000; 1931 snooze(10); 1932 /* dummyread first RAM adress four times */ 1933 dummy = ((volatile uint32 *)si->framebuffer)[0x00]; 1934 dummy = ((volatile uint32 *)si->framebuffer)[0x00]; 1935 dummy = ((volatile uint32 *)si->framebuffer)[0x00]; 1936 dummy = ((volatile uint32 *)si->framebuffer)[0x00]; 1937 /* check testpattern to have survived */ 1938 if (((volatile uint32 *)si->framebuffer)[(data >> 2)] == 0x4e564441) stat = B_OK; 1939 cnt++; 1940 } 1941 1942 /* if pattern did not hold modify RAM-type setup */ 1943 if (stat != B_OK) 1944 { 1945 LOG(8,("INFO: ---RAM test #2 done: access errors, modified setup.\n")); 1946 NV_REG32(NV32_PFB_CONFIG_0) &= 0xffffefff; 1947 } 1948 else 1949 { 1950 LOG(8,("INFO: ---RAM test #2 done: access is OK.\n")); 1951 } 1952 } 1953 1954 /* Note: this routine assumes at least 128Mb was mapped to memory (kerneldriver). 1955 * It doesn't matter if the card actually _has_ this amount of RAM or not(!) */ 1956 static void setup_ram_config_nv28(uint8* rom) 1957 { 1958 /* note: 1959 * After writing data to RAM a snooze is required to make the test work. 1960 * Confirmed a NV11: without snooze it worked OK on a low-voltage AGP2.0 slot, 1961 * but on a higher-voltage AGP 1.0 slot it failed to identify errors correctly!! 1962 * Adding the snooze fixed that. */ 1963 1964 uint32 dummy; 1965 uint8 cnt = 0; 1966 status_t stat = B_ERROR; 1967 1968 /* set 'refctrl is valid' */ 1969 NV_REG32(NV32_PFB_REFCTRL) = 0x80000000; 1970 1971 /* check RAM */ 1972 while ((cnt < 4) && (stat != B_OK)) 1973 { 1974 /* set bit 11: 'pulse' something into a new setting? */ 1975 NV_REG32(NV32_PFB_CONFIG_0) |= 0x00000800; 1976 /* write testpattern to RAM adress 127Mb */ 1977 ((volatile uint32 *)si->framebuffer)[0x01fc0000] = 0x4e564441; 1978 snooze(10); 1979 /* reset first RAM adress */ 1980 ((volatile uint32 *)si->framebuffer)[0x00000000] = 0x00000000; 1981 snooze(10); 1982 /* dummyread first RAM adress four times */ 1983 dummy = ((volatile uint32 *)si->framebuffer)[0x00000000]; 1984 LOG(8,("INFO: (#%d) dummy1 = $%08x, ", cnt, dummy)); 1985 dummy = ((volatile uint32 *)si->framebuffer)[0x00000000]; 1986 LOG(8,("dummy2 = $%08x, ", dummy)); 1987 dummy = ((volatile uint32 *)si->framebuffer)[0x00000000]; 1988 LOG(8,("dummy3 = $%08x, ", dummy)); 1989 dummy = ((volatile uint32 *)si->framebuffer)[0x00000000]; 1990 LOG(8,("dummy4 = $%08x\n", dummy)); 1991 /* check testpattern to have survived */ 1992 if (((volatile uint32 *)si->framebuffer)[0x01fc0000] == 0x4e564441) stat = B_OK; 1993 cnt++; 1994 } 1995 1996 /* clear bit 11: set normal mode */ 1997 NV_REG32(NV32_PFB_CONFIG_0) &= ~0x00000800; 1998 1999 if (stat == B_OK) 2000 LOG(8,("INFO: ---RAM test done: access was OK within %d iteration(s).\n", cnt)); 2001 else 2002 LOG(8,("INFO: ---RAM test done: access was still not OK after 4 iterations.\n")); 2003 } 2004 2005 static status_t translate_ISA_PCI(uint32* reg) 2006 { 2007 switch (*reg) 2008 { 2009 case 0x03c0: 2010 *reg = NV8_ATTRDATW; 2011 break; 2012 case 0x03c1: 2013 *reg = NV8_ATTRDATR; 2014 break; 2015 case 0x03c2: 2016 *reg = NV8_MISCW; 2017 break; 2018 case 0x03c4: 2019 *reg = NV8_SEQIND; 2020 break; 2021 case 0x03c5: 2022 *reg = NV8_SEQDAT; 2023 break; 2024 case 0x03c6: 2025 *reg = NV8_PALMASK; 2026 break; 2027 case 0x03c7: 2028 *reg = NV8_PALINDR; 2029 break; 2030 case 0x03c8: 2031 *reg = NV8_PALINDW; 2032 break; 2033 case 0x03c9: 2034 *reg = NV8_PALDATA; 2035 break; 2036 case 0x03cc: 2037 *reg = NV8_MISCR; 2038 break; 2039 case 0x03ce: 2040 *reg = NV8_GRPHIND; 2041 break; 2042 case 0x03cf: 2043 *reg = NV8_GRPHDAT; 2044 break; 2045 case 0x03d4: 2046 *reg = NV8_CRTCIND; 2047 break; 2048 case 0x03d5: 2049 *reg = NV8_CRTCDAT; 2050 break; 2051 case 0x03da: 2052 *reg = NV8_INSTAT1; 2053 break; 2054 default: 2055 LOG(8,("\n\nINFO: WARNING: ISA->PCI register adress translation failed!\n\n")); 2056 return B_ERROR; 2057 break; 2058 } 2059 2060 return B_OK; 2061 } 2062 2063 void set_pll(uint32 reg, uint32 req_clk) 2064 { 2065 uint32 data; 2066 float calced_clk; 2067 uint8 m, n, p; 2068 nv_dac_sys_pll_find(req_clk, &calced_clk, &m, &n, &p, 0); 2069 /* programming the PLL needs to be done in steps! (confirmed NV28) */ 2070 data = NV_REG32(reg); 2071 NV_REG32(reg) = ((data & 0xffff0000) | (n << 8) | m); 2072 data = NV_REG32(reg); 2073 NV_REG32(reg) = ((p << 16) | (n << 8) | m); 2074 2075 //fixme? 2076 /* program 2nd set N and M scalers if they exist (b31=1 enables them) */ 2077 if (si->ps.ext_pll) 2078 { 2079 if (reg == NV32_COREPLL) NV_REG32(NV32_COREPLL2) = 0x80000401; 2080 if (reg == NV32_MEMPLL) NV_REG32(NV32_MEMPLL2) = 0x80000401; 2081 } 2082 2083 log_pll(reg, req_clk); 2084 } 2085 2086 /* doing general fail-safe default setup here */ 2087 static status_t nv_crtc_setup_fifo() 2088 { 2089 /* enable access to primary head */ 2090 set_crtc_owner(0); 2091 2092 /* set CRTC FIFO burst size to 256 */ 2093 CRTCW(FIFO, 0x03); 2094 2095 /* set CRTC FIFO low watermark to 32 */ 2096 CRTCW(FIFO_LWM, 0x20); 2097 2098 return B_OK; 2099 } 2100 2101 /* (pre)set 'fixed' card specifications */ 2102 void set_specs(void) 2103 { 2104 LOG(8,("INFO: setting up card specifications\n")); 2105 2106 /* set failsave speeds */ 2107 switch (si->ps.card_type) 2108 { 2109 case NV04: 2110 pinsnv4_fake(); 2111 break; 2112 case NV05: 2113 case NV05M64: 2114 pinsnv5_nv5m64_fake(); 2115 break; 2116 case NV06: 2117 pinsnv6_fake(); 2118 break; 2119 default: 2120 switch (si->ps.card_arch) 2121 { 2122 case NV10A: 2123 pinsnv10_arch_fake(); 2124 break; 2125 case NV20A: 2126 pinsnv20_arch_fake(); 2127 break; 2128 case NV30A: 2129 case NV40A: 2130 pinsnv30_arch_fake(); 2131 break; 2132 default: 2133 /* 'failsafe' values... */ 2134 pinsnv10_arch_fake(); 2135 break; 2136 } 2137 break; 2138 } 2139 2140 /* detect reference crystal frequency and dualhead */ 2141 switch (si->ps.card_arch) 2142 { 2143 case NV04A: 2144 getstrap_arch_nv4(); 2145 break; 2146 default: 2147 getstrap_arch_nv10_20_30_40(); 2148 break; 2149 } 2150 } 2151 2152 /* this routine presumes the card was coldstarted by the card's BIOS for panel stuff */ 2153 void fake_panel_start(void) 2154 { 2155 LOG(8,("INFO: detecting RAM size\n")); 2156 2157 /* detect RAM amount */ 2158 switch (si->ps.card_arch) 2159 { 2160 case NV04A: 2161 getRAMsize_arch_nv4(); 2162 break; 2163 default: 2164 getRAMsize_arch_nv10_20_30_40(); 2165 break; 2166 } 2167 2168 /* override memory detection if requested by user */ 2169 if (si->settings.memory != 0) 2170 { 2171 LOG(2,("INFO: forcing memory size (specified in settings file)\n")); 2172 si->ps.memory_size = si->settings.memory * 1024 * 1024; 2173 } 2174 2175 /* find out if the card has a tvout chip */ 2176 si->ps.tvout = false; 2177 si->ps.tv_encoder.type = NONE; 2178 si->ps.tv_encoder.version = 0; 2179 /* I2C init currently also fetches DDC EDID info from all connected screens */ 2180 i2c_init(); 2181 //fixme: add support for more encoders... 2182 BT_probe(); 2183 2184 LOG(8,("INFO: faking panel startup\n")); 2185 2186 /* find out the BIOS preprogrammed panel use status... */ 2187 detect_panels(); 2188 2189 /* determine and setup output devices and heads */ 2190 setup_output_matrix(); 2191 2192 /* select other CRTC for primary head use if specified by user in settings file */ 2193 if (si->ps.secondary_head && si->settings.switchhead) 2194 { 2195 LOG(2,("INFO: inverting head use (specified in nvidia.settings file)\n")); 2196 si->ps.crtc2_prim = !si->ps.crtc2_prim; 2197 } 2198 } 2199 2200 /* notes: 2201 * - Since laptops don't have edid for their internal panels, and we can't switch 2202 * digitally connected external panels to DAC's, we keep needing the info fetched 2203 * from card programming done by the cardBIOS. 2204 * - Because we can only output modes on digitally connected panels upto/including 2205 * the modeline programmed into the GPU by the cardBIOS we don't use the actual 2206 * native modelines fetched via EDID for digitally connected panels. 2207 * - If the BIOS didn't program a modeline in the GPU for a digitally connected panel 2208 * we can't use that panel. 2209 * - The above restrictions exist due to missing nVidia hardware specs. */ 2210 static void detect_panels() 2211 { 2212 /* detect if the BIOS enabled LCD's (internal panels or DVI) or TVout */ 2213 2214 /* both external TMDS transmitters (used for LCD/DVI) and external TVencoders 2215 * (can) use the CRTC's in slaved mode. */ 2216 /* Note: 2217 * DFP's are programmed with standard VESA modelines by the card's BIOS! */ 2218 bool slaved_for_dev1 = false, slaved_for_dev2 = false; 2219 bool tvout1 = false, tvout2 = false; 2220 2221 /* check primary head: */ 2222 /* enable access to primary head */ 2223 set_crtc_owner(0); 2224 2225 /* unlock head's registers for R/W access */ 2226 CRTCW(LOCK, 0x57); 2227 CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); 2228 2229 LOG(2,("INFO: Dumping flatpanel related CRTC registers:\n")); 2230 /* related info PIXEL register: 2231 * b7: 1 = slaved mode (all cards). */ 2232 LOG(2,("CRTC1: PIXEL register: $%02x\n", CRTCR(PIXEL))); 2233 /* info LCD register: 2234 * b7: 1 = stereo view (shutter glasses use) (all cards), 2235 * b5: 1 = power ext. TMDS (or something)/0 = TVout use (?) (confirmed NV17, NV28), 2236 * b4: 1 = power ext. TMDS (or something)/0 = TVout use (?) (confirmed NV34), 2237 * b3: 1 = ??? (not panel related probably!) (confirmed NV34), 2238 * b1: 1 = power ext. TMDS (or something) (?) (confirmed NV05?, NV17), 2239 * b0: 1 = select panel encoder / 0 = select TVout encoder (all cards). */ 2240 LOG(2,("CRTC1: LCD register: $%02x\n", CRTCR(LCD))); 2241 /* info 0x59 register: 2242 * b0: 1 = enable ext. TMDS clock (DPMS) (confirmed NV28, NV34). */ 2243 LOG(2,("CRTC1: register $59: $%02x\n", CRTCR(0x59))); 2244 /* info 0x9f register: 2245 * b4: 0 = TVout use (?). */ 2246 LOG(2,("CRTC1: register $9f: $%02x\n", CRTCR(0x9f))); 2247 2248 /* detect active slave device (if any) */ 2249 slaved_for_dev1 = (CRTCR(PIXEL) & 0x80); 2250 if (slaved_for_dev1) 2251 { 2252 /* if the panel isn't selected, tvout is.. */ 2253 tvout1 = !(CRTCR(LCD) & 0x01); 2254 } 2255 2256 if (si->ps.secondary_head) 2257 { 2258 /* check secondary head: */ 2259 /* enable access to secondary head */ 2260 set_crtc_owner(1); 2261 /* unlock head's registers for R/W access */ 2262 CRTC2W(LOCK, 0x57); 2263 CRTC2W(VSYNCE ,(CRTC2R(VSYNCE) & 0x7f)); 2264 2265 LOG(2,("CRTC2: PIXEL register: $%02x\n", CRTC2R(PIXEL))); 2266 LOG(2,("CRTC2: LCD register: $%02x\n", CRTC2R(LCD))); 2267 LOG(2,("CRTC2: register $59: $%02x\n", CRTC2R(0x59))); 2268 LOG(2,("CRTC2: register $9f: $%02x\n", CRTC2R(0x9f))); 2269 2270 /* detect active slave device (if any) */ 2271 slaved_for_dev2 = (CRTC2R(PIXEL) & 0x80); 2272 if (slaved_for_dev2) 2273 { 2274 /* if the panel isn't selected, tvout is.. */ 2275 tvout2 = !(CRTC2R(LCD) & 0x01); 2276 } 2277 } 2278 2279 LOG(2,("INFO: End flatpanel related CRTC registers dump.\n")); 2280 2281 /* do some presets */ 2282 si->ps.p1_timing.h_display = 0; 2283 si->ps.p1_timing.v_display = 0; 2284 si->ps.p2_timing.h_display = 0; 2285 si->ps.p2_timing.v_display = 0; 2286 si->ps.slaved_tmds1 = false; 2287 si->ps.slaved_tmds2 = false; 2288 si->ps.master_tmds1 = false; 2289 si->ps.master_tmds2 = false; 2290 si->ps.monitors = 0x00; 2291 /* determine the situation we are in... (regarding flatpanels) */ 2292 /* fixme: add VESA DDC EDID stuff one day... */ 2293 /* fixme: find out how to program those transmitters one day instead of 2294 * relying on the cards BIOS to do it. This adds TVout options where panels 2295 * are used! 2296 * Currently we'd loose the panel setup while not being able to restore it. */ 2297 2298 /* note: (facts) 2299 * -> NV11 and NV17 laptops have LVDS panels, programmed in both sets registers; 2300 * -> NV34 laptops have TMDS panels, programmed in only one set of registers; 2301 * -> NV11, NV25 and NV34 DVI cards, so external panels (TMDS) are programmed 2302 * in only one set of registers; 2303 * -> a register-set's FP_TG_CTRL register, bit 31 tells you if a LVDS panel is 2304 * connected to the primary head (0), or to the secondary head (1) except 2305 * on some NV11's if this bit is '0' there; 2306 * -> for LVDS panels both registersets are programmed identically by the card's 2307 * BIOSes; 2308 * -> the programmed set of registers tells you where a TMDS (DVI) panel is 2309 * connected; 2310 * -> On all cards a CRTC is used in slaved mode when a panel is connected, 2311 * except on NV11: here master mode is (might be?) detected. */ 2312 /* note also: 2313 * external TMDS encoders are only used for logic-level translation: it's 2314 * modeline registers are not used. Instead the GPU's internal modeline registers 2315 * are used. The external encoder is not connected to a I2C bus (confirmed NV34). */ 2316 if (slaved_for_dev1 && !tvout1) 2317 { 2318 uint16 width = ((DACR(FP_HDISPEND) & 0x0000ffff) + 1); 2319 uint16 height = ((DACR(FP_VDISPEND) & 0x0000ffff) + 1); 2320 if ((width >= 640) && (height >= 480)) 2321 { 2322 si->ps.slaved_tmds1 = true; 2323 si->ps.monitors |= CRTC1_TMDS; 2324 si->ps.p1_timing.h_display = width; 2325 si->ps.p1_timing.v_display = height; 2326 } 2327 } 2328 2329 if (si->ps.secondary_head && slaved_for_dev2 && !tvout2) 2330 { 2331 uint16 width = ((DAC2R(FP_HDISPEND) & 0x0000ffff) + 1); 2332 uint16 height = ((DAC2R(FP_VDISPEND) & 0x0000ffff) + 1); 2333 if ((width >= 640) && (height >= 480)) 2334 { 2335 si->ps.slaved_tmds2 = true; 2336 si->ps.monitors |= CRTC2_TMDS; 2337 si->ps.p2_timing.h_display = width; 2338 si->ps.p2_timing.v_display = height; 2339 } 2340 } 2341 2342 if ((si->ps.card_type == NV11) && 2343 !si->ps.slaved_tmds1 && !tvout1) 2344 { 2345 uint16 width = ((DACR(FP_HDISPEND) & 0x0000ffff) + 1); 2346 uint16 height = ((DACR(FP_VDISPEND) & 0x0000ffff) + 1); 2347 if ((width >= 640) && (height >= 480)) 2348 { 2349 si->ps.master_tmds1 = true; 2350 si->ps.monitors |= CRTC1_TMDS; 2351 si->ps.p1_timing.h_display = width; 2352 si->ps.p1_timing.v_display = height; 2353 } 2354 } 2355 2356 if ((si->ps.card_type == NV11) && 2357 si->ps.secondary_head && !si->ps.slaved_tmds2 && !tvout2) 2358 { 2359 uint16 width = ((DAC2R(FP_HDISPEND) & 0x0000ffff) + 1); 2360 uint16 height = ((DAC2R(FP_VDISPEND) & 0x0000ffff) + 1); 2361 if ((width >= 640) && (height >= 480)) 2362 { 2363 si->ps.master_tmds2 = true; 2364 si->ps.monitors |= CRTC2_TMDS; 2365 si->ps.p2_timing.h_display = width; 2366 si->ps.p2_timing.v_display = height; 2367 } 2368 } 2369 2370 //fixme...: 2371 //we are assuming that no DVI is used as external monitor on laptops; 2372 //otherwise we probably get into trouble here if the checked specs match. 2373 if (si->ps.laptop && 2374 ((si->ps.monitors & (CRTC1_TMDS | CRTC2_TMDS)) == (CRTC1_TMDS | CRTC2_TMDS)) && 2375 ((DACR(FP_TG_CTRL) & 0x80000000) == (DAC2R(FP_TG_CTRL) & 0x80000000)) && 2376 (si->ps.p1_timing.h_display == si->ps.p2_timing.h_display) && 2377 (si->ps.p1_timing.v_display == si->ps.p2_timing.v_display)) 2378 { 2379 LOG(2,("INFO: correcting double detection of single panel!\n")); 2380 2381 if (si->ps.card_type == NV11) 2382 { 2383 /* LVDS panel is _always_ on CRTC2, so clear false primary detection */ 2384 si->ps.slaved_tmds1 = false; 2385 si->ps.master_tmds1 = false; 2386 si->ps.monitors &= ~CRTC1_TMDS; 2387 si->ps.p1_timing.h_display = 0; 2388 si->ps.p1_timing.v_display = 0; 2389 } 2390 else 2391 { 2392 if (DACR(FP_TG_CTRL) & 0x80000000) 2393 { 2394 /* LVDS panel is on CRTC2, so clear false primary detection */ 2395 si->ps.slaved_tmds1 = false; 2396 si->ps.master_tmds1 = false; 2397 si->ps.monitors &= ~CRTC1_TMDS; 2398 si->ps.p1_timing.h_display = 0; 2399 si->ps.p1_timing.v_display = 0; 2400 } 2401 else 2402 { 2403 /* LVDS panel is on CRTC1, so clear false secondary detection */ 2404 si->ps.slaved_tmds2 = false; 2405 si->ps.master_tmds2 = false; 2406 si->ps.monitors &= ~CRTC2_TMDS; 2407 si->ps.p2_timing.h_display = 0; 2408 si->ps.p2_timing.v_display = 0; 2409 } 2410 } 2411 } 2412 2413 /* fetch panel(s) modeline(s) */ 2414 if (si->ps.monitors & CRTC1_TMDS) 2415 { 2416 /* horizontal timing */ 2417 si->ps.p1_timing.h_sync_start = (DACR(FP_HSYNC_S) & 0x0000ffff) + 1; 2418 si->ps.p1_timing.h_sync_end = (DACR(FP_HSYNC_E) & 0x0000ffff) + 1; 2419 si->ps.p1_timing.h_total = (DACR(FP_HTOTAL) & 0x0000ffff) + 1; 2420 /* vertical timing */ 2421 si->ps.p1_timing.v_sync_start = (DACR(FP_VSYNC_S) & 0x0000ffff) + 1; 2422 si->ps.p1_timing.v_sync_end = (DACR(FP_VSYNC_E) & 0x0000ffff) + 1; 2423 si->ps.p1_timing.v_total = (DACR(FP_VTOTAL) & 0x0000ffff) + 1; 2424 /* sync polarity */ 2425 si->ps.p1_timing.flags = 0; 2426 if (DACR(FP_TG_CTRL) & 0x00000001) si->ps.p1_timing.flags |= B_POSITIVE_VSYNC; 2427 if (DACR(FP_TG_CTRL) & 0x00000010) si->ps.p1_timing.flags |= B_POSITIVE_HSYNC; 2428 /* display enable polarity (not an official flag) */ 2429 if (DACR(FP_TG_CTRL) & 0x10000000) si->ps.p1_timing.flags |= B_BLANK_PEDESTAL; 2430 /* refreshrate: 2431 * fix a DVI or laptop flatpanel to 60Hz refresh! */ 2432 si->ps.p1_timing.pixel_clock = 2433 (si->ps.p1_timing.h_total * si->ps.p1_timing.v_total * 60) / 1000; 2434 } 2435 if (si->ps.monitors & CRTC2_TMDS) 2436 { 2437 /* horizontal timing */ 2438 si->ps.p2_timing.h_sync_start = (DAC2R(FP_HSYNC_S) & 0x0000ffff) + 1; 2439 si->ps.p2_timing.h_sync_end = (DAC2R(FP_HSYNC_E) & 0x0000ffff) + 1; 2440 si->ps.p2_timing.h_total = (DAC2R(FP_HTOTAL) & 0x0000ffff) + 1; 2441 /* vertical timing */ 2442 si->ps.p2_timing.v_sync_start = (DAC2R(FP_VSYNC_S) & 0x0000ffff) + 1; 2443 si->ps.p2_timing.v_sync_end = (DAC2R(FP_VSYNC_E) & 0x0000ffff) + 1; 2444 si->ps.p2_timing.v_total = (DAC2R(FP_VTOTAL) & 0x0000ffff) + 1; 2445 /* sync polarity */ 2446 si->ps.p2_timing.flags = 0; 2447 if (DAC2R(FP_TG_CTRL) & 0x00000001) si->ps.p2_timing.flags |= B_POSITIVE_VSYNC; 2448 if (DAC2R(FP_TG_CTRL) & 0x00000010) si->ps.p2_timing.flags |= B_POSITIVE_HSYNC; 2449 /* display enable polarity (not an official flag) */ 2450 if (DAC2R(FP_TG_CTRL) & 0x10000000) si->ps.p2_timing.flags |= B_BLANK_PEDESTAL; 2451 /* refreshrate: 2452 * fix a DVI or laptop flatpanel to 60Hz refresh! */ 2453 si->ps.p2_timing.pixel_clock = 2454 (si->ps.p2_timing.h_total * si->ps.p2_timing.v_total * 60) / 1000; 2455 } 2456 2457 /* dump some panel configuration registers... */ 2458 LOG(2,("INFO: Dumping flatpanel registers:\n")); 2459 LOG(2,("DUALHEAD_CTRL: $%08x\n", NV_REG32(NV32_DUALHEAD_CTRL))); 2460 LOG(2,("DAC1: FP_HDISPEND: %d\n", DACR(FP_HDISPEND))); 2461 LOG(2,("DAC1: FP_HTOTAL: %d\n", DACR(FP_HTOTAL))); 2462 LOG(2,("DAC1: FP_HCRTC: %d\n", DACR(FP_HCRTC))); 2463 LOG(2,("DAC1: FP_HSYNC_S: %d\n", DACR(FP_HSYNC_S))); 2464 LOG(2,("DAC1: FP_HSYNC_E: %d\n", DACR(FP_HSYNC_E))); 2465 LOG(2,("DAC1: FP_HVALID_S: %d\n", DACR(FP_HVALID_S))); 2466 LOG(2,("DAC1: FP_HVALID_E: %d\n", DACR(FP_HVALID_E))); 2467 2468 LOG(2,("DAC1: FP_VDISPEND: %d\n", DACR(FP_VDISPEND))); 2469 LOG(2,("DAC1: FP_VTOTAL: %d\n", DACR(FP_VTOTAL))); 2470 LOG(2,("DAC1: FP_VCRTC: %d\n", DACR(FP_VCRTC))); 2471 LOG(2,("DAC1: FP_VSYNC_S: %d\n", DACR(FP_VSYNC_S))); 2472 LOG(2,("DAC1: FP_VSYNC_E: %d\n", DACR(FP_VSYNC_E))); 2473 LOG(2,("DAC1: FP_VVALID_S: %d\n", DACR(FP_VVALID_S))); 2474 LOG(2,("DAC1: FP_VVALID_E: %d\n", DACR(FP_VVALID_E))); 2475 2476 LOG(2,("DAC1: FP_CHKSUM: $%08x = (dec) %d\n", DACR(FP_CHKSUM),DACR(FP_CHKSUM))); 2477 LOG(2,("DAC1: FP_TST_CTRL: $%08x\n", DACR(FP_TST_CTRL))); 2478 LOG(2,("DAC1: FP_TG_CTRL: $%08x\n", DACR(FP_TG_CTRL))); 2479 LOG(2,("DAC1: FP_DEBUG0: $%08x\n", DACR(FP_DEBUG0))); 2480 LOG(2,("DAC1: FP_DEBUG1: $%08x\n", DACR(FP_DEBUG1))); 2481 LOG(2,("DAC1: FP_DEBUG2: $%08x\n", DACR(FP_DEBUG2))); 2482 LOG(2,("DAC1: FP_DEBUG3: $%08x\n", DACR(FP_DEBUG3))); 2483 2484 LOG(2,("DAC1: FUNCSEL: $%08x\n", NV_REG32(NV32_FUNCSEL))); 2485 LOG(2,("DAC1: PANEL_PWR: $%08x\n", NV_REG32(NV32_PANEL_PWR))); 2486 2487 if(si->ps.secondary_head) 2488 { 2489 LOG(2,("DAC2: FP_HDISPEND: %d\n", DAC2R(FP_HDISPEND))); 2490 LOG(2,("DAC2: FP_HTOTAL: %d\n", DAC2R(FP_HTOTAL))); 2491 LOG(2,("DAC2: FP_HCRTC: %d\n", DAC2R(FP_HCRTC))); 2492 LOG(2,("DAC2: FP_HSYNC_S: %d\n", DAC2R(FP_HSYNC_S))); 2493 LOG(2,("DAC2: FP_HSYNC_E: %d\n", DAC2R(FP_HSYNC_E))); 2494 LOG(2,("DAC2: FP_HVALID_S:%d\n", DAC2R(FP_HVALID_S))); 2495 LOG(2,("DAC2: FP_HVALID_E: %d\n", DAC2R(FP_HVALID_E))); 2496 2497 LOG(2,("DAC2: FP_VDISPEND: %d\n", DAC2R(FP_VDISPEND))); 2498 LOG(2,("DAC2: FP_VTOTAL: %d\n", DAC2R(FP_VTOTAL))); 2499 LOG(2,("DAC2: FP_VCRTC: %d\n", DAC2R(FP_VCRTC))); 2500 LOG(2,("DAC2: FP_VSYNC_S: %d\n", DAC2R(FP_VSYNC_S))); 2501 LOG(2,("DAC2: FP_VSYNC_E: %d\n", DAC2R(FP_VSYNC_E))); 2502 LOG(2,("DAC2: FP_VVALID_S: %d\n", DAC2R(FP_VVALID_S))); 2503 LOG(2,("DAC2: FP_VVALID_E: %d\n", DAC2R(FP_VVALID_E))); 2504 2505 LOG(2,("DAC2: FP_CHKSUM: $%08x = (dec) %d\n", DAC2R(FP_CHKSUM),DAC2R(FP_CHKSUM))); 2506 LOG(2,("DAC2: FP_TST_CTRL: $%08x\n", DAC2R(FP_TST_CTRL))); 2507 LOG(2,("DAC2: FP_TG_CTRL: $%08x\n", DAC2R(FP_TG_CTRL))); 2508 LOG(2,("DAC2: FP_DEBUG0: $%08x\n", DAC2R(FP_DEBUG0))); 2509 LOG(2,("DAC2: FP_DEBUG1: $%08x\n", DAC2R(FP_DEBUG1))); 2510 LOG(2,("DAC2: FP_DEBUG2: $%08x\n", DAC2R(FP_DEBUG2))); 2511 LOG(2,("DAC2: FP_DEBUG3: $%08x\n", DAC2R(FP_DEBUG3))); 2512 2513 LOG(2,("DAC2: FUNCSEL: $%08x\n", NV_REG32(NV32_2FUNCSEL))); 2514 LOG(2,("DAC2: PANEL_PWR: $%08x\n", NV_REG32(NV32_2PANEL_PWR))); 2515 } 2516 2517 /* if something goes wrong during driver init reading those registers below might 2518 * result in a hanging system. Without reading them at least a blind (or KDL) 2519 * restart becomes possible. Leaving the code here for debugging purposes. */ 2520 if (0) { 2521 /* determine flatpanel type(s) */ 2522 /* note: 2523 * - on NV11 accessing registerset(s) hangs card. 2524 * - the same applies for NV34. 2525 * Confirmed for DAC2 access on ID 0x0322, 2526 * but only after a failed VESA modeswitch by the HAIKU kernel 2527 * at boot time caused by a BIOS fault inside the gfx card: it says 2528 * it can do VESA 1280x1024x32 on CRTC1/DAC1 but it fails: no signal. */ 2529 if ((si->ps.monitors & CRTC1_TMDS) && (si->ps.card_type != NV11)) 2530 { 2531 /* Read a indexed register to see if it indicates LVDS or TMDS panel presence. 2532 * b0-7 = adress, b16 = 1 = write_enable */ 2533 DACW(FP_TMDS_CTRL, ((1 << 16) | 0x04)); 2534 /* (b0-7 = data) */ 2535 if (DACR(FP_TMDS_DATA) & 0x01) 2536 LOG(2,("INFO: Flatpanel on head 1 is LVDS type\n")); 2537 else 2538 LOG(2,("INFO: Flatpanel on head 1 is TMDS type\n")); 2539 } 2540 if ((si->ps.monitors & CRTC2_TMDS) && (si->ps.card_type != NV11)) 2541 { 2542 /* Read a indexed register to see if it indicates LVDS or TMDS panel presence. 2543 * b0-7 = adress, b16 = 1 = write_enable */ 2544 DAC2W(FP_TMDS_CTRL, ((1 << 16) | 0x04)); 2545 /* (b0-7 = data) */ 2546 if (DAC2R(FP_TMDS_DATA) & 0x01) 2547 LOG(2,("INFO: Flatpanel on head 2 is LVDS type\n")); 2548 else 2549 LOG(2,("INFO: Flatpanel on head 2 is TMDS type\n")); 2550 } 2551 } 2552 2553 LOG(2,("INFO: End flatpanel registers dump.\n")); 2554 } 2555 2556 static void setup_output_matrix() 2557 { 2558 /* setup defaults: */ 2559 /* head 1 will be the primary head */ 2560 si->ps.crtc2_prim = false; 2561 /* no screens usable */ 2562 si->ps.crtc1_screen.have_native_edid = false; 2563 si->ps.crtc1_screen.have_full_edid = false; 2564 si->ps.crtc1_screen.timing.h_display = 0; 2565 si->ps.crtc1_screen.timing.v_display = 0; 2566 si->ps.crtc2_screen.have_native_edid = false; 2567 si->ps.crtc2_screen.have_full_edid = false; 2568 si->ps.crtc2_screen.timing.h_display = 0; 2569 si->ps.crtc2_screen.timing.v_display = 0; 2570 2571 /* connect analog outputs straight through if possible */ 2572 if ((si->ps.secondary_head) && (si->ps.card_type != NV11)) 2573 nv_general_output_select(false); 2574 2575 /* panels are pre-connected to a CRTC (1 or 2) by the card's BIOS, 2576 * we can't change this (lack of info) */ 2577 2578 /* detect analog monitors. First try EDID, else use load sensing. */ 2579 /* (load sensing is confirmed working OK on NV04, NV05, NV11, NV18, NV28 and NV34.) */ 2580 /* primary connector: */ 2581 if (si->ps.con1_screen.have_native_edid) { 2582 if (!si->ps.con1_screen.digital) si->ps.monitors |= CRTC1_VGA; 2583 } else { 2584 if (nv_dac_crt_connected()) { 2585 si->ps.monitors |= CRTC1_VGA; 2586 /* assume 4:3 monitor on con1 */ 2587 si->ps.con1_screen.aspect = 1.33; 2588 } 2589 } 2590 2591 /* Note: digitally connected panels take precedence over analog connected screens. */ 2592 2593 /* fill-out crtc1_screen. This is tricky since we don't know which connector connects 2594 * to crtc1. 2595 * Also the BIOS might have programmed for a lower mode than EDID reports: 2596 * which limits our use of the panel (LVDS link setup too slow). */ 2597 if(si->ps.monitors & CRTC1_TMDS) { 2598 /* see if we have the full EDID info somewhere (lacking a hardware spec so 2599 * we need to compare: we don't know the location of a digital cross switch. 2600 * Note: don't compare pixelclock and flags as we make them up ourselves!) */ 2601 if (si->ps.con1_screen.have_full_edid && si->ps.con1_screen.digital && 2602 (si->ps.p1_timing.h_display == si->ps.con1_screen.timing.h_display) && 2603 (si->ps.p1_timing.h_sync_start == si->ps.con1_screen.timing.h_sync_start) && 2604 (si->ps.p1_timing.h_sync_end == si->ps.con1_screen.timing.h_sync_end) && 2605 (si->ps.p1_timing.h_total == si->ps.con1_screen.timing.h_total) && 2606 (si->ps.p1_timing.v_display == si->ps.con1_screen.timing.v_display) && 2607 (si->ps.p1_timing.v_sync_start == si->ps.con1_screen.timing.v_sync_start) && 2608 (si->ps.p1_timing.v_sync_end == si->ps.con1_screen.timing.v_sync_end) && 2609 (si->ps.p1_timing.v_total == si->ps.con1_screen.timing.v_total)) { 2610 /* fill-out crtc1_screen from EDID info fetched from connector 1 */ 2611 memcpy(&(si->ps.crtc1_screen), &(si->ps.con1_screen), sizeof(si->ps.crtc1_screen)); 2612 } else { 2613 if (si->ps.con2_screen.have_full_edid && si->ps.con2_screen.digital && 2614 (si->ps.p1_timing.h_display == si->ps.con2_screen.timing.h_display) && 2615 (si->ps.p1_timing.h_sync_start == si->ps.con2_screen.timing.h_sync_start) && 2616 (si->ps.p1_timing.h_sync_end == si->ps.con2_screen.timing.h_sync_end) && 2617 (si->ps.p1_timing.h_total == si->ps.con2_screen.timing.h_total) && 2618 (si->ps.p1_timing.v_display == si->ps.con2_screen.timing.v_display) && 2619 (si->ps.p1_timing.v_sync_start == si->ps.con2_screen.timing.v_sync_start) && 2620 (si->ps.p1_timing.v_sync_end == si->ps.con2_screen.timing.v_sync_end) && 2621 (si->ps.p1_timing.v_total == si->ps.con2_screen.timing.v_total)) { 2622 /* fill-out crtc1_screen from EDID info fetched from connector 2 */ 2623 memcpy(&(si->ps.crtc1_screen), &(si->ps.con2_screen), sizeof(si->ps.crtc1_screen)); 2624 } else { 2625 /* no match or no full EDID info: use the info fetched from the GPU */ 2626 si->ps.crtc1_screen.timing.pixel_clock = si->ps.p1_timing.pixel_clock; 2627 si->ps.crtc1_screen.timing.h_display = si->ps.p1_timing.h_display; 2628 si->ps.crtc1_screen.timing.h_sync_start = si->ps.p1_timing.h_sync_start; 2629 si->ps.crtc1_screen.timing.h_sync_end = si->ps.p1_timing.h_sync_end; 2630 si->ps.crtc1_screen.timing.h_total = si->ps.p1_timing.h_total; 2631 si->ps.crtc1_screen.timing.v_display = si->ps.p1_timing.v_display; 2632 si->ps.crtc1_screen.timing.v_sync_start = si->ps.p1_timing.v_sync_start; 2633 si->ps.crtc1_screen.timing.v_sync_end = si->ps.p1_timing.v_sync_end; 2634 si->ps.crtc1_screen.timing.v_total = si->ps.p1_timing.v_total; 2635 si->ps.crtc1_screen.timing.flags = si->ps.p1_timing.flags; 2636 si->ps.crtc1_screen.have_native_edid = true; 2637 si->ps.crtc1_screen.aspect = 2638 (si->ps.p1_timing.h_display / ((float)si->ps.p1_timing.v_display)); 2639 si->ps.crtc1_screen.digital = true; 2640 } 2641 } 2642 } else if(si->ps.monitors & CRTC1_VGA) { 2643 /* fill-out crtc1_screen from EDID info, or faked info if EDID failed. */ 2644 memcpy(&(si->ps.crtc1_screen), &(si->ps.con1_screen), sizeof(si->ps.crtc1_screen)); 2645 } 2646 2647 /* force widescreen types if requested */ 2648 if (si->settings.force_ws) si->ps.crtc1_screen.aspect = 1.78; 2649 2650 /* setup output devices and heads */ 2651 if (si->ps.secondary_head) 2652 { 2653 /* fill-out crtc2_screen. This is tricky since we don't know which connector 2654 * connects to crtc2. 2655 * Also the BIOS might have programmed for a lower mode than EDID reports: 2656 * which limits our use of the panel (LVDS link setup too slow). */ 2657 if(si->ps.monitors & CRTC2_TMDS) { 2658 /* see if we have the full EDID info somewhere (lacking a hardware spec so 2659 * we need to compare: we don't know the location of a digital cross switch. 2660 * Note: don't compare pixelclock and flags as we make them up ourselves!) */ 2661 if (si->ps.con1_screen.have_full_edid && si->ps.con1_screen.digital && 2662 (si->ps.p2_timing.h_display == si->ps.con1_screen.timing.h_display) && 2663 (si->ps.p2_timing.h_sync_start == si->ps.con1_screen.timing.h_sync_start) && 2664 (si->ps.p2_timing.h_sync_end == si->ps.con1_screen.timing.h_sync_end) && 2665 (si->ps.p2_timing.h_total == si->ps.con1_screen.timing.h_total) && 2666 (si->ps.p2_timing.v_display == si->ps.con1_screen.timing.v_display) && 2667 (si->ps.p2_timing.v_sync_start == si->ps.con1_screen.timing.v_sync_start) && 2668 (si->ps.p2_timing.v_sync_end == si->ps.con1_screen.timing.v_sync_end) && 2669 (si->ps.p2_timing.v_total == si->ps.con1_screen.timing.v_total)) { 2670 /* fill-out crtc2_screen from EDID info fetched from connector 1 */ 2671 memcpy(&(si->ps.crtc2_screen), &(si->ps.con1_screen), sizeof(si->ps.crtc2_screen)); 2672 } else { 2673 if (si->ps.con2_screen.have_full_edid && si->ps.con2_screen.digital && 2674 (si->ps.p2_timing.h_display == si->ps.con2_screen.timing.h_display) && 2675 (si->ps.p2_timing.h_sync_start == si->ps.con2_screen.timing.h_sync_start) && 2676 (si->ps.p2_timing.h_sync_end == si->ps.con2_screen.timing.h_sync_end) && 2677 (si->ps.p2_timing.h_total == si->ps.con2_screen.timing.h_total) && 2678 (si->ps.p2_timing.v_display == si->ps.con2_screen.timing.v_display) && 2679 (si->ps.p2_timing.v_sync_start == si->ps.con2_screen.timing.v_sync_start) && 2680 (si->ps.p2_timing.v_sync_end == si->ps.con2_screen.timing.v_sync_end) && 2681 (si->ps.p2_timing.v_total == si->ps.con2_screen.timing.v_total)) { 2682 /* fill-out crtc2_screen from EDID info fetched from connector 2 */ 2683 memcpy(&(si->ps.crtc2_screen), &(si->ps.con2_screen), sizeof(si->ps.crtc2_screen)); 2684 } else { 2685 /* no match or no full EDID info: use the info fetched from the GPU */ 2686 si->ps.crtc2_screen.timing.pixel_clock = si->ps.p2_timing.pixel_clock; 2687 si->ps.crtc2_screen.timing.h_display = si->ps.p2_timing.h_display; 2688 si->ps.crtc2_screen.timing.h_sync_start = si->ps.p2_timing.h_sync_start; 2689 si->ps.crtc2_screen.timing.h_sync_end = si->ps.p2_timing.h_sync_end; 2690 si->ps.crtc2_screen.timing.h_total = si->ps.p2_timing.h_total; 2691 si->ps.crtc2_screen.timing.v_display = si->ps.p2_timing.v_display; 2692 si->ps.crtc2_screen.timing.v_sync_start = si->ps.p2_timing.v_sync_start; 2693 si->ps.crtc2_screen.timing.v_sync_end = si->ps.p2_timing.v_sync_end; 2694 si->ps.crtc2_screen.timing.v_total = si->ps.p2_timing.v_total; 2695 si->ps.crtc2_screen.timing.flags = si->ps.p2_timing.flags; 2696 si->ps.crtc2_screen.have_native_edid = true; 2697 si->ps.crtc2_screen.aspect = 2698 (si->ps.p2_timing.h_display / ((float)si->ps.p2_timing.v_display)); 2699 si->ps.crtc2_screen.digital = true; 2700 } 2701 } 2702 } 2703 2704 if (si->ps.card_type != NV11) 2705 { 2706 /* panels are pre-connected to a CRTC (1 or 2) by the card's BIOS, 2707 * we can't change this (lack of info) */ 2708 2709 /* detect analog monitors. First try EDID, else use load sensing. */ 2710 /* (load sensing is confirmed working OK on NV18, NV28 and NV34.) */ 2711 2712 /* secondary connector */ 2713 if (si->ps.con2_screen.have_native_edid) { 2714 if (!si->ps.con2_screen.digital) si->ps.monitors |= CRTC2_VGA; 2715 } else { 2716 if (nv_dac2_crt_connected()) { 2717 si->ps.monitors |= CRTC2_VGA; 2718 /* assume 4:3 monitor on con2 */ 2719 si->ps.con2_screen.aspect = 1.33; 2720 } 2721 } 2722 2723 /* Note: digitally connected panels take precedence over analog connected screens. */ 2724 /* fill-out crtc2_screen if not already filled in by TMDS */ 2725 if ((si->ps.monitors & (CRTC2_TMDS | CRTC2_VGA)) == CRTC2_VGA) { 2726 /* fill-out crtc2_screen from EDID info, or faked info if EDID failed. */ 2727 memcpy(&(si->ps.crtc2_screen), &(si->ps.con2_screen), sizeof(si->ps.crtc2_screen)); 2728 } 2729 /* force widescreen types if requested */ 2730 if (si->settings.force_ws) si->ps.crtc2_screen.aspect = 1.78; 2731 2732 /* setup correct output and head use */ 2733 //fixme? add TVout (only, so no CRT(s) connected) support... 2734 switch (si->ps.monitors) 2735 { 2736 case 0x00: /* no monitor found at all */ 2737 LOG(2,("INFO: head 1 has nothing connected;\n")); 2738 LOG(2,("INFO: head 2 has nothing connected:\n")); 2739 LOG(2,("INFO: defaulting to head 1 for primary use.\n")); 2740 break; 2741 case 0x01: /* digital panel on head 1, nothing on head 2 */ 2742 LOG(2,("INFO: head 1 has a digital panel;\n")); 2743 LOG(2,("INFO: head 2 has nothing connected:\n")); 2744 LOG(2,("INFO: defaulting to head 1 for primary use.\n")); 2745 break; 2746 case 0x02: /* analog panel or CRT on head 1, nothing on head 2 */ 2747 LOG(2,("INFO: head 1 has an analog panel or CRT;\n")); 2748 LOG(2,("INFO: head 2 has nothing connected:\n")); 2749 LOG(2,("INFO: defaulting to head 1 for primary use.\n")); 2750 break; 2751 case 0x03: /* both types on head 1, nothing on head 2 */ 2752 LOG(2,("INFO: head 1 has a digital panel AND an analog panel or CRT;\n")); 2753 LOG(2,("INFO: head 2 has nothing connected:\n")); 2754 LOG(2,("INFO: correcting...\n")); 2755 /* cross connect analog outputs so analog panel or CRT gets head 2 */ 2756 nv_general_output_select(true); 2757 si->ps.monitors = 0x21; 2758 /* tell head 2 it now has a screen (connected at connector 1) */ 2759 memcpy(&(si->ps.crtc2_screen), &(si->ps.con1_screen), sizeof(si->ps.crtc2_screen)); 2760 LOG(2,("INFO: head 1 has a digital panel;\n")); 2761 LOG(2,("INFO: head 2 has an analog panel or CRT:\n")); 2762 LOG(2,("INFO: defaulting to head 1 for primary use.\n")); 2763 break; 2764 case 0x10: /* nothing on head 1, digital panel on head 2 */ 2765 LOG(2,("INFO: head 1 has nothing connected;\n")); 2766 LOG(2,("INFO: head 2 has a digital panel:\n")); 2767 LOG(2,("INFO: defaulting to head 2 for primary use.\n")); 2768 si->ps.crtc2_prim = true; 2769 break; 2770 case 0x20: /* nothing on head 1, analog panel or CRT on head 2 */ 2771 if (si->ps.card_arch < NV40A) { 2772 LOG(2,("INFO: head 1 has nothing connected;\n")); 2773 LOG(2,("INFO: head 2 has an analog panel or CRT:\n")); 2774 LOG(2,("INFO: defaulting to head 2 for primary use.\n")); 2775 si->ps.crtc2_prim = true; 2776 } else { 2777 switch (si->ps.card_type) { 2778 case NV40: /* Geforce 6800 AGP was confirmed OK 'in the old days' */ 2779 case NV41: /* Geforce 6800 type as well - needs to be confirmed (guessing) */ 2780 case NV45: /* Geforce 6800 PCIe - needs to be confirmed (guessing) */ 2781 LOG(2,("INFO: head 1 has nothing connected;\n")); 2782 LOG(2,("INFO: head 2 has an analog panel or CRT:\n")); 2783 LOG(2,("INFO: defaulting to head 2 for primary use.\n")); 2784 si->ps.crtc2_prim = true; 2785 break; 2786 case NV44: 2787 /* NV44 is a special case in this situation (confirmed Geforce 6200LE): 2788 * It's hardware behaves as a NV40/41/45 but there's some unknown extra bit 2789 * which needs to be programmed now to get CRTC2/DAC2 displaying anything 2790 * else than blackness (with monitor ON @ correct refresh and resolution). 2791 * We are therefore forced to use CRTC1/DAC1 instead (as these are presetup 2792 * fully by the card's BIOS at POST in this situation). */ 2793 LOG(2,("INFO: head 1 has nothing connected;\n")); 2794 LOG(2,("INFO: head 2 has an analog panel or CRT:\n")); 2795 LOG(2,("INFO: cross-switching outputs for NV44!\n")); 2796 nv_general_output_select(true); 2797 LOG(2,("INFO: defaulting to head 1 for primary use.\n")); 2798 break; 2799 default: 2800 /* newer NV40 architecture cards contains (an) additional switch(es) 2801 * to connect a CRTC/DAC combination to a connector. The BIOSes of 2802 * these cards connect head1 to connectors 1 and 2 simultaneously if 2803 * only one VGA screen is found being on connector 2. Which is the 2804 * case here. 2805 * Confirmed on NV43, G71 and G73. */ 2806 LOG(2,("INFO: Both card outputs are connected to head 1;\n")); 2807 LOG(2,("INFO: defaulting to head 1 for primary use.\n")); 2808 break; 2809 } 2810 } 2811 break; 2812 case 0x30: /* nothing on head 1, both types on head 2 */ 2813 LOG(2,("INFO: head 1 has nothing connected;\n")); 2814 LOG(2,("INFO: head 2 has a digital panel AND an analog panel or CRT:\n")); 2815 LOG(2,("INFO: correcting...\n")); 2816 /* cross connect analog outputs so analog panel or CRT gets head 1 */ 2817 nv_general_output_select(true); 2818 si->ps.monitors = 0x12; 2819 /* tell head 1 it now has a screen (connected at connector 2) */ 2820 memcpy(&(si->ps.crtc1_screen), &(si->ps.con2_screen), sizeof(si->ps.crtc1_screen)); 2821 LOG(2,("INFO: head 1 has an analog panel or CRT;\n")); 2822 LOG(2,("INFO: head 2 has a digital panel:\n")); 2823 LOG(2,("INFO: defaulting to head 2 for primary use.\n")); 2824 si->ps.crtc2_prim = true; 2825 break; 2826 case 0x11: /* digital panels on both heads */ 2827 LOG(2,("INFO: head 1 has a digital panel;\n")); 2828 LOG(2,("INFO: head 2 has a digital panel:\n")); 2829 LOG(2,("INFO: defaulting to head 1 for primary use.\n")); 2830 break; 2831 case 0x12: /* analog panel or CRT on head 1, digital panel on head 2 */ 2832 LOG(2,("INFO: head 1 has an analog panel or CRT;\n")); 2833 LOG(2,("INFO: head 2 has a digital panel:\n")); 2834 LOG(2,("INFO: defaulting to head 2 for primary use.\n")); 2835 si->ps.crtc2_prim = true; 2836 break; 2837 case 0x21: /* digital panel on head 1, analog panel or CRT on head 2 */ 2838 LOG(2,("INFO: head 1 has a digital panel;\n")); 2839 LOG(2,("INFO: head 2 has an analog panel or CRT:\n")); 2840 LOG(2,("INFO: defaulting to head 1 for primary use.\n")); 2841 break; 2842 case 0x22: /* analog panel(s) or CRT(s) on both heads */ 2843 LOG(2,("INFO: head 1 has an analog panel or CRT;\n")); 2844 LOG(2,("INFO: head 2 has an analog panel or CRT:\n")); 2845 LOG(2,("INFO: defaulting to head 1 for primary use.\n")); 2846 break; 2847 case 0x32: /* more than two monitors connected to just two outputs: illegal! */ 2848 LOG(2,("INFO: illegal monitor setup ($%02x):\n", si->ps.monitors)); 2849 /* head 2 takes precedence because it has a digital panel while 2850 * head 1 has not. */ 2851 LOG(2,("INFO: defaulting to head 2 for primary use.\n")); 2852 si->ps.crtc2_prim = true; 2853 break; 2854 default: /* more than two monitors connected to just two outputs: illegal! */ 2855 LOG(2,("INFO: illegal monitor setup ($%02x):\n", si->ps.monitors)); 2856 LOG(2,("INFO: defaulting to head 1 for primary use.\n")); 2857 break; 2858 } 2859 } 2860 else /* dualhead NV11 cards */ 2861 { 2862 /* confirmed no analog output switch-options for NV11 */ 2863 LOG(2,("INFO: NV11 outputs are hardwired to be straight-through\n")); 2864 2865 /* (DDC or load sense analog monitor on secondary connector is impossible on NV11) */ 2866 2867 /* force widescreen types if requested */ 2868 if (si->settings.force_ws) si->ps.crtc2_screen.aspect = 1.78; 2869 2870 /* setup correct output and head use */ 2871 //fixme? add TVout (only, so no CRT(s) connected) support... 2872 switch (si->ps.monitors) 2873 { 2874 case 0x00: /* no monitor found at all */ 2875 LOG(2,("INFO: head 1 has nothing connected;\n")); 2876 LOG(2,("INFO: head 2 has nothing connected:\n")); 2877 LOG(2,("INFO: defaulting to head 1 for primary use.\n")); 2878 break; 2879 case 0x01: /* digital panel on head 1, nothing on head 2 */ 2880 LOG(2,("INFO: head 1 has a digital panel;\n")); 2881 LOG(2,("INFO: head 2 has nothing connected:\n")); 2882 LOG(2,("INFO: defaulting to head 1 for primary use.\n")); 2883 break; 2884 case 0x02: /* analog panel or CRT on head 1, nothing on head 2 */ 2885 LOG(2,("INFO: head 1 has an analog panel or CRT;\n")); 2886 LOG(2,("INFO: head 2 has nothing connected:\n")); 2887 LOG(2,("INFO: defaulting to head 1 for primary use.\n")); 2888 break; 2889 case 0x03: /* both types on head 1, nothing on head 2 */ 2890 LOG(2,("INFO: head 1 has a digital panel AND an analog panel or CRT;\n")); 2891 LOG(2,("INFO: head 2 has nothing connected:\n")); 2892 LOG(2,("INFO: correction not possible...\n")); 2893 LOG(2,("INFO: defaulting to head 1 for primary use.\n")); 2894 break; 2895 case 0x10: /* nothing on head 1, digital panel on head 2 */ 2896 LOG(2,("INFO: head 1 has nothing connected;\n")); 2897 LOG(2,("INFO: head 2 has a digital panel:\n")); 2898 LOG(2,("INFO: defaulting to head 2 for primary use.\n")); 2899 si->ps.crtc2_prim = true; 2900 break; 2901 case 0x11: /* digital panels on both heads */ 2902 LOG(2,("INFO: head 1 has a digital panel;\n")); 2903 LOG(2,("INFO: head 2 has a digital panel:\n")); 2904 LOG(2,("INFO: defaulting to head 1 for primary use.\n")); 2905 break; 2906 case 0x12: /* analog panel or CRT on head 1, digital panel on head 2 */ 2907 LOG(2,("INFO: head 1 has an analog panel or CRT;\n")); 2908 LOG(2,("INFO: head 2 has a digital panel:\n")); 2909 LOG(2,("INFO: defaulting to head 2 for primary use.\n")); 2910 si->ps.crtc2_prim = true; 2911 break; 2912 default: /* more than two monitors connected to just two outputs: illegal! */ 2913 LOG(2,("INFO: illegal monitor setup ($%02x):\n", si->ps.monitors)); 2914 LOG(2,("INFO: defaulting to head 1 for primary use.\n")); 2915 break; 2916 } 2917 } 2918 } 2919 else /* singlehead cards */ 2920 { 2921 //fixme? add TVout (only, so no CRT connected) support... 2922 } 2923 } 2924 2925 status_t get_crtc1_screen_native_mode(display_mode *mode) 2926 { 2927 if (!si->ps.crtc1_screen.have_native_edid) return B_ERROR; 2928 2929 mode->space = B_RGB32_LITTLE; 2930 mode->virtual_width = si->ps.crtc1_screen.timing.h_display; 2931 mode->virtual_height = si->ps.crtc1_screen.timing.v_display; 2932 mode->h_display_start = 0; 2933 mode->v_display_start = 0; 2934 mode->flags = 0; 2935 memcpy(&mode->timing, &si->ps.crtc1_screen.timing, sizeof(mode->timing)); 2936 2937 return B_OK; 2938 } 2939 2940 status_t get_crtc2_screen_native_mode(display_mode *mode) 2941 { 2942 if (!si->ps.crtc2_screen.have_native_edid) return B_ERROR; 2943 2944 mode->space = B_RGB32_LITTLE; 2945 mode->virtual_width = si->ps.crtc2_screen.timing.h_display; 2946 mode->virtual_height = si->ps.crtc2_screen.timing.v_display; 2947 mode->h_display_start = 0; 2948 mode->v_display_start = 0; 2949 mode->flags = 0; 2950 memcpy(&mode->timing, &si->ps.crtc2_screen.timing, sizeof(mode->timing)); 2951 2952 return B_OK; 2953 } 2954 2955 static void pinsnv4_fake(void) 2956 { 2957 /* we have a standard PLL */ 2958 si->ps.ext_pll = false; 2959 /* carefull not to take to high limits, and high should be >= 2x low. */ 2960 si->ps.max_system_vco = 256; 2961 si->ps.min_system_vco = 128; 2962 si->ps.max_pixel_vco = 256; 2963 si->ps.min_pixel_vco = 128; 2964 si->ps.max_video_vco = 0; 2965 si->ps.min_video_vco = 0; 2966 si->ps.max_dac1_clock = 250; 2967 si->ps.max_dac1_clock_8 = 250; 2968 si->ps.max_dac1_clock_16 = 250; 2969 /* 'failsave' values */ 2970 si->ps.max_dac1_clock_24 = 220; 2971 si->ps.max_dac1_clock_32 = 180; 2972 si->ps.max_dac1_clock_32dh = 180; 2973 /* secondary head */ 2974 si->ps.max_dac2_clock = 0; 2975 si->ps.max_dac2_clock_8 = 0; 2976 si->ps.max_dac2_clock_16 = 0; 2977 si->ps.max_dac2_clock_24 = 0; 2978 si->ps.max_dac2_clock_32 = 0; 2979 /* 'failsave' values */ 2980 si->ps.max_dac2_clock_32dh = 0; 2981 //fixme: primary & secondary_dvi should be overrule-able via nv.settings 2982 si->ps.primary_dvi = false; 2983 si->ps.secondary_dvi = false; 2984 /* not used (yet) because no coldstart will be attempted (yet) */ 2985 si->ps.std_engine_clock = 90; 2986 si->ps.std_memory_clock = 110; 2987 } 2988 2989 static void pinsnv5_nv5m64_fake(void) 2990 { 2991 /* we have a standard PLL */ 2992 si->ps.ext_pll = false; 2993 /* carefull not to take to high limits, and high should be >= 2x low. */ 2994 si->ps.max_system_vco = 300; 2995 si->ps.min_system_vco = 128; 2996 si->ps.max_pixel_vco = 300; 2997 si->ps.min_pixel_vco = 128; 2998 si->ps.max_video_vco = 0; 2999 si->ps.min_video_vco = 0; 3000 si->ps.max_dac1_clock = 300; 3001 si->ps.max_dac1_clock_8 = 300; 3002 si->ps.max_dac1_clock_16 = 300; 3003 /* 'failsave' values */ 3004 si->ps.max_dac1_clock_24 = 270; 3005 si->ps.max_dac1_clock_32 = 230; 3006 si->ps.max_dac1_clock_32dh = 230; 3007 /* secondary head */ 3008 si->ps.max_dac2_clock = 0; 3009 si->ps.max_dac2_clock_8 = 0; 3010 si->ps.max_dac2_clock_16 = 0; 3011 si->ps.max_dac2_clock_24 = 0; 3012 si->ps.max_dac2_clock_32 = 0; 3013 /* 'failsave' values */ 3014 si->ps.max_dac2_clock_32dh = 0; 3015 //fixme: primary & secondary_dvi should be overrule-able via nv.settings 3016 si->ps.primary_dvi = false; 3017 si->ps.secondary_dvi = false; 3018 /* not used (yet) because no coldstart will be attempted (yet) */ 3019 si->ps.std_engine_clock = 125; 3020 si->ps.std_memory_clock = 150; 3021 } 3022 3023 static void pinsnv6_fake(void) 3024 { 3025 /* we have a standard PLL */ 3026 si->ps.ext_pll = false; 3027 /* carefull not to take to high limits, and high should be >= 2x low. */ 3028 si->ps.max_system_vco = 300; 3029 si->ps.min_system_vco = 128; 3030 si->ps.max_pixel_vco = 300; 3031 si->ps.min_pixel_vco = 128; 3032 si->ps.max_video_vco = 0; 3033 si->ps.min_video_vco = 0; 3034 si->ps.max_dac1_clock = 300; 3035 si->ps.max_dac1_clock_8 = 300; 3036 si->ps.max_dac1_clock_16 = 300; 3037 /* 'failsave' values */ 3038 si->ps.max_dac1_clock_24 = 270; 3039 si->ps.max_dac1_clock_32 = 230; 3040 si->ps.max_dac1_clock_32dh = 230; 3041 /* secondary head */ 3042 si->ps.max_dac2_clock = 0; 3043 si->ps.max_dac2_clock_8 = 0; 3044 si->ps.max_dac2_clock_16 = 0; 3045 si->ps.max_dac2_clock_24 = 0; 3046 si->ps.max_dac2_clock_32 = 0; 3047 /* 'failsave' values */ 3048 si->ps.max_dac2_clock_32dh = 0; 3049 //fixme: primary & secondary_dvi should be overrule-able via nv.settings 3050 si->ps.primary_dvi = false; 3051 si->ps.secondary_dvi = false; 3052 /* not used (yet) because no coldstart will be attempted (yet) */ 3053 si->ps.std_engine_clock = 100; 3054 si->ps.std_memory_clock = 125; 3055 } 3056 3057 static void pinsnv10_arch_fake(void) 3058 { 3059 /* we have a standard PLL */ 3060 si->ps.ext_pll = false; 3061 /* carefull not to take to high limits, and high should be >= 2x low. */ 3062 si->ps.max_system_vco = 350; 3063 si->ps.min_system_vco = 128; 3064 si->ps.max_pixel_vco = 350; 3065 si->ps.min_pixel_vco = 128; 3066 si->ps.max_video_vco = 350; 3067 si->ps.min_video_vco = 128; 3068 si->ps.max_dac1_clock = 350; 3069 si->ps.max_dac1_clock_8 = 350; 3070 si->ps.max_dac1_clock_16 = 350; 3071 /* 'failsave' values */ 3072 si->ps.max_dac1_clock_24 = 320; 3073 si->ps.max_dac1_clock_32 = 280; 3074 si->ps.max_dac1_clock_32dh = 250; 3075 /* secondary head */ 3076 if (si->ps.card_type < NV17) 3077 { 3078 /* if a GeForce2 has analog VGA dualhead capability, 3079 * it uses an external secondary DAC probably with limited capability. */ 3080 /* (called twinview technology) */ 3081 si->ps.max_dac2_clock = 200; 3082 si->ps.max_dac2_clock_8 = 200; 3083 si->ps.max_dac2_clock_16 = 200; 3084 si->ps.max_dac2_clock_24 = 200; 3085 si->ps.max_dac2_clock_32 = 200; 3086 /* 'failsave' values */ 3087 si->ps.max_dac2_clock_32dh = 180; 3088 } 3089 else 3090 { 3091 /* GeForce4 cards have dual integrated DACs with identical capaability */ 3092 /* (called nview technology) */ 3093 si->ps.max_dac2_clock = 350; 3094 si->ps.max_dac2_clock_8 = 350; 3095 si->ps.max_dac2_clock_16 = 350; 3096 /* 'failsave' values */ 3097 si->ps.max_dac2_clock_24 = 320; 3098 si->ps.max_dac2_clock_32 = 280; 3099 si->ps.max_dac2_clock_32dh = 250; 3100 } 3101 //fixme: primary & secondary_dvi should be overrule-able via nv.settings 3102 si->ps.primary_dvi = false; 3103 si->ps.secondary_dvi = false; 3104 /* not used (yet) because no coldstart will be attempted (yet) */ 3105 si->ps.std_engine_clock = 120; 3106 si->ps.std_memory_clock = 150; 3107 } 3108 3109 static void pinsnv20_arch_fake(void) 3110 { 3111 /* we have a standard PLL */ 3112 si->ps.ext_pll = false; 3113 /* carefull not to take to high limits, and high should be >= 2x low. */ 3114 si->ps.max_system_vco = 350; 3115 si->ps.min_system_vco = 128; 3116 si->ps.max_pixel_vco = 350; 3117 si->ps.min_pixel_vco = 128; 3118 si->ps.max_video_vco = 350; 3119 si->ps.min_video_vco = 128; 3120 si->ps.max_dac1_clock = 350; 3121 si->ps.max_dac1_clock_8 = 350; 3122 si->ps.max_dac1_clock_16 = 350; 3123 /* 'failsave' values */ 3124 si->ps.max_dac1_clock_24 = 320; 3125 si->ps.max_dac1_clock_32 = 280; 3126 si->ps.max_dac1_clock_32dh = 250; 3127 /* secondary head */ 3128 /* GeForce4 cards have dual integrated DACs with identical capaability */ 3129 /* (called nview technology) */ 3130 si->ps.max_dac2_clock = 350; 3131 si->ps.max_dac2_clock_8 = 350; 3132 si->ps.max_dac2_clock_16 = 350; 3133 /* 'failsave' values */ 3134 si->ps.max_dac2_clock_24 = 320; 3135 si->ps.max_dac2_clock_32 = 280; 3136 si->ps.max_dac2_clock_32dh = 250; 3137 //fixme: primary & secondary_dvi should be overrule-able via nv.settings 3138 si->ps.primary_dvi = false; 3139 si->ps.secondary_dvi = false; 3140 /* not used (yet) because no coldstart will be attempted (yet) */ 3141 si->ps.std_engine_clock = 175; 3142 si->ps.std_memory_clock = 200; 3143 } 3144 3145 /* notes on PLL's: 3146 on NV34, GeForce FX 5200, id 0x0322 DAC1 PLL observed behaviour: 3147 - Fcomp may be as high as 27Mhz (BIOS), and current set range seems ok as well; 3148 - Fvco may not be as low as 216Mhz (DVI pixelclock intermittant locking error, 3149 visible as horizontal shifting picture and black screen (out of range): both intermittant); 3150 - Fvco may be as high as 432Mhz (BIOS); 3151 - This is not an extended PLL: the second divisor register does not do anything. 3152 */ 3153 static void pinsnv30_arch_fake(void) 3154 { 3155 /* determine PLL type */ 3156 if ((si->ps.card_type == NV31) || 3157 (si->ps.card_type == NV36) || 3158 (si->ps.card_type >= NV40)) 3159 { 3160 /* we have a extended PLL */ 3161 si->ps.ext_pll = true; 3162 } 3163 else 3164 { 3165 /* we have a standard PLL */ 3166 si->ps.ext_pll = false; 3167 } 3168 /* carefull not to take to high limits, and high should be >= 2x low. */ 3169 si->ps.max_system_vco = 350; 3170 si->ps.min_system_vco = 128; 3171 if (si->ps.ext_pll) 3172 { 3173 si->ps.max_pixel_vco = 600; 3174 si->ps.min_pixel_vco = 220; 3175 si->ps.max_video_vco = 600; 3176 si->ps.min_video_vco = 220; 3177 } 3178 else 3179 { 3180 si->ps.max_pixel_vco = 350; 3181 si->ps.min_pixel_vco = 128; 3182 si->ps.max_video_vco = 350; 3183 si->ps.min_video_vco = 128; 3184 } 3185 si->ps.max_dac1_clock = 350; 3186 si->ps.max_dac1_clock_8 = 350; 3187 si->ps.max_dac1_clock_16 = 350; 3188 /* 'failsave' values */ 3189 si->ps.max_dac1_clock_24 = 320; 3190 si->ps.max_dac1_clock_32 = 280; 3191 si->ps.max_dac1_clock_32dh = 250; 3192 /* secondary head */ 3193 /* GeForceFX cards have dual integrated DACs with identical capability */ 3194 /* (called nview technology) */ 3195 si->ps.max_dac2_clock = 350; 3196 si->ps.max_dac2_clock_8 = 350; 3197 si->ps.max_dac2_clock_16 = 350; 3198 /* 'failsave' values */ 3199 si->ps.max_dac2_clock_24 = 320; 3200 si->ps.max_dac2_clock_32 = 280; 3201 si->ps.max_dac2_clock_32dh = 250; 3202 //fixme: primary & secondary_dvi should be overrule-able via nv.settings 3203 si->ps.primary_dvi = false; 3204 si->ps.secondary_dvi = false; 3205 /* not used (yet) because no coldstart will be attempted (yet) */ 3206 si->ps.std_engine_clock = 190; 3207 si->ps.std_memory_clock = 190; 3208 } 3209 3210 static void getRAMsize_arch_nv4(void) 3211 { 3212 uint32 strapinfo = NV_REG32(NV32_NV4STRAPINFO); 3213 3214 if (strapinfo & 0x00000100) 3215 { 3216 /* Unified memory architecture used */ 3217 si->ps.memory_size = 1024 * 1024 * 3218 ((((strapinfo & 0x0000f000) >> 12) * 2) + 2); 3219 3220 LOG(8,("INFO: NV4 architecture chip with UMA detected\n")); 3221 } 3222 else 3223 { 3224 /* private memory architecture used */ 3225 switch (strapinfo & 0x00000003) 3226 { 3227 case 0: 3228 si->ps.memory_size = 32 * 1024 * 1024; 3229 break; 3230 case 1: 3231 si->ps.memory_size = 4 * 1024 * 1024; 3232 break; 3233 case 2: 3234 si->ps.memory_size = 8 * 1024 * 1024; 3235 break; 3236 case 3: 3237 si->ps.memory_size = 16 * 1024 * 1024; 3238 break; 3239 } 3240 } 3241 } 3242 3243 static void getstrap_arch_nv4(void) 3244 { 3245 uint32 strapinfo = NV_REG32(NV32_NVSTRAPINFO2); 3246 3247 /* determine PLL reference crystal frequency */ 3248 if (strapinfo & 0x00000040) 3249 si->ps.f_ref = 14.31818; 3250 else 3251 si->ps.f_ref = 13.50000; 3252 3253 /* these cards are always singlehead */ 3254 si->ps.secondary_head = false; 3255 } 3256 3257 static void getRAMsize_arch_nv10_20_30_40(void) 3258 { 3259 uint32 dev_manID = CFGR(DEVID); 3260 uint32 strapinfo = NV_REG32(NV32_NV10STRAPINFO); 3261 uint32 mem_size; 3262 3263 switch (dev_manID) 3264 { 3265 case 0x01a010de: /* Nvidia GeForce2 Integrated GPU */ 3266 case 0x01f010de: /* Nvidia GeForce4 MX Integrated GPU */ 3267 /* the kerneldriver already determined the amount of RAM these cards have at 3268 * their disposal (UMA, values read from PCI config space in other device) */ 3269 LOG(8,("INFO: nVidia GPU with UMA detected\n")); 3270 break; 3271 default: 3272 LOG(8,("INFO: kerneldriver mapped %3.3fMb framebuffer memory\n", 3273 (si->ps.memory_size / (1024.0 * 1024.0)))); 3274 LOG(8,("INFO: (Memory detection) Strapinfo value is: $%08x\n", strapinfo)); 3275 3276 mem_size = (strapinfo & 0x3ff00000); 3277 if (!mem_size) { 3278 mem_size = 16 * 1024 * 1024; 3279 3280 LOG(8,("INFO: NV10/20/30 architecture chip with unknown RAM amount detected;\n")); 3281 LOG(8,("INFO: Setting 16Mb\n")); 3282 } 3283 /* don't attempt to adress memory not mapped by the kerneldriver */ 3284 if (si->ps.memory_size > mem_size) si->ps.memory_size = mem_size; 3285 } 3286 } 3287 3288 static void getstrap_arch_nv10_20_30_40(void) 3289 { 3290 uint32 dev_manID = CFGR(DEVID); 3291 uint32 strapinfo = NV_REG32(NV32_NVSTRAPINFO2); 3292 3293 /* determine if we have a dualhead card */ 3294 si->ps.secondary_head = false; 3295 switch (si->ps.card_type) 3296 { 3297 case NV04: 3298 case NV05: 3299 case NV05M64: 3300 case NV06: 3301 case NV10: 3302 case NV15: 3303 case NV20: 3304 break; 3305 default: 3306 if ((dev_manID & 0xfff0ffff) == 0x01a010de) 3307 { 3308 /* this is a singlehead NV11! */ 3309 } 3310 else 3311 { 3312 si->ps.secondary_head = true; 3313 } 3314 } 3315 3316 /* determine PLL reference crystal frequency: three types are used... */ 3317 if (strapinfo & 0x00000040) 3318 si->ps.f_ref = 14.31818; 3319 else 3320 si->ps.f_ref = 13.50000; 3321 3322 if ((si->ps.secondary_head) && (si->ps.card_type != NV11)) 3323 { 3324 if (strapinfo & 0x00400000) si->ps.f_ref = 27.00000; 3325 } 3326 } 3327 3328 void dump_pins(void) 3329 { 3330 char *msg = ""; 3331 3332 LOG(2,("INFO: pinsdump follows:\n")); 3333 LOG(2,("PLL type: %s\n", si->ps.ext_pll ? "extended" : "standard")); 3334 LOG(2,("f_ref: %fMhz\n", si->ps.f_ref)); 3335 LOG(2,("max_system_vco: %dMhz\n", si->ps.max_system_vco)); 3336 LOG(2,("min_system_vco: %dMhz\n", si->ps.min_system_vco)); 3337 LOG(2,("max_pixel_vco: %dMhz\n", si->ps.max_pixel_vco)); 3338 LOG(2,("min_pixel_vco: %dMhz\n", si->ps.min_pixel_vco)); 3339 LOG(2,("max_video_vco: %dMhz\n", si->ps.max_video_vco)); 3340 LOG(2,("min_video_vco: %dMhz\n", si->ps.min_video_vco)); 3341 LOG(2,("std_engine_clock: %dMhz\n", si->ps.std_engine_clock)); 3342 LOG(2,("std_memory_clock: %dMhz\n", si->ps.std_memory_clock)); 3343 LOG(2,("max_dac1_clock: %dMhz\n", si->ps.max_dac1_clock)); 3344 LOG(2,("max_dac1_clock_8: %dMhz\n", si->ps.max_dac1_clock_8)); 3345 LOG(2,("max_dac1_clock_16: %dMhz\n", si->ps.max_dac1_clock_16)); 3346 LOG(2,("max_dac1_clock_24: %dMhz\n", si->ps.max_dac1_clock_24)); 3347 LOG(2,("max_dac1_clock_32: %dMhz\n", si->ps.max_dac1_clock_32)); 3348 LOG(2,("max_dac1_clock_32dh: %dMhz\n", si->ps.max_dac1_clock_32dh)); 3349 LOG(2,("max_dac2_clock: %dMhz\n", si->ps.max_dac2_clock)); 3350 LOG(2,("max_dac2_clock_8: %dMhz\n", si->ps.max_dac2_clock_8)); 3351 LOG(2,("max_dac2_clock_16: %dMhz\n", si->ps.max_dac2_clock_16)); 3352 LOG(2,("max_dac2_clock_24: %dMhz\n", si->ps.max_dac2_clock_24)); 3353 LOG(2,("max_dac2_clock_32: %dMhz\n", si->ps.max_dac2_clock_32)); 3354 LOG(2,("max_dac2_clock_32dh: %dMhz\n", si->ps.max_dac2_clock_32dh)); 3355 LOG(2,("secondary_head: %s\n", si->ps.secondary_head ? "present" : "absent")); 3356 LOG(2,("tvout: %s\n", si->ps.tvout ? "present" : "absent")); 3357 /* setup TVout logmessage text */ 3358 switch (si->ps.tv_encoder.type) 3359 { 3360 case NONE: 3361 msg = "No"; 3362 break; 3363 case CH7003: 3364 msg = "Chrontel CH7003"; 3365 break; 3366 case CH7004: 3367 msg = "Chrontel CH7004"; 3368 break; 3369 case CH7005: 3370 msg = "Chrontel CH7005"; 3371 break; 3372 case CH7006: 3373 msg = "Chrontel CH7006"; 3374 break; 3375 case CH7007: 3376 msg = "Chrontel CH7007"; 3377 break; 3378 case CH7008: 3379 msg = "Chrontel CH7008"; 3380 break; 3381 case SAA7102: 3382 msg = "Philips SAA7102"; 3383 break; 3384 case SAA7103: 3385 msg = "Philips SAA7103"; 3386 break; 3387 case SAA7104: 3388 msg = "Philips SAA7104"; 3389 break; 3390 case SAA7105: 3391 msg = "Philips SAA7105"; 3392 break; 3393 case BT868: 3394 msg = "Brooktree/Conexant BT868"; 3395 break; 3396 case BT869: 3397 msg = "Brooktree/Conexant BT869"; 3398 break; 3399 case CX25870: 3400 msg = "Conexant CX25870"; 3401 break; 3402 case CX25871: 3403 msg = "Conexant CX25871"; 3404 break; 3405 case NVIDIA: 3406 msg = "Nvidia internal"; 3407 break; 3408 default: 3409 msg = "Unknown"; 3410 break; 3411 } 3412 LOG(2, ("%s TV encoder detected; silicon revision is $%02x\n", 3413 msg, si->ps.tv_encoder.version)); 3414 // LOG(2,("primary_dvi: ")); 3415 // if (si->ps.primary_dvi) LOG(2,("present\n")); else LOG(2,("absent\n")); 3416 // LOG(2,("secondary_dvi: ")); 3417 // if (si->ps.secondary_dvi) LOG(2,("present\n")); else LOG(2,("absent\n")); 3418 LOG(2,("card memory_size: %3.3fMb\n", (si->ps.memory_size / (1024.0 * 1024.0)))); 3419 LOG(2,("laptop: ")); 3420 if (si->ps.laptop) LOG(2,("yes\n")); else LOG(2,("no\n")); 3421 if (si->ps.monitors & CRTC1_TMDS) 3422 { 3423 LOG(2,("found DFP (digital flatpanel) on CRTC1; CRTC1 is %s\n", 3424 si->ps.slaved_tmds1 ? "slaved" : "master")); 3425 LOG(2,("panel width: %d, height: %d, aspect ratio: %1.2f\n", 3426 si->ps.p1_timing.h_display, si->ps.p1_timing.v_display, si->ps.crtc1_screen.aspect)); 3427 } 3428 if (si->ps.monitors & CRTC2_TMDS) 3429 { 3430 LOG(2,("found DFP (digital flatpanel) on CRTC2; CRTC2 is %s\n", 3431 si->ps.slaved_tmds2 ? "slaved" : "master")); 3432 LOG(2,("panel width: %d, height: %d, aspect ratio: %1.2f\n", 3433 si->ps.p2_timing.h_display, si->ps.p2_timing.v_display, si->ps.crtc2_screen.aspect)); 3434 } 3435 LOG(2,("monitor (output devices) setup matrix: $%02x\n", si->ps.monitors)); 3436 LOG(2,("INFO: end pinsdump.\n")); 3437 } 3438