1 /* Read initialisation information from card */ 2 /* some bits are hacks, where PINS is not known */ 3 /* Author: 4 Rudolf Cornelissen 7/2003 5 */ 6 7 #define MODULE_BIT 0x00002000 8 9 #include "nv_std.h" 10 11 /* Parse the BIOS PINS structure if there */ 12 status_t parse_pins () 13 { 14 uint8 pins_len = 0; 15 uint8 *rom; 16 uint8 *pins; 17 uint8 chksum = 0; 18 int i; 19 status_t result = B_ERROR; 20 21 /* preset PINS read status to failed */ 22 si->ps.pins_status = B_ERROR; 23 24 /* check the validity of PINS */ 25 LOG(2,("INFO: Reading PINS info\n")); 26 rom = (uint8 *) si->rom_mirror; 27 /* check BIOS signature */ 28 if (rom[0]!=0x55 || rom[1]!=0xaa) 29 { 30 LOG(8,("INFO: BIOS signiture not found\n")); 31 return B_ERROR; 32 } 33 LOG(2,("INFO: BIOS signiture $AA55 found OK\n")); 34 /* check for a valid PINS struct adress */ 35 pins = rom + (rom[0x7FFC]|(rom[0x7FFD]<<8)); 36 if ((pins - rom) > 0x7F80) 37 { 38 LOG(8,("INFO: invalid PINS adress\n")); 39 return B_ERROR; 40 } 41 /* checkout new PINS struct version if there */ 42 if ((pins[0] == 0x2E) && (pins[1] == 0x41)) 43 { 44 pins_len = pins[2]; 45 if (pins_len < 3 || pins_len > 128) 46 { 47 LOG(8,("INFO: invalid PINS size\n")); 48 return B_ERROR; 49 } 50 51 /* calculate PINS checksum */ 52 for (i = 0; i < pins_len; i++) 53 { 54 chksum += pins[i]; 55 } 56 if (chksum) 57 { 58 LOG(8,("INFO: PINS checksum error\n")); 59 return B_ERROR; 60 } 61 LOG(2,("INFO: new PINS, version %u.%u, length %u\n", pins[5], pins[4], pins[2])); 62 /* fill out the si->ps struct if possible */ 63 switch (pins[5]) 64 { 65 case 5: 66 result = pins5_read(pins, pins_len); 67 break; 68 default: 69 LOG(8,("INFO: unknown PINS version\n")); 70 return B_ERROR; 71 break; 72 } 73 } 74 /* no valid PINS signature found */ 75 else 76 { 77 LOG(8,("INFO: no PINS signature found\n")); 78 return B_ERROR; 79 } 80 /* check PINS read result */ 81 if (result == B_ERROR) 82 { 83 LOG(8,("INFO: PINS read/decode error\n")); 84 return B_ERROR; 85 } 86 /* PINS scan succeeded */ 87 si->ps.pins_status = B_OK; 88 LOG(2,("INFO: PINS scan completed succesfully\n")); 89 return B_OK; 90 } 91 92 /* pins v5 is used by G450 and G550 */ 93 status_t pins5_read(uint8 *pins, uint8 length) 94 { 95 unsigned int m_factor = 6; 96 97 if (length != 128) 98 { 99 LOG(8,("INFO: wrong PINS length, expected 128, got %d\n", length)); 100 return B_ERROR; 101 } 102 103 /* fill out the shared info si->ps struct */ 104 if (pins[4] == 0x01) m_factor = 8; 105 if (pins[4] >= 0x02) m_factor = 10; 106 107 si->ps.max_system_vco = m_factor * pins[36]; 108 si->ps.max_video_vco = m_factor * pins[37]; 109 si->ps.max_pixel_vco = m_factor * pins[38]; 110 si->ps.min_system_vco = m_factor * pins[121]; 111 si->ps.min_video_vco = m_factor * pins[122]; 112 si->ps.min_pixel_vco = m_factor * pins[123]; 113 114 if (pins[39] == 0xff) si->ps.max_dac1_clock_8 = si->ps.max_pixel_vco; 115 else si->ps.max_dac1_clock_8 = 4 * pins[39]; 116 117 if (pins[40] == 0xff) si->ps.max_dac1_clock_16 = si->ps.max_dac1_clock_8; 118 else si->ps.max_dac1_clock_16 = 4 * pins[40]; 119 120 if (pins[41] == 0xff) si->ps.max_dac1_clock_24 = si->ps.max_dac1_clock_16; 121 else si->ps.max_dac1_clock_24 = 4 * pins[41]; 122 123 if (pins[42] == 0xff) si->ps.max_dac1_clock_32 = si->ps.max_dac1_clock_24; 124 else si->ps.max_dac1_clock_32 = 4 * pins[42]; 125 126 if (pins[124] == 0xff) si->ps.max_dac1_clock_32dh = si->ps.max_dac1_clock_32; 127 else si->ps.max_dac1_clock_32dh = 4 * pins[124]; 128 129 if (pins[43] == 0xff) si->ps.max_dac2_clock_16 = si->ps.max_video_vco; 130 else si->ps.max_dac2_clock_16 = 4 * pins[43]; 131 132 if (pins[44] == 0xff) si->ps.max_dac2_clock_32 = si->ps.max_dac2_clock_16; 133 else si->ps.max_dac2_clock_32 = 4 * pins[44]; 134 135 if (pins[125] == 0xff) si->ps.max_dac2_clock_32dh = si->ps.max_dac2_clock_32; 136 else si->ps.max_dac2_clock_32dh = 4 * pins[125]; 137 138 if (pins[118] == 0xff) si->ps.max_dac1_clock = si->ps.max_dac1_clock_8; 139 else si->ps.max_dac1_clock = 4 * pins[118]; 140 141 if (pins[119] == 0xff) si->ps.max_dac2_clock = si->ps.max_dac1_clock; 142 else si->ps.max_dac2_clock = 4 * pins[119]; 143 144 si->ps.std_engine_clock = 4 * pins[74]; 145 si->ps.std_memory_clock = 4 * pins[92]; 146 147 si->ps.memory_size = ((pins[114] & 0x03) + 1) * 8; 148 if ((pins[114] & 0x07) > 3) 149 { 150 LOG(8,("INFO: unknown RAM size, defaulting to 8Mb\n")); 151 si->ps.memory_size = 8; 152 } 153 154 if (pins[110] & 0x01) si->ps.f_ref = 14.31818; 155 else si->ps.f_ref = 27.00000; 156 157 /* make sure SGRAM functions only get enabled if SGRAM mounted */ 158 if ((pins[114] & 0x18) == 0x08) si->ps.sdram = false; 159 else si->ps.sdram = true; 160 161 /* various registers */ 162 si->ps.secondary_head = (pins[117] & 0x70); 163 si->ps.tvout = (pins[117] & 0x40); 164 si->ps.primary_dvi = (pins[117] & 0x02); 165 si->ps.secondary_dvi = (pins[117] & 0x20); 166 167 /* not supported: */ 168 si->ps.max_dac2_clock_8 = 0; 169 si->ps.max_dac2_clock_24 = 0; 170 171 return B_OK; 172 } 173 174 /* fake_pins presumes the card was coldstarted by it's BIOS */ 175 void fake_pins(void) 176 { 177 LOG(8,("INFO: faking PINS\n")); 178 179 /* set failsave speeds */ 180 switch (si->ps.card_type) 181 { 182 case NV04: 183 pinsnv4_fake(); 184 break; 185 case NV05: 186 case NV05M64: 187 pinsnv5_nv5m64_fake(); 188 break; 189 case NV06: 190 pinsnv6_fake(); 191 break; 192 default: 193 switch (si->ps.card_arch) 194 { 195 case NV10A: 196 pinsnv10_arch_fake(); 197 break; 198 case NV20A: 199 pinsnv20_arch_fake(); 200 break; 201 case NV30A: 202 pinsnv30_arch_fake(); 203 break; 204 default: 205 /* 'failsafe' values... */ 206 pinsnv10_arch_fake(); 207 break; 208 } 209 break; 210 } 211 212 /* detect RAM amount, reference crystal frequency and dualhead */ 213 switch (si->ps.card_arch) 214 { 215 case NV04A: 216 getstrap_arch_nv4(); 217 break; 218 default: 219 getstrap_arch_nv10_20(); 220 break; 221 } 222 223 /* find out if the card has a tvout chip */ 224 si->ps.tvout = false; 225 si->ps.tvout_chip_type = NONE; 226 //fixme ;-) 227 /* if (i2c_maven_probe() == B_OK) 228 { 229 si->ps.tvout = true; 230 si->ps.tvout_chip_bus = ???; 231 si->ps.tvout_chip_type = ???; 232 } 233 */ 234 } 235 236 void pinsnv4_fake(void) 237 { 238 /* carefull not to take to high limits, and high should be >= 2x low. */ 239 si->ps.max_system_vco = 256; 240 si->ps.min_system_vco = 128; 241 si->ps.max_pixel_vco = 256; 242 si->ps.min_pixel_vco = 128; 243 si->ps.max_video_vco = 0; 244 si->ps.min_video_vco = 0; 245 si->ps.max_dac1_clock = 250; 246 si->ps.max_dac1_clock_8 = 250; 247 si->ps.max_dac1_clock_16 = 250; 248 /* 'failsave' values */ 249 si->ps.max_dac1_clock_24 = 220; 250 si->ps.max_dac1_clock_32 = 180; 251 si->ps.max_dac1_clock_32dh = 180; 252 /* secondary head */ 253 si->ps.max_dac2_clock = 0; 254 si->ps.max_dac2_clock_8 = 0; 255 si->ps.max_dac2_clock_16 = 0; 256 si->ps.max_dac2_clock_24 = 0; 257 si->ps.max_dac2_clock_32 = 0; 258 /* 'failsave' values */ 259 si->ps.max_dac2_clock_32dh = 0; 260 //fixme: primary & secondary_dvi should be overrule-able via nv.settings 261 si->ps.primary_dvi = false; 262 si->ps.secondary_dvi = false; 263 //fixme: is this needed for nv acc? 264 //fail-safe mode for now: 265 si->ps.sdram = true; 266 267 /* not used (yet) because no coldstart will be attempted (yet) */ 268 si->ps.std_engine_clock = 90; 269 si->ps.std_memory_clock = 110; 270 } 271 272 void pinsnv5_nv5m64_fake(void) 273 { 274 /* carefull not to take to high limits, and high should be >= 2x low. */ 275 si->ps.max_system_vco = 300; 276 si->ps.min_system_vco = 128; 277 si->ps.max_pixel_vco = 300; 278 si->ps.min_pixel_vco = 128; 279 si->ps.max_video_vco = 0; 280 si->ps.min_video_vco = 0; 281 si->ps.max_dac1_clock = 300; 282 si->ps.max_dac1_clock_8 = 300; 283 si->ps.max_dac1_clock_16 = 300; 284 /* 'failsave' values */ 285 si->ps.max_dac1_clock_24 = 270; 286 si->ps.max_dac1_clock_32 = 230; 287 si->ps.max_dac1_clock_32dh = 230; 288 /* secondary head */ 289 si->ps.max_dac2_clock = 0; 290 si->ps.max_dac2_clock_8 = 0; 291 si->ps.max_dac2_clock_16 = 0; 292 si->ps.max_dac2_clock_24 = 0; 293 si->ps.max_dac2_clock_32 = 0; 294 /* 'failsave' values */ 295 si->ps.max_dac2_clock_32dh = 0; 296 //fixme: primary & secondary_dvi should be overrule-able via nv.settings 297 si->ps.primary_dvi = false; 298 si->ps.secondary_dvi = false; 299 //fixme: is this needed for nv acc? 300 //fail-safe mode for now: 301 si->ps.sdram = true; 302 303 /* not used (yet) because no coldstart will be attempted (yet) */ 304 si->ps.std_engine_clock = 125; 305 si->ps.std_memory_clock = 150; 306 } 307 308 void pinsnv6_fake(void) 309 { 310 /* carefull not to take to high limits, and high should be >= 2x low. */ 311 si->ps.max_system_vco = 300; 312 si->ps.min_system_vco = 128; 313 si->ps.max_pixel_vco = 300; 314 si->ps.min_pixel_vco = 128; 315 si->ps.max_video_vco = 0; 316 si->ps.min_video_vco = 0; 317 si->ps.max_dac1_clock = 300; 318 si->ps.max_dac1_clock_8 = 300; 319 si->ps.max_dac1_clock_16 = 300; 320 /* 'failsave' values */ 321 si->ps.max_dac1_clock_24 = 270; 322 si->ps.max_dac1_clock_32 = 230; 323 si->ps.max_dac1_clock_32dh = 230; 324 /* secondary head */ 325 si->ps.max_dac2_clock = 0; 326 si->ps.max_dac2_clock_8 = 0; 327 si->ps.max_dac2_clock_16 = 0; 328 si->ps.max_dac2_clock_24 = 0; 329 si->ps.max_dac2_clock_32 = 0; 330 /* 'failsave' values */ 331 si->ps.max_dac2_clock_32dh = 0; 332 //fixme: primary & secondary_dvi should be overrule-able via nv.settings 333 si->ps.primary_dvi = false; 334 si->ps.secondary_dvi = false; 335 //fixme: is this needed for nv acc? 336 //fail-safe mode for now: 337 si->ps.sdram = true; 338 339 /* not used (yet) because no coldstart will be attempted (yet) */ 340 si->ps.std_engine_clock = 100; 341 si->ps.std_memory_clock = 125; 342 } 343 344 void pinsnv10_arch_fake(void) 345 { 346 /* carefull not to take to high limits, and high should be >= 2x low. */ 347 si->ps.max_system_vco = 350; 348 si->ps.min_system_vco = 128; 349 si->ps.max_pixel_vco = 350; 350 si->ps.min_pixel_vco = 128; 351 si->ps.max_video_vco = 350; 352 si->ps.min_video_vco = 128; 353 si->ps.max_dac1_clock = 350; 354 si->ps.max_dac1_clock_8 = 350; 355 si->ps.max_dac1_clock_16 = 350; 356 /* 'failsave' values */ 357 si->ps.max_dac1_clock_24 = 320; 358 si->ps.max_dac1_clock_32 = 280; 359 si->ps.max_dac1_clock_32dh = 250; 360 /* secondary head */ 361 //fixme? assuming... 362 si->ps.max_dac2_clock = 200; 363 si->ps.max_dac2_clock_8 = 200; 364 si->ps.max_dac2_clock_16 = 200; 365 si->ps.max_dac2_clock_24 = 200; 366 si->ps.max_dac2_clock_32 = 200; 367 /* 'failsave' values */ 368 si->ps.max_dac2_clock_32dh = 180; 369 //fixme: primary & secondary_dvi should be overrule-able via nv.settings 370 si->ps.primary_dvi = false; 371 si->ps.secondary_dvi = false; 372 //fixme: is this needed for nv acc? 373 //fail-safe mode for now: 374 si->ps.sdram = true; 375 376 /* not used (yet) because no coldstart will be attempted (yet) */ 377 si->ps.std_engine_clock = 120; 378 si->ps.std_memory_clock = 150; 379 } 380 381 void pinsnv20_arch_fake(void) 382 { 383 /* carefull not to take to high limits, and high should be >= 2x low. */ 384 si->ps.max_system_vco = 350; 385 si->ps.min_system_vco = 128; 386 si->ps.max_pixel_vco = 350; 387 si->ps.min_pixel_vco = 128; 388 si->ps.max_video_vco = 350; 389 si->ps.min_video_vco = 128; 390 si->ps.max_dac1_clock = 350; 391 si->ps.max_dac1_clock_8 = 350; 392 si->ps.max_dac1_clock_16 = 350; 393 /* 'failsave' values */ 394 si->ps.max_dac1_clock_24 = 320; 395 si->ps.max_dac1_clock_32 = 280; 396 si->ps.max_dac1_clock_32dh = 250; 397 /* secondary head */ 398 //fixme? assuming... 399 si->ps.max_dac2_clock = 200; 400 si->ps.max_dac2_clock_8 = 200; 401 si->ps.max_dac2_clock_16 = 200; 402 si->ps.max_dac2_clock_24 = 200; 403 si->ps.max_dac2_clock_32 = 200; 404 /* 'failsave' values */ 405 si->ps.max_dac2_clock_32dh = 180; 406 //fixme: primary & secondary_dvi should be overrule-able via nv.settings 407 si->ps.primary_dvi = false; 408 si->ps.secondary_dvi = false; 409 //fixme: is this needed for nv acc? 410 //fail-safe mode for now: 411 si->ps.sdram = true; 412 413 /* not used (yet) because no coldstart will be attempted (yet) */ 414 si->ps.std_engine_clock = 175; 415 si->ps.std_memory_clock = 200; 416 } 417 418 void pinsnv30_arch_fake(void) 419 { 420 /* carefull not to take to high limits, and high should be >= 2x low. */ 421 si->ps.max_system_vco = 350; 422 si->ps.min_system_vco = 128; 423 si->ps.max_pixel_vco = 350; 424 si->ps.min_pixel_vco = 128; 425 si->ps.max_video_vco = 350; 426 si->ps.min_video_vco = 128; 427 si->ps.max_dac1_clock = 350; 428 si->ps.max_dac1_clock_8 = 350; 429 si->ps.max_dac1_clock_16 = 350; 430 /* 'failsave' values */ 431 si->ps.max_dac1_clock_24 = 320; 432 si->ps.max_dac1_clock_32 = 280; 433 si->ps.max_dac1_clock_32dh = 250; 434 /* secondary head */ 435 //fixme? assuming... 436 si->ps.max_dac2_clock = 200; 437 si->ps.max_dac2_clock_8 = 200; 438 si->ps.max_dac2_clock_16 = 200; 439 si->ps.max_dac2_clock_24 = 200; 440 si->ps.max_dac2_clock_32 = 200; 441 /* 'failsave' values */ 442 si->ps.max_dac2_clock_32dh = 180; 443 //fixme: primary & secondary_dvi should be overrule-able via nv.settings 444 si->ps.primary_dvi = false; 445 si->ps.secondary_dvi = false; 446 //fixme: is this needed for nv acc? 447 //fail-safe mode for now: 448 si->ps.sdram = true; 449 450 /* not used (yet) because no coldstart will be attempted (yet) */ 451 si->ps.std_engine_clock = 190; 452 si->ps.std_memory_clock = 190; 453 } 454 455 void getstrap_arch_nv4(void) 456 { 457 uint32 strapinfo = NV_REG32(NV32_NV4STRAPINFO); 458 459 if (strapinfo & 0x00000100) 460 { 461 /* Unified memory architecture used */ 462 si->ps.memory_size = 463 ((((strapinfo & 0x0000f000) >> 12) * 2) + 2); 464 465 LOG(8,("INFO: NV4 architecture chip with UMA detected\n")); 466 } 467 else 468 { 469 /* private memory architecture used */ 470 switch (strapinfo & 0x00000003) 471 { 472 case 0: 473 si->ps.memory_size = 32; 474 break; 475 case 1: 476 si->ps.memory_size = 4; 477 break; 478 case 2: 479 si->ps.memory_size = 8; 480 break; 481 case 3: 482 si->ps.memory_size = 16; 483 break; 484 } 485 } 486 487 strapinfo = NV_REG32(NV32_NVSTRAPINFO2); 488 489 /* determine PLL reference crystal frequency */ 490 if (strapinfo & 0x00000040) 491 si->ps.f_ref = 14.31818; 492 else 493 si->ps.f_ref = 13.50000; 494 495 /* these cards are always singlehead */ 496 si->ps.secondary_head = false; 497 } 498 499 void getstrap_arch_nv10_20(void) 500 { 501 uint32 dev_manID = CFGR(DEVID); 502 uint32 strapinfo = NV_REG32(NV32_NV10STRAPINFO); 503 504 switch (dev_manID) 505 { 506 case 0x01a010de: /* Nvidia GeForce2 Integrated GPU */ 507 si->ps.memory_size = (((CFGR(GF2IGPU) & 0x000007c0) >> 6) + 1); 508 break; 509 case 0x01f010de: /* Nvidia GeForce4 MX Integrated GPU */ 510 si->ps.memory_size = (((CFGR(GF4MXIGPU) & 0x000007f0) >> 4) + 1); 511 //remove this line if det. is OK: int amt = pciReadLong(pciTag(0, 0, 1), 0x84); 512 break; 513 default: 514 switch ((strapinfo & 0x0ff00000) >> 20) 515 { 516 case 2: 517 si->ps.memory_size = 2; 518 break; 519 case 4: 520 si->ps.memory_size = 4; 521 break; 522 case 8: 523 si->ps.memory_size = 8; 524 break; 525 case 16: 526 si->ps.memory_size = 16; 527 break; 528 case 32: 529 si->ps.memory_size = 32; 530 break; 531 case 64: 532 si->ps.memory_size = 64; 533 break; 534 case 128: 535 si->ps.memory_size = 128; 536 break; 537 default: 538 si->ps.memory_size = 16; 539 540 LOG(8,("INFO: NV10/20 architecture chip with unknown RAM amount detected;\n")); 541 LOG(8,("INFO: Setting 16Mb\n")); 542 break; 543 } 544 } 545 546 strapinfo = NV_REG32(NV32_NVSTRAPINFO2); 547 548 /* determine PLL reference crystal frequency: three types are used... */ 549 if (strapinfo & 0x00000040) 550 si->ps.f_ref = 14.31818; 551 else 552 si->ps.f_ref = 13.50000; 553 554 switch (dev_manID & 0xfff0ffff) 555 { 556 /* Nvidia cards: */ 557 case 0x017010de: 558 case 0x018010de: 559 case 0x01f010de: 560 case 0x025010de: 561 case 0x028010de: 562 case 0x030010de: 563 case 0x031010de: 564 case 0x032010de: 565 case 0x033010de: 566 /* Varisys cards: */ 567 case 0x35001888: 568 if (strapinfo & 0x00400000) si->ps.f_ref = 27.00000; 569 break; 570 default: 571 break; 572 } 573 574 /* determine if we have a dualhead card */ 575 switch (dev_manID & 0xfff0ffff) 576 { 577 /* Nvidia cards: */ 578 case 0x011010de: 579 case 0x017010de: 580 case 0x018010de: 581 case 0x01f010de: 582 case 0x025010de: 583 case 0x028010de: 584 case 0x030010de: 585 case 0x031010de: 586 case 0x032010de: 587 case 0x033010de: 588 /* Varisys cards: */ 589 case 0x35001888: 590 si->ps.secondary_head = true; 591 break; 592 default: 593 si->ps.secondary_head = false; 594 break; 595 } 596 } 597 598 void dump_pins(void) 599 { 600 char *msg = ""; 601 602 LOG(2,("INFO: pinsdump follows:\n")); 603 LOG(2,("f_ref: %fMhz\n", si->ps.f_ref)); 604 LOG(2,("max_system_vco: %dMhz\n", si->ps.max_system_vco)); 605 LOG(2,("min_system_vco: %dMhz\n", si->ps.min_system_vco)); 606 LOG(2,("max_pixel_vco: %dMhz\n", si->ps.max_pixel_vco)); 607 LOG(2,("min_pixel_vco: %dMhz\n", si->ps.min_pixel_vco)); 608 LOG(2,("max_video_vco: %dMhz\n", si->ps.max_video_vco)); 609 LOG(2,("min_video_vco: %dMhz\n", si->ps.min_video_vco)); 610 LOG(2,("std_engine_clock: %dMhz\n", si->ps.std_engine_clock)); 611 LOG(2,("std_memory_clock: %dMhz\n", si->ps.std_memory_clock)); 612 LOG(2,("max_dac1_clock: %dMhz\n", si->ps.max_dac1_clock)); 613 LOG(2,("max_dac1_clock_8: %dMhz\n", si->ps.max_dac1_clock_8)); 614 LOG(2,("max_dac1_clock_16: %dMhz\n", si->ps.max_dac1_clock_16)); 615 LOG(2,("max_dac1_clock_24: %dMhz\n", si->ps.max_dac1_clock_24)); 616 LOG(2,("max_dac1_clock_32: %dMhz\n", si->ps.max_dac1_clock_32)); 617 LOG(2,("max_dac1_clock_32dh: %dMhz\n", si->ps.max_dac1_clock_32dh)); 618 LOG(2,("max_dac2_clock: %dMhz\n", si->ps.max_dac2_clock)); 619 LOG(2,("max_dac2_clock_8: %dMhz\n", si->ps.max_dac2_clock_8)); 620 LOG(2,("max_dac2_clock_16: %dMhz\n", si->ps.max_dac2_clock_16)); 621 LOG(2,("max_dac2_clock_24: %dMhz\n", si->ps.max_dac2_clock_24)); 622 LOG(2,("max_dac2_clock_32: %dMhz\n", si->ps.max_dac2_clock_32)); 623 LOG(2,("max_dac2_clock_32dh: %dMhz\n", si->ps.max_dac2_clock_32dh)); 624 LOG(2,("secondary_head: ")); 625 if (si->ps.secondary_head) LOG(2,("present\n")); else LOG(2,("absent\n")); 626 LOG(2,("tvout: ")); 627 if (si->ps.tvout) LOG(2,("present\n")); else LOG(2,("absent\n")); 628 /* setup TVout logmessage text */ 629 switch (si->ps.tvout_chip_type) 630 { 631 case NONE: 632 msg = "No"; 633 break; 634 case CH7003: 635 msg = "Chrontel CH7003"; 636 break; 637 case CH7004: 638 msg = "Chrontel CH7004"; 639 break; 640 case CH7005: 641 msg = "Chrontel CH7005"; 642 break; 643 case CH7006: 644 msg = "Chrontel CH7006"; 645 break; 646 case CH7007: 647 msg = "Chrontel CH7007"; 648 break; 649 case SAA7102: 650 msg = "Philips SAA7102"; 651 break; 652 case SAA7108: 653 msg = "Philips SAA7108"; 654 break; 655 case BT868: 656 msg = "Brooktree/Conexant BT868"; 657 break; 658 case BT869: 659 msg = "Brooktree/Conexant BT869"; 660 break; 661 case CX25870: 662 msg = "Conexant CX25870"; 663 break; 664 case CX25871: 665 msg = "Conexant CX25871"; 666 break; 667 case NVIDIA: 668 msg = "Nvidia internal"; 669 break; 670 default: 671 msg = "Unknown"; 672 break; 673 } 674 LOG(2, ("%s TVout chip detected\n", msg)); 675 LOG(2,("primary_dvi: ")); 676 if (si->ps.primary_dvi) LOG(2,("present\n")); else LOG(2,("absent\n")); 677 LOG(2,("secondary_dvi: ")); 678 if (si->ps.secondary_dvi) LOG(2,("present\n")); else LOG(2,("absent\n")); 679 LOG(2,("card memory_size: %dMb\n", si->ps.memory_size)); 680 LOG(2,("sdram: ")); 681 if (si->ps.sdram) LOG(2,("SDRAM card\n")); else LOG(2,("SGRAM card\n")); 682 LOG(2,("laptop: ")); 683 if (si->ps.laptop) LOG(2,("yes\n")); else LOG(2,("no\n")); 684 LOG(2,("INFO: end pinsdump.\n")); 685 } 686