xref: /haiku/src/add-ons/accelerants/nvidia/engine/nv_globals.h (revision 0669fe20bd6ea42d6db669c6776898093ad1bbe6)
16f1ef82cSshatty extern int fd;
26f1ef82cSshatty extern shared_info *si;
36f1ef82cSshatty extern area_id shared_info_area;
46f1ef82cSshatty extern area_id regs_area;
56f1ef82cSshatty extern vuint32 *regs;
66f1ef82cSshatty extern display_mode *my_mode_list;
76f1ef82cSshatty extern area_id my_mode_list_area;
86f1ef82cSshatty extern int accelerantIsClone;
96f1ef82cSshatty 
106f1ef82cSshatty extern nv_get_set_pci nv_pci_access;
11*0669fe20SRudolf Cornelissen 
12*0669fe20SRudolf Cornelissen 
13*0669fe20SRudolf Cornelissen typedef status_t (*crtc_validate_timing)(uint16*, uint16*, uint16*, uint16*, uint16*, uint16*, uint16*, uint16*);
14*0669fe20SRudolf Cornelissen typedef status_t (*crtc_set_timing)(display_mode);
15*0669fe20SRudolf Cornelissen typedef status_t (*crtc_depth)(int);
16*0669fe20SRudolf Cornelissen typedef status_t (*crtc_dpms)(bool, bool, bool);
17*0669fe20SRudolf Cornelissen typedef status_t (*crtc_dpms_fetch)(bool*, bool*, bool*);
18*0669fe20SRudolf Cornelissen typedef status_t (*crtc_set_display_pitch)(void);
19*0669fe20SRudolf Cornelissen typedef status_t (*crtc_set_display_start)(uint32, uint8);
20*0669fe20SRudolf Cornelissen typedef status_t (*crtc_cursor_init)(void);
21*0669fe20SRudolf Cornelissen typedef status_t (*crtc_cursor_show)(void);
22*0669fe20SRudolf Cornelissen typedef status_t (*crtc_cursor_hide)(void);
23*0669fe20SRudolf Cornelissen typedef status_t (*crtc_cursor_define)(uint8*, uint8*);
24*0669fe20SRudolf Cornelissen typedef status_t (*crtc_cursor_position)(uint16, uint16);
25*0669fe20SRudolf Cornelissen 
26*0669fe20SRudolf Cornelissen crtc_validate_timing 	head1_validate_timing;
27*0669fe20SRudolf Cornelissen crtc_set_timing 		head1_set_timing;
28*0669fe20SRudolf Cornelissen crtc_depth				head1_depth;
29*0669fe20SRudolf Cornelissen crtc_dpms				head1_dpms;
30*0669fe20SRudolf Cornelissen crtc_dpms_fetch			head1_dpms_fetch;
31*0669fe20SRudolf Cornelissen crtc_set_display_pitch	head1_set_display_pitch;
32*0669fe20SRudolf Cornelissen crtc_set_display_start	head1_set_display_start;
33*0669fe20SRudolf Cornelissen crtc_cursor_init		head1_cursor_init;
34*0669fe20SRudolf Cornelissen crtc_cursor_show		head1_cursor_show;
35*0669fe20SRudolf Cornelissen crtc_cursor_hide		head1_cursor_hide;
36*0669fe20SRudolf Cornelissen crtc_cursor_define		head1_cursor_define;
37*0669fe20SRudolf Cornelissen crtc_cursor_position	head1_cursor_position;
38*0669fe20SRudolf Cornelissen 
39*0669fe20SRudolf Cornelissen crtc_validate_timing	head2_validate_timing;
40*0669fe20SRudolf Cornelissen crtc_set_timing			head2_set_timing;
41*0669fe20SRudolf Cornelissen crtc_depth				head2_depth;
42*0669fe20SRudolf Cornelissen crtc_dpms				head2_dpms;
43*0669fe20SRudolf Cornelissen crtc_dpms_fetch			head2_dpms_fetch;
44*0669fe20SRudolf Cornelissen crtc_set_display_pitch	head2_set_display_pitch;
45*0669fe20SRudolf Cornelissen crtc_set_display_start	head2_set_display_start;
46*0669fe20SRudolf Cornelissen crtc_cursor_init		head2_cursor_init;
47*0669fe20SRudolf Cornelissen crtc_cursor_show		head2_cursor_show;
48*0669fe20SRudolf Cornelissen crtc_cursor_hide		head2_cursor_hide;
49*0669fe20SRudolf Cornelissen crtc_cursor_define		head2_cursor_define;
50*0669fe20SRudolf Cornelissen crtc_cursor_position	head2_cursor_position;
51