1 /* program the secondary DAC */ 2 /* Author: 3 Rudolf Cornelissen 12/2003-1/2004 4 */ 5 6 #define MODULE_BIT 0x00001000 7 8 #include "nv_std.h" 9 10 static status_t nv10_nv20_dac2_pix_pll_find( 11 display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test); 12 13 /* see if an analog VGA monitor is connected to DAC */ 14 bool nv_dac2_crt_connected() 15 { 16 uint32 output, dac; 17 bool present; 18 19 //fixme? checkout NV11... 20 /* save output connector setting */ 21 output = DAC2R(OUTPUT); 22 /* save DAC state */ 23 dac = DAC2R(TSTCTRL); 24 25 /* turn on DAC2 */ 26 DAC2W(TSTCTRL, (DAC2R(TSTCTRL) & 0xfffeffff)); 27 /* select primary head and turn off CRT (and DVI?) outputs */ 28 DAC2W(OUTPUT, (output & 0x0000feee)); 29 /* wait for signal lines to stabilize */ 30 snooze(1000); 31 /* re-enable CRT output */ 32 DAC2W(OUTPUT, (DAC2R(OUTPUT) | 0x00000001)); 33 34 /* setup RGB test signal levels to approx 30% of DAC range and enable them 35 * (NOTE: testsignal function block resides in DAC1 only (!)) */ 36 DACW(TSTDATA, ((0x2 << 30) | (0x140 << 20) | (0x140 << 10) | (0x140 << 0))); 37 /* route test signals to output 38 * (NOTE: testsignal function block resides in DAC1 only (!)) */ 39 DACW(TSTCTRL, (DACR(TSTCTRL) | 0x00001000)); 40 /* wait for signal lines to stabilize */ 41 snooze(1000); 42 43 /* do actual detection: all signals paths high == CRT connected */ 44 if (DAC2R(TSTCTRL) & 0x10000000) 45 { 46 present = true; 47 LOG(4,("DAC2: CRT detected\n")); 48 } 49 else 50 { 51 present = false; 52 LOG(4,("DAC2: no CRT detected\n")); 53 } 54 55 /* kill test signal routing 56 * (NOTE: testsignal function block resides in DAC1 only (!)) */ 57 DACW(TSTCTRL, (DACR(TSTCTRL) & 0xffffefff)); 58 59 /* restore output connector setting */ 60 DAC2W(OUTPUT, output); 61 /* restore DAC state */ 62 DAC2W(TSTCTRL, dac); 63 64 return present; 65 } 66 67 /*set the mode, brightness is a value from 0->2 (where 1 is equivalent to direct)*/ 68 status_t nv_dac2_mode(int mode,float brightness) 69 { 70 uint8 *r,*g,*b; 71 int i, ri; 72 73 /*set colour arrays to point to space reserved in shared info*/ 74 r = si->color_data; 75 g = r + 256; 76 b = g + 256; 77 78 LOG(4,("DAC2: Setting screen mode %d brightness %f\n", mode, brightness)); 79 /* init the palette for brightness specified */ 80 /* (Nvidia cards always use MSbits from screenbuffer as index for PAL) */ 81 for (i = 0; i < 256; i++) 82 { 83 ri = i * brightness; 84 if (ri > 255) ri = 255; 85 b[i] = g[i] = r[i] = ri; 86 } 87 88 if (nv_dac2_palette(r,g,b) != B_OK) return B_ERROR; 89 90 /* disable palette RAM adressing mask */ 91 NV_REG8(NV8_PAL2MASK) = 0xff; 92 LOG(2,("DAC2: PAL pixrdmsk readback $%02x\n", NV_REG8(NV8_PAL2MASK))); 93 94 return B_OK; 95 } 96 97 /*program the DAC palette using the given r,g,b values*/ 98 status_t nv_dac2_palette(uint8 r[256],uint8 g[256],uint8 b[256]) 99 { 100 int i; 101 102 LOG(4,("DAC2: setting palette\n")); 103 104 /* select first PAL adress before starting programming */ 105 NV_REG8(NV8_PAL2INDW) = 0x00; 106 107 /* loop through all 256 to program DAC */ 108 for (i = 0; i < 256; i++) 109 { 110 /* the 6 implemented bits are on b0-b5 of the bus */ 111 NV_REG8(NV8_PAL2DATA) = r[i]; 112 NV_REG8(NV8_PAL2DATA) = g[i]; 113 NV_REG8(NV8_PAL2DATA) = b[i]; 114 } 115 if (NV_REG8(NV8_PAL2INDW) != 0x00) 116 { 117 LOG(8,("DAC2: PAL write index incorrect after programming\n")); 118 return B_ERROR; 119 } 120 if (1) 121 {//reread LUT 122 uint8 R, G, B; 123 124 /* select first PAL adress to read (modulo 3 counter) */ 125 NV_REG8(NV8_PAL2INDR) = 0x00; 126 for (i = 0; i < 256; i++) 127 { 128 R = NV_REG8(NV8_PAL2DATA); 129 G = NV_REG8(NV8_PAL2DATA); 130 B = NV_REG8(NV8_PAL2DATA); 131 if ((r[i] != R) || (g[i] != G) || (b[i] != B)) 132 LOG(1,("DAC2 palette %d: w %x %x %x, r %x %x %x\n", i, r[i], g[i], b[i], R, G, B)); // apsed 133 } 134 } 135 136 return B_OK; 137 } 138 139 /*program the pixpll - frequency in kHz*/ 140 status_t nv_dac2_set_pix_pll(display_mode target) 141 { 142 uint8 m=0,n=0,p=0; 143 // uint time = 0; 144 145 float pix_setting, req_pclk; 146 status_t result; 147 148 req_pclk = (target.timing.pixel_clock)/1000.0; 149 LOG(4,("DAC2: Setting PIX PLL for pixelclock %f\n", req_pclk)); 150 151 /* signal that we actually want to set the mode */ 152 result = nv_dac2_pix_pll_find(target,&pix_setting,&m,&n,&p, 1); 153 if (result != B_OK) 154 { 155 return result; 156 } 157 158 /*reprogram (disable,select,wait for stability,enable)*/ 159 // DXIW(PIXCLKCTRL,(DXIR(PIXCLKCTRL)&0x0F)|0x04); /*disable the PIXPLL*/ 160 // DXIW(PIXCLKCTRL,(DXIR(PIXCLKCTRL)&0x0C)|0x01); /*select the PIXPLL*/ 161 162 /* program new frequency */ 163 DAC2W(PIXPLLC, ((p << 16) | (n << 8) | m)); 164 165 /* program 2nd set N and M scalers if they exist (b31=1 enables them) */ 166 if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) 167 DAC2W(PIXPLLC2, 0x80000401); 168 169 /* Wait for the PIXPLL frequency to lock until timeout occurs */ 170 //fixme: do NV cards have a LOCK indication bit?? 171 /* while((!(DXIR(PIXPLLSTAT)&0x40)) & (time <= 2000)) 172 { 173 time++; 174 snooze(1); 175 } 176 177 if (time > 2000) 178 LOG(2,("DAC: PIX PLL frequency not locked!\n")); 179 else 180 LOG(2,("DAC: PIX PLL frequency locked\n")); 181 DXIW(PIXCLKCTRL,DXIR(PIXCLKCTRL)&0x0B); //enable the PIXPLL 182 */ 183 184 //for now: 185 /* Give the PIXPLL frequency some time to lock... */ 186 snooze(1000); 187 LOG(2,("DAC2: PIX PLL frequency should be locked now...\n")); 188 189 return B_OK; 190 } 191 192 /* find nearest valid pix pll */ 193 status_t nv_dac2_pix_pll_find 194 (display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test) 195 { 196 switch (si->ps.card_type) { 197 default: return nv10_nv20_dac2_pix_pll_find(target, calc_pclk, m_result, n_result, p_result, test); 198 } 199 return B_ERROR; 200 } 201 202 /* find nearest valid pixel PLL setting */ 203 static status_t nv10_nv20_dac2_pix_pll_find( 204 display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test) 205 { 206 int m = 0, n = 0, p = 0/*, m_max*/; 207 float error, error_best = 999999999; 208 int best[3]; 209 float f_vco, max_pclk; 210 float req_pclk = target.timing.pixel_clock/1000.0; 211 212 /* determine the max. reference-frequency postscaler setting for the 213 * current card (see G100, G200 and G400 specs). */ 214 /* switch(si->ps.card_type) 215 { 216 case G100: 217 LOG(4,("DAC: G100 restrictions apply\n")); 218 m_max = 7; 219 break; 220 case G200: 221 LOG(4,("DAC: G200 restrictions apply\n")); 222 m_max = 7; 223 break; 224 default: 225 LOG(4,("DAC: G400/G400MAX restrictions apply\n")); 226 m_max = 32; 227 break; 228 } 229 */ 230 LOG(4,("DAC2: NV10/NV20 restrictions apply\n")); 231 232 /* determine the max. pixelclock for the current videomode */ 233 switch (target.space) 234 { 235 case B_CMAP8: 236 max_pclk = si->ps.max_dac2_clock_8; 237 break; 238 case B_RGB15_LITTLE: 239 case B_RGB16_LITTLE: 240 max_pclk = si->ps.max_dac2_clock_16; 241 break; 242 case B_RGB24_LITTLE: 243 max_pclk = si->ps.max_dac2_clock_24; 244 break; 245 case B_RGB32_LITTLE: 246 max_pclk = si->ps.max_dac2_clock_32; 247 break; 248 default: 249 /* use fail-safe value */ 250 max_pclk = si->ps.max_dac2_clock_32; 251 break; 252 } 253 /* if some dualhead mode is active, an extra restriction might apply */ 254 if ((target.flags & DUALHEAD_BITS) && (target.space == B_RGB32_LITTLE)) 255 max_pclk = si->ps.max_dac2_clock_32dh; 256 257 /* Make sure the requested pixelclock is within the PLL's operational limits */ 258 /* lower limit is min_pixel_vco divided by highest postscaler-factor */ 259 if (req_pclk < (si->ps.min_video_vco / 16.0)) 260 { 261 LOG(4,("DAC2: clamping pixclock: requested %fMHz, set to %fMHz\n", 262 req_pclk, (float)(si->ps.min_video_vco / 16.0))); 263 req_pclk = (si->ps.min_video_vco / 16.0); 264 } 265 /* upper limit is given by pins in combination with current active mode */ 266 if (req_pclk > max_pclk) 267 { 268 LOG(4,("DAC2: clamping pixclock: requested %fMHz, set to %fMHz\n", 269 req_pclk, (float)max_pclk)); 270 req_pclk = max_pclk; 271 } 272 273 /* iterate through all valid PLL postscaler settings */ 274 for (p=0x01; p < 0x20; p = p<<1) 275 { 276 /* calculate the needed VCO frequency for this postscaler setting */ 277 f_vco = req_pclk * p; 278 279 /* check if this is within range of the VCO specs */ 280 if ((f_vco >= si->ps.min_video_vco) && (f_vco <= si->ps.max_video_vco)) 281 { 282 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 283 if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) f_vco /= 4; 284 285 /* iterate trough all valid reference-frequency postscaler settings */ 286 for (m = 7; m <= 14; m++) 287 { 288 /* check if phase-discriminator will be within operational limits */ 289 if (((si->ps.f_ref / m) < 1.0) || ((si->ps.f_ref / m) > 2.0)) continue; 290 291 /* calculate VCO postscaler setting for current setup.. */ 292 n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5); 293 /* ..and check for validity */ 294 if ((n < 1) || (n > 255)) continue; 295 296 /* find error in frequency this setting gives */ 297 if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) 298 { 299 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 300 error = fabs((req_pclk / 4) - (((si->ps.f_ref / m) * n) / p)); 301 } 302 else 303 error = fabs(req_pclk - (((si->ps.f_ref / m) * n) / p)); 304 305 /* note the setting if best yet */ 306 if (error < error_best) 307 { 308 error_best = error; 309 best[0]=m; 310 best[1]=n; 311 best[2]=p; 312 } 313 } 314 } 315 } 316 317 /* setup the scalers programming values for found optimum setting */ 318 m = best[0]; 319 n = best[1]; 320 p = best[2]; 321 322 /* log the VCO frequency found */ 323 f_vco = ((si->ps.f_ref / m) * n); 324 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 325 if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) f_vco *= 4; 326 327 LOG(2,("DAC2: pix VCO frequency found %fMhz\n", f_vco)); 328 329 /* return the results */ 330 *calc_pclk = (f_vco / p); 331 *m_result = m; 332 *n_result = n; 333 switch(p) 334 { 335 case 1: 336 p = 0x00; 337 break; 338 case 2: 339 p = 0x01; 340 break; 341 case 4: 342 p = 0x02; 343 break; 344 case 8: 345 p = 0x03; 346 break; 347 case 16: 348 p = 0x04; 349 break; 350 } 351 *p_result = p; 352 353 /* display the found pixelclock values */ 354 LOG(2,("DAC2: pix PLL check: requested %fMHz got %fMHz, mnp 0x%02x 0x%02x 0x%02x\n", 355 req_pclk, *calc_pclk, *m_result, *n_result, *p_result)); 356 357 return B_OK; 358 } 359