1 /* program the secondary DAC */ 2 /* Author: 3 Rudolf Cornelissen 12/2003-5/2004 4 */ 5 6 #define MODULE_BIT 0x00001000 7 8 #include "nv_std.h" 9 10 static status_t nv10_nv20_dac2_pix_pll_find( 11 display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test); 12 13 /* see if an analog VGA monitor is connected to connector #2 */ 14 bool nv_dac2_crt_connected() 15 { 16 uint32 output, dac; 17 bool present; 18 19 /* NOTE: 20 * NV11 can't do this: It will report DAC1 status instead because it HAS no 21 * actual secondary DAC function. */ 22 /* (It DOES have a secondary palette RAM and pixelclock PLL though.) */ 23 24 /* save output connector setting */ 25 output = DAC2R(OUTPUT); 26 /* save DAC state */ 27 dac = DAC2R(TSTCTRL); 28 29 /* turn on DAC2 */ 30 DAC2W(TSTCTRL, (DAC2R(TSTCTRL) & 0xfffeffff)); 31 /* select primary head and turn off CRT (and DVI?) outputs */ 32 DAC2W(OUTPUT, (output & 0x0000feee)); 33 /* wait for signal lines to stabilize */ 34 snooze(1000); 35 /* re-enable CRT output */ 36 DAC2W(OUTPUT, (DAC2R(OUTPUT) | 0x00000001)); 37 38 /* setup RGB test signal levels to approx 30% of DAC range and enable them 39 * (NOTE: testsignal function block resides in DAC1 only (!)) */ 40 DACW(TSTDATA, ((0x2 << 30) | (0x140 << 20) | (0x140 << 10) | (0x140 << 0))); 41 /* route test signals to output 42 * (NOTE: testsignal function block resides in DAC1 only (!)) */ 43 DACW(TSTCTRL, (DACR(TSTCTRL) | 0x00001000)); 44 /* wait for signal lines to stabilize */ 45 snooze(1000); 46 47 /* do actual detection: all signals paths high == CRT connected */ 48 if (DAC2R(TSTCTRL) & 0x10000000) 49 { 50 present = true; 51 LOG(4,("DAC2: CRT detected on connector #2\n")); 52 } 53 else 54 { 55 present = false; 56 LOG(4,("DAC2: no CRT detected on connector #2\n")); 57 } 58 59 /* kill test signal routing 60 * (NOTE: testsignal function block resides in DAC1 only (!)) */ 61 DACW(TSTCTRL, (DACR(TSTCTRL) & 0xffffefff)); 62 63 /* restore output connector setting */ 64 DAC2W(OUTPUT, output); 65 /* restore DAC state */ 66 DAC2W(TSTCTRL, dac); 67 68 return present; 69 } 70 71 /*set the mode, brightness is a value from 0->2 (where 1 is equivalent to direct)*/ 72 status_t nv_dac2_mode(int mode,float brightness) 73 { 74 uint8 *r,*g,*b; 75 int i, ri; 76 77 /*set colour arrays to point to space reserved in shared info*/ 78 r = si->color_data; 79 g = r + 256; 80 b = g + 256; 81 82 LOG(4,("DAC2: Setting screen mode %d brightness %f\n", mode, brightness)); 83 /* init the palette for brightness specified */ 84 /* (Nvidia cards always use MSbits from screenbuffer as index for PAL) */ 85 for (i = 0; i < 256; i++) 86 { 87 ri = i * brightness; 88 if (ri > 255) ri = 255; 89 b[i] = g[i] = r[i] = ri; 90 } 91 92 if (nv_dac2_palette(r,g,b) != B_OK) return B_ERROR; 93 94 /* disable palette RAM adressing mask */ 95 NV_REG8(NV8_PAL2MASK) = 0xff; 96 LOG(2,("DAC2: PAL pixrdmsk readback $%02x\n", NV_REG8(NV8_PAL2MASK))); 97 98 return B_OK; 99 } 100 101 /*program the DAC palette using the given r,g,b values*/ 102 status_t nv_dac2_palette(uint8 r[256],uint8 g[256],uint8 b[256]) 103 { 104 int i; 105 106 LOG(4,("DAC2: setting palette\n")); 107 108 /* select first PAL adress before starting programming */ 109 NV_REG8(NV8_PAL2INDW) = 0x00; 110 111 /* loop through all 256 to program DAC */ 112 for (i = 0; i < 256; i++) 113 { 114 /* the 6 implemented bits are on b0-b5 of the bus */ 115 NV_REG8(NV8_PAL2DATA) = r[i]; 116 NV_REG8(NV8_PAL2DATA) = g[i]; 117 NV_REG8(NV8_PAL2DATA) = b[i]; 118 } 119 if (NV_REG8(NV8_PAL2INDW) != 0x00) 120 { 121 LOG(8,("DAC2: PAL write index incorrect after programming\n")); 122 return B_ERROR; 123 } 124 if (1) 125 {//reread LUT 126 uint8 R, G, B; 127 128 /* select first PAL adress to read (modulo 3 counter) */ 129 NV_REG8(NV8_PAL2INDR) = 0x00; 130 for (i = 0; i < 256; i++) 131 { 132 R = NV_REG8(NV8_PAL2DATA); 133 G = NV_REG8(NV8_PAL2DATA); 134 B = NV_REG8(NV8_PAL2DATA); 135 if ((r[i] != R) || (g[i] != G) || (b[i] != B)) 136 LOG(1,("DAC2 palette %d: w %x %x %x, r %x %x %x\n", i, r[i], g[i], b[i], R, G, B)); // apsed 137 } 138 } 139 140 return B_OK; 141 } 142 143 /*program the pixpll - frequency in kHz*/ 144 status_t nv_dac2_set_pix_pll(display_mode target) 145 { 146 uint8 m=0,n=0,p=0; 147 // uint time = 0; 148 149 float pix_setting, req_pclk; 150 status_t result; 151 152 /* fix a DVI or laptop flatpanel to 62Hz refresh! 153 * (we can't risk getting below 60.0Hz as some panels shut-off then!) */ 154 /* Note: 155 * The pixelclock drives the flatpanel modeline, not the CRTC modeline. */ 156 if (si->ps.tmds2_active) 157 { 158 LOG(4,("DAC2: Fixing DFP refresh to 62Hz!\n")); 159 160 /* use the panel's modeline to determine the needed pixelclock */ 161 target.timing.pixel_clock = si->ps.p2_timing.pixel_clock; 162 } 163 164 req_pclk = (target.timing.pixel_clock)/1000.0; 165 LOG(4,("DAC2: Setting PIX PLL for pixelclock %f\n", req_pclk)); 166 167 /* signal that we actually want to set the mode */ 168 result = nv_dac2_pix_pll_find(target,&pix_setting,&m,&n,&p, 1); 169 if (result != B_OK) 170 { 171 return result; 172 } 173 174 /*reprogram (disable,select,wait for stability,enable)*/ 175 // DXIW(PIXCLKCTRL,(DXIR(PIXCLKCTRL)&0x0F)|0x04); /*disable the PIXPLL*/ 176 // DXIW(PIXCLKCTRL,(DXIR(PIXCLKCTRL)&0x0C)|0x01); /*select the PIXPLL*/ 177 178 /* program new frequency */ 179 DAC2W(PIXPLLC, ((p << 16) | (n << 8) | m)); 180 181 /* program 2nd set N and M scalers if they exist (b31=1 enables them) */ 182 if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) 183 DAC2W(PIXPLLC2, 0x80000401); 184 185 /* Wait for the PIXPLL frequency to lock until timeout occurs */ 186 //fixme: do NV cards have a LOCK indication bit?? 187 /* while((!(DXIR(PIXPLLSTAT)&0x40)) & (time <= 2000)) 188 { 189 time++; 190 snooze(1); 191 } 192 193 if (time > 2000) 194 LOG(2,("DAC: PIX PLL frequency not locked!\n")); 195 else 196 LOG(2,("DAC: PIX PLL frequency locked\n")); 197 DXIW(PIXCLKCTRL,DXIR(PIXCLKCTRL)&0x0B); //enable the PIXPLL 198 */ 199 200 //for now: 201 /* Give the PIXPLL frequency some time to lock... */ 202 snooze(1000); 203 LOG(2,("DAC2: PIX PLL frequency should be locked now...\n")); 204 205 return B_OK; 206 } 207 208 /* find nearest valid pix pll */ 209 status_t nv_dac2_pix_pll_find 210 (display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test) 211 { 212 switch (si->ps.card_type) { 213 default: return nv10_nv20_dac2_pix_pll_find(target, calc_pclk, m_result, n_result, p_result, test); 214 } 215 return B_ERROR; 216 } 217 218 /* find nearest valid pixel PLL setting */ 219 static status_t nv10_nv20_dac2_pix_pll_find( 220 display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test) 221 { 222 int m = 0, n = 0, p = 0/*, m_max*/; 223 float error, error_best = 999999999; 224 int best[3]; 225 float f_vco, max_pclk; 226 float req_pclk = target.timing.pixel_clock/1000.0; 227 228 /* determine the max. reference-frequency postscaler setting for the 229 * current card (see G100, G200 and G400 specs). */ 230 /* switch(si->ps.card_type) 231 { 232 case G100: 233 LOG(4,("DAC: G100 restrictions apply\n")); 234 m_max = 7; 235 break; 236 case G200: 237 LOG(4,("DAC: G200 restrictions apply\n")); 238 m_max = 7; 239 break; 240 default: 241 LOG(4,("DAC: G400/G400MAX restrictions apply\n")); 242 m_max = 32; 243 break; 244 } 245 */ 246 LOG(4,("DAC2: NV10/NV20 restrictions apply\n")); 247 248 /* determine the max. pixelclock for the current videomode */ 249 switch (target.space) 250 { 251 case B_CMAP8: 252 max_pclk = si->ps.max_dac2_clock_8; 253 break; 254 case B_RGB15_LITTLE: 255 case B_RGB16_LITTLE: 256 max_pclk = si->ps.max_dac2_clock_16; 257 break; 258 case B_RGB24_LITTLE: 259 max_pclk = si->ps.max_dac2_clock_24; 260 break; 261 case B_RGB32_LITTLE: 262 max_pclk = si->ps.max_dac2_clock_32; 263 break; 264 default: 265 /* use fail-safe value */ 266 max_pclk = si->ps.max_dac2_clock_32; 267 break; 268 } 269 /* if some dualhead mode is active, an extra restriction might apply */ 270 if ((target.flags & DUALHEAD_BITS) && (target.space == B_RGB32_LITTLE)) 271 max_pclk = si->ps.max_dac2_clock_32dh; 272 273 /* Make sure the requested pixelclock is within the PLL's operational limits */ 274 /* lower limit is min_pixel_vco divided by highest postscaler-factor */ 275 if (req_pclk < (si->ps.min_video_vco / 16.0)) 276 { 277 LOG(4,("DAC2: clamping pixclock: requested %fMHz, set to %fMHz\n", 278 req_pclk, (float)(si->ps.min_video_vco / 16.0))); 279 req_pclk = (si->ps.min_video_vco / 16.0); 280 } 281 /* upper limit is given by pins in combination with current active mode */ 282 if (req_pclk > max_pclk) 283 { 284 LOG(4,("DAC2: clamping pixclock: requested %fMHz, set to %fMHz\n", 285 req_pclk, (float)max_pclk)); 286 req_pclk = max_pclk; 287 } 288 289 /* iterate through all valid PLL postscaler settings */ 290 for (p=0x01; p < 0x20; p = p<<1) 291 { 292 /* calculate the needed VCO frequency for this postscaler setting */ 293 f_vco = req_pclk * p; 294 295 /* check if this is within range of the VCO specs */ 296 if ((f_vco >= si->ps.min_video_vco) && (f_vco <= si->ps.max_video_vco)) 297 { 298 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 299 if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) f_vco /= 4; 300 301 /* iterate trough all valid reference-frequency postscaler settings */ 302 for (m = 7; m <= 14; m++) 303 { 304 /* check if phase-discriminator will be within operational limits */ 305 //fixme: PLL calcs will be resetup/splitup/updated... 306 if (si->ps.card_type == NV36) 307 { 308 if (((si->ps.f_ref / m) < 3.2) || ((si->ps.f_ref / m) > 6.4)) continue; 309 } 310 else 311 { 312 if (((si->ps.f_ref / m) < 1.0) || ((si->ps.f_ref / m) > 2.0)) continue; 313 } 314 315 /* calculate VCO postscaler setting for current setup.. */ 316 n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5); 317 /* ..and check for validity */ 318 if ((n < 1) || (n > 255)) continue; 319 320 /* find error in frequency this setting gives */ 321 if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) 322 { 323 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 324 error = fabs((req_pclk / 4) - (((si->ps.f_ref / m) * n) / p)); 325 } 326 else 327 error = fabs(req_pclk - (((si->ps.f_ref / m) * n) / p)); 328 329 /* note the setting if best yet */ 330 if (error < error_best) 331 { 332 error_best = error; 333 best[0]=m; 334 best[1]=n; 335 best[2]=p; 336 } 337 } 338 } 339 } 340 341 /* setup the scalers programming values for found optimum setting */ 342 m = best[0]; 343 n = best[1]; 344 p = best[2]; 345 346 /* log the VCO frequency found */ 347 f_vco = ((si->ps.f_ref / m) * n); 348 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 349 if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) f_vco *= 4; 350 351 LOG(2,("DAC2: pix VCO frequency found %fMhz\n", f_vco)); 352 353 /* return the results */ 354 *calc_pclk = (f_vco / p); 355 *m_result = m; 356 *n_result = n; 357 switch(p) 358 { 359 case 1: 360 p = 0x00; 361 break; 362 case 2: 363 p = 0x01; 364 break; 365 case 4: 366 p = 0x02; 367 break; 368 case 8: 369 p = 0x03; 370 break; 371 case 16: 372 p = 0x04; 373 break; 374 } 375 *p_result = p; 376 377 /* display the found pixelclock values */ 378 LOG(2,("DAC2: pix PLL check: requested %fMHz got %fMHz, mnp 0x%02x 0x%02x 0x%02x\n", 379 req_pclk, *calc_pclk, *m_result, *n_result, *p_result)); 380 381 return B_OK; 382 } 383