1 /* program the secondary DAC */ 2 /* Author: 3 Rudolf Cornelissen 12/2003-3/2004 4 */ 5 6 #define MODULE_BIT 0x00001000 7 8 #include "nv_std.h" 9 10 static status_t nv10_nv20_dac2_pix_pll_find( 11 display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test); 12 13 /* see if an analog VGA monitor is connected to DAC */ 14 bool nv_dac2_crt_connected() 15 { 16 uint32 output, dac; 17 bool present; 18 19 //fixme? checkout NV11... 20 /* save output connector setting */ 21 output = DAC2R(OUTPUT); 22 /* save DAC state */ 23 dac = DAC2R(TSTCTRL); 24 25 /* turn on DAC2 */ 26 DAC2W(TSTCTRL, (DAC2R(TSTCTRL) & 0xfffeffff)); 27 /* select primary head and turn off CRT (and DVI?) outputs */ 28 DAC2W(OUTPUT, (output & 0x0000feee)); 29 /* wait for signal lines to stabilize */ 30 snooze(1000); 31 /* re-enable CRT output */ 32 DAC2W(OUTPUT, (DAC2R(OUTPUT) | 0x00000001)); 33 34 /* setup RGB test signal levels to approx 30% of DAC range and enable them 35 * (NOTE: testsignal function block resides in DAC1 only (!)) */ 36 DACW(TSTDATA, ((0x2 << 30) | (0x140 << 20) | (0x140 << 10) | (0x140 << 0))); 37 /* route test signals to output 38 * (NOTE: testsignal function block resides in DAC1 only (!)) */ 39 DACW(TSTCTRL, (DACR(TSTCTRL) | 0x00001000)); 40 /* wait for signal lines to stabilize */ 41 snooze(1000); 42 43 /* do actual detection: all signals paths high == CRT connected */ 44 if (DAC2R(TSTCTRL) & 0x10000000) 45 { 46 present = true; 47 LOG(4,("DAC2: CRT detected\n")); 48 } 49 else 50 { 51 present = false; 52 LOG(4,("DAC2: no CRT detected\n")); 53 } 54 55 /* kill test signal routing 56 * (NOTE: testsignal function block resides in DAC1 only (!)) */ 57 DACW(TSTCTRL, (DACR(TSTCTRL) & 0xffffefff)); 58 59 /* restore output connector setting */ 60 DAC2W(OUTPUT, output); 61 /* restore DAC state */ 62 DAC2W(TSTCTRL, dac); 63 64 return present; 65 } 66 67 /*set the mode, brightness is a value from 0->2 (where 1 is equivalent to direct)*/ 68 status_t nv_dac2_mode(int mode,float brightness) 69 { 70 uint8 *r,*g,*b; 71 int i, ri; 72 73 /*set colour arrays to point to space reserved in shared info*/ 74 r = si->color_data; 75 g = r + 256; 76 b = g + 256; 77 78 LOG(4,("DAC2: Setting screen mode %d brightness %f\n", mode, brightness)); 79 /* init the palette for brightness specified */ 80 /* (Nvidia cards always use MSbits from screenbuffer as index for PAL) */ 81 for (i = 0; i < 256; i++) 82 { 83 ri = i * brightness; 84 if (ri > 255) ri = 255; 85 b[i] = g[i] = r[i] = ri; 86 } 87 88 if (nv_dac2_palette(r,g,b) != B_OK) return B_ERROR; 89 90 /* disable palette RAM adressing mask */ 91 NV_REG8(NV8_PAL2MASK) = 0xff; 92 LOG(2,("DAC2: PAL pixrdmsk readback $%02x\n", NV_REG8(NV8_PAL2MASK))); 93 94 return B_OK; 95 } 96 97 /*program the DAC palette using the given r,g,b values*/ 98 status_t nv_dac2_palette(uint8 r[256],uint8 g[256],uint8 b[256]) 99 { 100 int i; 101 102 LOG(4,("DAC2: setting palette\n")); 103 104 /* select first PAL adress before starting programming */ 105 NV_REG8(NV8_PAL2INDW) = 0x00; 106 107 /* loop through all 256 to program DAC */ 108 for (i = 0; i < 256; i++) 109 { 110 /* the 6 implemented bits are on b0-b5 of the bus */ 111 NV_REG8(NV8_PAL2DATA) = r[i]; 112 NV_REG8(NV8_PAL2DATA) = g[i]; 113 NV_REG8(NV8_PAL2DATA) = b[i]; 114 } 115 if (NV_REG8(NV8_PAL2INDW) != 0x00) 116 { 117 LOG(8,("DAC2: PAL write index incorrect after programming\n")); 118 return B_ERROR; 119 } 120 if (1) 121 {//reread LUT 122 uint8 R, G, B; 123 124 /* select first PAL adress to read (modulo 3 counter) */ 125 NV_REG8(NV8_PAL2INDR) = 0x00; 126 for (i = 0; i < 256; i++) 127 { 128 R = NV_REG8(NV8_PAL2DATA); 129 G = NV_REG8(NV8_PAL2DATA); 130 B = NV_REG8(NV8_PAL2DATA); 131 if ((r[i] != R) || (g[i] != G) || (b[i] != B)) 132 LOG(1,("DAC2 palette %d: w %x %x %x, r %x %x %x\n", i, r[i], g[i], b[i], R, G, B)); // apsed 133 } 134 } 135 136 return B_OK; 137 } 138 139 /*program the pixpll - frequency in kHz*/ 140 status_t nv_dac2_set_pix_pll(display_mode target) 141 { 142 uint8 m=0,n=0,p=0; 143 // uint time = 0; 144 145 float pix_setting, req_pclk; 146 status_t result; 147 148 /* fix a DVI or laptop flatpanel to 60Hz refresh! */ 149 /* Note: 150 * The pixelclock drives the flatpanel modeline, not the CRTC modeline. */ 151 if (si->ps.tmds2_active) 152 { 153 LOG(4,("DAC2: Fixing DFP refresh to 60Hz!\n")); 154 155 /* readout the panel's modeline to determine the needed pixelclock */ 156 target.timing.pixel_clock = ( 157 ((DAC2R(FP_HTOTAL) & 0x0000ffff) + 1) * 158 ((DAC2R(FP_VTOTAL) & 0x0000ffff) + 1) * 159 60) / 1000; 160 } 161 162 req_pclk = (target.timing.pixel_clock)/1000.0; 163 LOG(4,("DAC2: Setting PIX PLL for pixelclock %f\n", req_pclk)); 164 165 /* signal that we actually want to set the mode */ 166 result = nv_dac2_pix_pll_find(target,&pix_setting,&m,&n,&p, 1); 167 if (result != B_OK) 168 { 169 return result; 170 } 171 172 /*reprogram (disable,select,wait for stability,enable)*/ 173 // DXIW(PIXCLKCTRL,(DXIR(PIXCLKCTRL)&0x0F)|0x04); /*disable the PIXPLL*/ 174 // DXIW(PIXCLKCTRL,(DXIR(PIXCLKCTRL)&0x0C)|0x01); /*select the PIXPLL*/ 175 176 /* program new frequency */ 177 DAC2W(PIXPLLC, ((p << 16) | (n << 8) | m)); 178 179 /* program 2nd set N and M scalers if they exist (b31=1 enables them) */ 180 if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) 181 DAC2W(PIXPLLC2, 0x80000401); 182 183 /* Wait for the PIXPLL frequency to lock until timeout occurs */ 184 //fixme: do NV cards have a LOCK indication bit?? 185 /* while((!(DXIR(PIXPLLSTAT)&0x40)) & (time <= 2000)) 186 { 187 time++; 188 snooze(1); 189 } 190 191 if (time > 2000) 192 LOG(2,("DAC: PIX PLL frequency not locked!\n")); 193 else 194 LOG(2,("DAC: PIX PLL frequency locked\n")); 195 DXIW(PIXCLKCTRL,DXIR(PIXCLKCTRL)&0x0B); //enable the PIXPLL 196 */ 197 198 //for now: 199 /* Give the PIXPLL frequency some time to lock... */ 200 snooze(1000); 201 LOG(2,("DAC2: PIX PLL frequency should be locked now...\n")); 202 203 return B_OK; 204 } 205 206 /* find nearest valid pix pll */ 207 status_t nv_dac2_pix_pll_find 208 (display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test) 209 { 210 switch (si->ps.card_type) { 211 default: return nv10_nv20_dac2_pix_pll_find(target, calc_pclk, m_result, n_result, p_result, test); 212 } 213 return B_ERROR; 214 } 215 216 /* find nearest valid pixel PLL setting */ 217 static status_t nv10_nv20_dac2_pix_pll_find( 218 display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test) 219 { 220 int m = 0, n = 0, p = 0/*, m_max*/; 221 float error, error_best = 999999999; 222 int best[3]; 223 float f_vco, max_pclk; 224 float req_pclk = target.timing.pixel_clock/1000.0; 225 226 /* determine the max. reference-frequency postscaler setting for the 227 * current card (see G100, G200 and G400 specs). */ 228 /* switch(si->ps.card_type) 229 { 230 case G100: 231 LOG(4,("DAC: G100 restrictions apply\n")); 232 m_max = 7; 233 break; 234 case G200: 235 LOG(4,("DAC: G200 restrictions apply\n")); 236 m_max = 7; 237 break; 238 default: 239 LOG(4,("DAC: G400/G400MAX restrictions apply\n")); 240 m_max = 32; 241 break; 242 } 243 */ 244 LOG(4,("DAC2: NV10/NV20 restrictions apply\n")); 245 246 /* determine the max. pixelclock for the current videomode */ 247 switch (target.space) 248 { 249 case B_CMAP8: 250 max_pclk = si->ps.max_dac2_clock_8; 251 break; 252 case B_RGB15_LITTLE: 253 case B_RGB16_LITTLE: 254 max_pclk = si->ps.max_dac2_clock_16; 255 break; 256 case B_RGB24_LITTLE: 257 max_pclk = si->ps.max_dac2_clock_24; 258 break; 259 case B_RGB32_LITTLE: 260 max_pclk = si->ps.max_dac2_clock_32; 261 break; 262 default: 263 /* use fail-safe value */ 264 max_pclk = si->ps.max_dac2_clock_32; 265 break; 266 } 267 /* if some dualhead mode is active, an extra restriction might apply */ 268 if ((target.flags & DUALHEAD_BITS) && (target.space == B_RGB32_LITTLE)) 269 max_pclk = si->ps.max_dac2_clock_32dh; 270 271 /* Make sure the requested pixelclock is within the PLL's operational limits */ 272 /* lower limit is min_pixel_vco divided by highest postscaler-factor */ 273 if (req_pclk < (si->ps.min_video_vco / 16.0)) 274 { 275 LOG(4,("DAC2: clamping pixclock: requested %fMHz, set to %fMHz\n", 276 req_pclk, (float)(si->ps.min_video_vco / 16.0))); 277 req_pclk = (si->ps.min_video_vco / 16.0); 278 } 279 /* upper limit is given by pins in combination with current active mode */ 280 if (req_pclk > max_pclk) 281 { 282 LOG(4,("DAC2: clamping pixclock: requested %fMHz, set to %fMHz\n", 283 req_pclk, (float)max_pclk)); 284 req_pclk = max_pclk; 285 } 286 287 /* iterate through all valid PLL postscaler settings */ 288 for (p=0x01; p < 0x20; p = p<<1) 289 { 290 /* calculate the needed VCO frequency for this postscaler setting */ 291 f_vco = req_pclk * p; 292 293 /* check if this is within range of the VCO specs */ 294 if ((f_vco >= si->ps.min_video_vco) && (f_vco <= si->ps.max_video_vco)) 295 { 296 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 297 if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) f_vco /= 4; 298 299 /* iterate trough all valid reference-frequency postscaler settings */ 300 for (m = 7; m <= 14; m++) 301 { 302 /* check if phase-discriminator will be within operational limits */ 303 //fixme: PLL calcs will be resetup/splitup/updated... 304 if (si->ps.card_type == NV36) 305 { 306 if (((si->ps.f_ref / m) < 3.2) || ((si->ps.f_ref / m) > 6.4)) continue; 307 } 308 else 309 { 310 if (((si->ps.f_ref / m) < 1.0) || ((si->ps.f_ref / m) > 2.0)) continue; 311 } 312 313 /* calculate VCO postscaler setting for current setup.. */ 314 n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5); 315 /* ..and check for validity */ 316 if ((n < 1) || (n > 255)) continue; 317 318 /* find error in frequency this setting gives */ 319 if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) 320 { 321 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 322 error = fabs((req_pclk / 4) - (((si->ps.f_ref / m) * n) / p)); 323 } 324 else 325 error = fabs(req_pclk - (((si->ps.f_ref / m) * n) / p)); 326 327 /* note the setting if best yet */ 328 if (error < error_best) 329 { 330 error_best = error; 331 best[0]=m; 332 best[1]=n; 333 best[2]=p; 334 } 335 } 336 } 337 } 338 339 /* setup the scalers programming values for found optimum setting */ 340 m = best[0]; 341 n = best[1]; 342 p = best[2]; 343 344 /* log the VCO frequency found */ 345 f_vco = ((si->ps.f_ref / m) * n); 346 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 347 if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) f_vco *= 4; 348 349 LOG(2,("DAC2: pix VCO frequency found %fMhz\n", f_vco)); 350 351 /* return the results */ 352 *calc_pclk = (f_vco / p); 353 *m_result = m; 354 *n_result = n; 355 switch(p) 356 { 357 case 1: 358 p = 0x00; 359 break; 360 case 2: 361 p = 0x01; 362 break; 363 case 4: 364 p = 0x02; 365 break; 366 case 8: 367 p = 0x03; 368 break; 369 case 16: 370 p = 0x04; 371 break; 372 } 373 *p_result = p; 374 375 /* display the found pixelclock values */ 376 LOG(2,("DAC2: pix PLL check: requested %fMHz got %fMHz, mnp 0x%02x 0x%02x 0x%02x\n", 377 req_pclk, *calc_pclk, *m_result, *n_result, *p_result)); 378 379 return B_OK; 380 } 381