1 /* program the secondary DAC */ 2 /* Author: 3 Rudolf Cornelissen 12/2003-9/2004 4 */ 5 6 #define MODULE_BIT 0x00001000 7 8 #include "nv_std.h" 9 10 static status_t nv10_nv20_dac2_pix_pll_find( 11 display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test); 12 13 /* see if an analog VGA monitor is connected to connector #2 */ 14 //fixme if possible: on NV40 arch (confirmed NV43) this routine always find a monitor! 15 bool nv_dac2_crt_connected() 16 { 17 uint32 output, dac; 18 bool present; 19 20 /* NOTE: 21 * NV11 can't do this: It will report DAC1 status instead because it HAS no 22 * actual secondary DAC function. */ 23 /* (It DOES have a secondary palette RAM and pixelclock PLL though.) */ 24 25 /* save output connector setting */ 26 output = DAC2R(OUTPUT); 27 /* save DAC state */ 28 dac = DAC2R(TSTCTRL); 29 30 /* turn on DAC2 */ 31 DAC2W(TSTCTRL, (DAC2R(TSTCTRL) & 0xfffeffff)); 32 /* select primary CRTC (head) and turn off CRT (and DVI?) outputs */ 33 DAC2W(OUTPUT, (output & 0x0000feee)); 34 /* wait for signal lines to stabilize */ 35 snooze(1000); 36 /* re-enable CRT output */ 37 DAC2W(OUTPUT, (DAC2R(OUTPUT) | 0x00000001)); 38 39 /* setup RGB test signal levels to approx 30% of DAC range and enable them 40 * (NOTE: testsignal function block resides in DAC1 only (!)) */ 41 DACW(TSTDATA, ((0x2 << 30) | (0x140 << 20) | (0x140 << 10) | (0x140 << 0))); 42 /* route test signals to output 43 * (NOTE: testsignal function block resides in DAC1 only (!)) */ 44 DACW(TSTCTRL, (DACR(TSTCTRL) | 0x00001000)); 45 /* wait for signal lines to stabilize */ 46 snooze(1000); 47 48 /* do actual detection: all signals paths high == CRT connected */ 49 if (DAC2R(TSTCTRL) & 0x10000000) 50 { 51 present = true; 52 LOG(4,("DAC2: CRT detected on connector #2\n")); 53 } 54 else 55 { 56 present = false; 57 LOG(4,("DAC2: no CRT detected on connector #2\n")); 58 } 59 60 /* kill test signal routing 61 * (NOTE: testsignal function block resides in DAC1 only (!)) */ 62 DACW(TSTCTRL, (DACR(TSTCTRL) & 0xffffefff)); 63 64 /* restore output connector setting */ 65 DAC2W(OUTPUT, output); 66 /* restore DAC state */ 67 DAC2W(TSTCTRL, dac); 68 69 return present; 70 } 71 72 /*set the mode, brightness is a value from 0->2 (where 1 is equivalent to direct)*/ 73 status_t nv_dac2_mode(int mode,float brightness) 74 { 75 uint8 *r,*g,*b; 76 int i, ri; 77 78 /*set colour arrays to point to space reserved in shared info*/ 79 r = si->color_data; 80 g = r + 256; 81 b = g + 256; 82 83 LOG(4,("DAC2: Setting screen mode %d brightness %f\n", mode, brightness)); 84 /* init the palette for brightness specified */ 85 /* (Nvidia cards always use MSbits from screenbuffer as index for PAL) */ 86 for (i = 0; i < 256; i++) 87 { 88 ri = i * brightness; 89 if (ri > 255) ri = 255; 90 b[i] = g[i] = r[i] = ri; 91 } 92 93 if (nv_dac2_palette(r,g,b) != B_OK) return B_ERROR; 94 95 /* disable palette RAM adressing mask */ 96 NV_REG8(NV8_PAL2MASK) = 0xff; 97 LOG(2,("DAC2: PAL pixrdmsk readback $%02x\n", NV_REG8(NV8_PAL2MASK))); 98 99 return B_OK; 100 } 101 102 /*program the DAC palette using the given r,g,b values*/ 103 status_t nv_dac2_palette(uint8 r[256],uint8 g[256],uint8 b[256]) 104 { 105 int i; 106 107 LOG(4,("DAC2: setting palette\n")); 108 109 /* select first PAL adress before starting programming */ 110 NV_REG8(NV8_PAL2INDW) = 0x00; 111 112 /* loop through all 256 to program DAC */ 113 for (i = 0; i < 256; i++) 114 { 115 /* the 6 implemented bits are on b0-b5 of the bus */ 116 NV_REG8(NV8_PAL2DATA) = r[i]; 117 NV_REG8(NV8_PAL2DATA) = g[i]; 118 NV_REG8(NV8_PAL2DATA) = b[i]; 119 } 120 if (NV_REG8(NV8_PAL2INDW) != 0x00) 121 { 122 LOG(8,("DAC2: PAL write index incorrect after programming\n")); 123 return B_ERROR; 124 } 125 if (1) 126 {//reread LUT 127 uint8 R, G, B; 128 129 /* select first PAL adress to read (modulo 3 counter) */ 130 NV_REG8(NV8_PAL2INDR) = 0x00; 131 for (i = 0; i < 256; i++) 132 { 133 R = NV_REG8(NV8_PAL2DATA); 134 G = NV_REG8(NV8_PAL2DATA); 135 B = NV_REG8(NV8_PAL2DATA); 136 if ((r[i] != R) || (g[i] != G) || (b[i] != B)) 137 LOG(1,("DAC2 palette %d: w %x %x %x, r %x %x %x\n", i, r[i], g[i], b[i], R, G, B)); // apsed 138 } 139 } 140 141 return B_OK; 142 } 143 144 /*program the pixpll - frequency in kHz*/ 145 status_t nv_dac2_set_pix_pll(display_mode target) 146 { 147 uint8 m=0,n=0,p=0; 148 // uint time = 0; 149 150 float pix_setting, req_pclk; 151 status_t result; 152 153 /* we offer this option because some panels have very tight restrictions, 154 * and there's no overlapping settings range that makes them all work. 155 * note: 156 * this assumes the cards BIOS correctly programmed the panel (is likely) */ 157 //fixme: when VESA DDC EDID stuff is implemented, this option can be deleted... 158 if (si->ps.tmds2_active && !si->settings.pgm_panel) 159 { 160 LOG(4,("DAC2: Not programming DFP refresh (specified in nv.settings)\n")); 161 return B_OK; 162 } 163 164 /* fix a DVI or laptop flatpanel to 60Hz refresh! */ 165 /* Note: 166 * The pixelclock drives the flatpanel modeline, not the CRTC modeline. */ 167 if (si->ps.tmds2_active) 168 { 169 LOG(4,("DAC2: Fixing DFP refresh to 60Hz!\n")); 170 171 /* use the panel's modeline to determine the needed pixelclock */ 172 target.timing.pixel_clock = si->ps.p2_timing.pixel_clock; 173 } 174 175 req_pclk = (target.timing.pixel_clock)/1000.0; 176 LOG(4,("DAC2: Setting PIX PLL for pixelclock %f\n", req_pclk)); 177 178 /* signal that we actually want to set the mode */ 179 result = nv_dac2_pix_pll_find(target,&pix_setting,&m,&n,&p, 1); 180 if (result != B_OK) 181 { 182 return result; 183 } 184 185 /*reprogram (disable,select,wait for stability,enable)*/ 186 // DXIW(PIXCLKCTRL,(DXIR(PIXCLKCTRL)&0x0F)|0x04); /*disable the PIXPLL*/ 187 // DXIW(PIXCLKCTRL,(DXIR(PIXCLKCTRL)&0x0C)|0x01); /*select the PIXPLL*/ 188 189 /* program new frequency */ 190 DAC2W(PIXPLLC, ((p << 16) | (n << 8) | m)); 191 192 /* program 2nd set N and M scalers if they exist (b31=1 enables them) */ 193 if (si->ps.ext_pll) DAC2W(PIXPLLC2, 0x80000401); 194 195 /* Wait for the PIXPLL frequency to lock until timeout occurs */ 196 //fixme: do NV cards have a LOCK indication bit?? 197 /* while((!(DXIR(PIXPLLSTAT)&0x40)) & (time <= 2000)) 198 { 199 time++; 200 snooze(1); 201 } 202 203 if (time > 2000) 204 LOG(2,("DAC: PIX PLL frequency not locked!\n")); 205 else 206 LOG(2,("DAC: PIX PLL frequency locked\n")); 207 DXIW(PIXCLKCTRL,DXIR(PIXCLKCTRL)&0x0B); //enable the PIXPLL 208 */ 209 210 //for now: 211 /* Give the PIXPLL frequency some time to lock... */ 212 snooze(1000); 213 LOG(2,("DAC2: PIX PLL frequency should be locked now...\n")); 214 215 return B_OK; 216 } 217 218 /* find nearest valid pix pll */ 219 status_t nv_dac2_pix_pll_find 220 (display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test) 221 { 222 switch (si->ps.card_type) { 223 default: return nv10_nv20_dac2_pix_pll_find(target, calc_pclk, m_result, n_result, p_result, test); 224 } 225 return B_ERROR; 226 } 227 228 /* find nearest valid pixel PLL setting */ 229 static status_t nv10_nv20_dac2_pix_pll_find( 230 display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test) 231 { 232 int m = 0, n = 0, p = 0/*, m_max*/; 233 float error, error_best = 999999999; 234 int best[3]; 235 float f_vco, max_pclk; 236 float req_pclk = target.timing.pixel_clock/1000.0; 237 238 /* determine the max. reference-frequency postscaler setting for the 239 * current card (see G100, G200 and G400 specs). */ 240 /* switch(si->ps.card_type) 241 { 242 case G100: 243 LOG(4,("DAC: G100 restrictions apply\n")); 244 m_max = 7; 245 break; 246 case G200: 247 LOG(4,("DAC: G200 restrictions apply\n")); 248 m_max = 7; 249 break; 250 default: 251 LOG(4,("DAC: G400/G400MAX restrictions apply\n")); 252 m_max = 32; 253 break; 254 } 255 */ 256 LOG(4,("DAC2: NV10/NV20 restrictions apply\n")); 257 258 /* determine the max. pixelclock for the current videomode */ 259 switch (target.space) 260 { 261 case B_CMAP8: 262 max_pclk = si->ps.max_dac2_clock_8; 263 break; 264 case B_RGB15_LITTLE: 265 case B_RGB16_LITTLE: 266 max_pclk = si->ps.max_dac2_clock_16; 267 break; 268 case B_RGB24_LITTLE: 269 max_pclk = si->ps.max_dac2_clock_24; 270 break; 271 case B_RGB32_LITTLE: 272 max_pclk = si->ps.max_dac2_clock_32; 273 break; 274 default: 275 /* use fail-safe value */ 276 max_pclk = si->ps.max_dac2_clock_32; 277 break; 278 } 279 /* if some dualhead mode is active, an extra restriction might apply */ 280 if ((target.flags & DUALHEAD_BITS) && (target.space == B_RGB32_LITTLE)) 281 max_pclk = si->ps.max_dac2_clock_32dh; 282 283 /* Make sure the requested pixelclock is within the PLL's operational limits */ 284 /* lower limit is min_pixel_vco divided by highest postscaler-factor */ 285 if (req_pclk < (si->ps.min_video_vco / 16.0)) 286 { 287 LOG(4,("DAC2: clamping pixclock: requested %fMHz, set to %fMHz\n", 288 req_pclk, (float)(si->ps.min_video_vco / 16.0))); 289 req_pclk = (si->ps.min_video_vco / 16.0); 290 } 291 /* upper limit is given by pins in combination with current active mode */ 292 if (req_pclk > max_pclk) 293 { 294 LOG(4,("DAC2: clamping pixclock: requested %fMHz, set to %fMHz\n", 295 req_pclk, (float)max_pclk)); 296 req_pclk = max_pclk; 297 } 298 299 /* iterate through all valid PLL postscaler settings */ 300 for (p=0x01; p < 0x20; p = p<<1) 301 { 302 /* calculate the needed VCO frequency for this postscaler setting */ 303 f_vco = req_pclk * p; 304 305 /* check if this is within range of the VCO specs */ 306 if ((f_vco >= si->ps.min_video_vco) && (f_vco <= si->ps.max_video_vco)) 307 { 308 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 309 if (si->ps.ext_pll) f_vco /= 4; 310 311 /* iterate trough all valid reference-frequency postscaler settings */ 312 for (m = 7; m <= 14; m++) 313 { 314 /* check if phase-discriminator will be within operational limits */ 315 //fixme: PLL calcs will be resetup/splitup/updated... 316 if (si->ps.card_type == NV36) 317 { 318 if (((si->ps.f_ref / m) < 3.2) || ((si->ps.f_ref / m) > 6.4)) continue; 319 } 320 else 321 { 322 if (((si->ps.f_ref / m) < 1.0) || ((si->ps.f_ref / m) > 2.0)) continue; 323 } 324 325 /* calculate VCO postscaler setting for current setup.. */ 326 n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5); 327 /* ..and check for validity */ 328 if ((n < 1) || (n > 255)) continue; 329 330 /* find error in frequency this setting gives */ 331 if (si->ps.ext_pll) 332 { 333 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 334 error = fabs((req_pclk / 4) - (((si->ps.f_ref / m) * n) / p)); 335 } 336 else 337 error = fabs(req_pclk - (((si->ps.f_ref / m) * n) / p)); 338 339 /* note the setting if best yet */ 340 if (error < error_best) 341 { 342 error_best = error; 343 best[0]=m; 344 best[1]=n; 345 best[2]=p; 346 } 347 } 348 } 349 } 350 351 /* setup the scalers programming values for found optimum setting */ 352 m = best[0]; 353 n = best[1]; 354 p = best[2]; 355 356 /* log the VCO frequency found */ 357 f_vco = ((si->ps.f_ref / m) * n); 358 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 359 if (si->ps.ext_pll) f_vco *= 4; 360 361 LOG(2,("DAC2: pix VCO frequency found %fMhz\n", f_vco)); 362 363 /* return the results */ 364 *calc_pclk = (f_vco / p); 365 *m_result = m; 366 *n_result = n; 367 switch(p) 368 { 369 case 1: 370 p = 0x00; 371 break; 372 case 2: 373 p = 0x01; 374 break; 375 case 4: 376 p = 0x02; 377 break; 378 case 8: 379 p = 0x03; 380 break; 381 case 16: 382 p = 0x04; 383 break; 384 } 385 *p_result = p; 386 387 /* display the found pixelclock values */ 388 LOG(2,("DAC2: pix PLL check: requested %fMHz got %fMHz, mnp 0x%02x 0x%02x 0x%02x\n", 389 req_pclk, *calc_pclk, *m_result, *n_result, *p_result)); 390 391 return B_OK; 392 } 393