1 /* program the secondary DAC */ 2 /* Author: 3 Rudolf Cornelissen 12/2003-9/2009 4 */ 5 6 #define MODULE_BIT 0x00001000 7 8 #include "nv_std.h" 9 10 static void nv_dac2_dump_pix_pll(void); 11 static status_t nv10_nv20_dac2_pix_pll_find( 12 display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test); 13 14 /* see if an analog VGA monitor is connected to connector #2 */ 15 bool nv_dac2_crt_connected() 16 { 17 uint32 output, dac; 18 bool present; 19 20 switch(si->ps.card_type) { 21 /* NOTE: 22 * NV11 can't do this: It will report DAC1 status instead because it HAS no 23 * actual secondary DAC function. */ 24 /* (It DOES have a secondary palette RAM and pixelclock PLL though.) */ 25 case NV11: 26 /* on NV40 arch (confirmed NV43, G71, G73) this routine doesn't work. */ 27 /* (on NV44 (confirmed Geforce 6200LE) this routine *does* work.) */ 28 case NV43: 29 case G71: 30 case G73: 31 LOG(4,("DAC2: no load detection available. reporting no CRT detected on connector #2\n")); 32 return false; 33 } 34 35 /* save output connector setting */ 36 output = DAC2R(OUTPUT); 37 /* save DAC state */ 38 dac = DAC2R(TSTCTRL); 39 40 /* turn on DAC2 */ 41 DAC2W(TSTCTRL, (DAC2R(TSTCTRL) & 0xfffeffff)); 42 /* select primary CRTC (head) and turn off CRT (and DVI?) outputs */ 43 DAC2W(OUTPUT, (output & 0x0000feee)); 44 /* wait for signal lines to stabilize */ 45 snooze(1000); 46 /* re-enable CRT output */ 47 DAC2W(OUTPUT, (DAC2R(OUTPUT) | 0x00000001)); 48 49 /* setup RGB test signal levels to approx 30% of DAC range and enable them 50 * (NOTE: testsignal function block resides in DAC1 only (!)) */ 51 DACW(TSTDATA, ((0x2 << 30) | (0x140 << 20) | (0x140 << 10) | (0x140 << 0))); 52 /* route test signals to output 53 * (NOTE: testsignal function block resides in DAC1 only (!)) */ 54 DACW(TSTCTRL, (DACR(TSTCTRL) | 0x00001000)); 55 /* wait for signal lines to stabilize */ 56 snooze(1000); 57 58 /* do actual detection: all signals paths high == CRT connected */ 59 if (DAC2R(TSTCTRL) & 0x10000000) 60 { 61 present = true; 62 LOG(4,("DAC2: CRT detected on connector #2\n")); 63 } 64 else 65 { 66 present = false; 67 LOG(4,("DAC2: no CRT detected on connector #2\n")); 68 } 69 70 /* kill test signal routing 71 * (NOTE: testsignal function block resides in DAC1 only (!)) */ 72 DACW(TSTCTRL, (DACR(TSTCTRL) & 0xffffefff)); 73 74 /* restore output connector setting */ 75 DAC2W(OUTPUT, output); 76 /* restore DAC state */ 77 DAC2W(TSTCTRL, dac); 78 79 return present; 80 } 81 82 /*set the mode, brightness is a value from 0->2 (where 1 is equivalent to direct)*/ 83 status_t nv_dac2_mode(int mode,float brightness) 84 { 85 uint8 *r,*g,*b; 86 int i, ri; 87 88 /*set colour arrays to point to space reserved in shared info*/ 89 r = si->color_data; 90 g = r + 256; 91 b = g + 256; 92 93 LOG(4,("DAC2: Setting screen mode %d brightness %f\n", mode, brightness)); 94 /* init the palette for brightness specified */ 95 /* (Nvidia cards always use MSbits from screenbuffer as index for PAL) */ 96 for (i = 0; i < 256; i++) 97 { 98 ri = i * brightness; 99 if (ri > 255) ri = 255; 100 b[i] = g[i] = r[i] = ri; 101 } 102 103 if (nv_dac2_palette(r,g,b) != B_OK) return B_ERROR; 104 105 /* disable palette RAM adressing mask */ 106 NV_REG8(NV8_PAL2MASK) = 0xff; 107 LOG(2,("DAC2: PAL pixrdmsk readback $%02x\n", NV_REG8(NV8_PAL2MASK))); 108 109 return B_OK; 110 } 111 112 /*program the DAC palette using the given r,g,b values*/ 113 status_t nv_dac2_palette(uint8 r[256],uint8 g[256],uint8 b[256]) 114 { 115 int i; 116 117 LOG(4,("DAC2: setting palette\n")); 118 119 /* select first PAL adress before starting programming */ 120 NV_REG8(NV8_PAL2INDW) = 0x00; 121 122 /* loop through all 256 to program DAC */ 123 for (i = 0; i < 256; i++) 124 { 125 /* the 6 implemented bits are on b0-b5 of the bus */ 126 NV_REG8(NV8_PAL2DATA) = r[i]; 127 NV_REG8(NV8_PAL2DATA) = g[i]; 128 NV_REG8(NV8_PAL2DATA) = b[i]; 129 } 130 if (NV_REG8(NV8_PAL2INDW) != 0x00) 131 { 132 LOG(8,("DAC2: PAL write index incorrect after programming\n")); 133 return B_ERROR; 134 } 135 if (1) 136 {//reread LUT 137 uint8 R, G, B; 138 139 /* select first PAL adress to read (modulo 3 counter) */ 140 NV_REG8(NV8_PAL2INDR) = 0x00; 141 for (i = 0; i < 256; i++) 142 { 143 R = NV_REG8(NV8_PAL2DATA); 144 G = NV_REG8(NV8_PAL2DATA); 145 B = NV_REG8(NV8_PAL2DATA); 146 if ((r[i] != R) || (g[i] != G) || (b[i] != B)) 147 LOG(1,("DAC2 palette %d: w %x %x %x, r %x %x %x\n", i, r[i], g[i], b[i], R, G, B)); // apsed 148 } 149 } 150 151 return B_OK; 152 } 153 154 /*program the pixpll - frequency in kHz*/ 155 status_t nv_dac2_set_pix_pll(display_mode target) 156 { 157 uint8 m=0,n=0,p=0; 158 159 float pix_setting, req_pclk; 160 status_t result; 161 162 /* fix a DVI or laptop flatpanel to 60Hz refresh! */ 163 /* Note: 164 * The pixelclock drives the flatpanel modeline, not the CRTC modeline. */ 165 if (si->ps.monitors & CRTC2_TMDS) 166 { 167 LOG(4,("DAC2: Fixing DFP refresh to 60Hz!\n")); 168 169 /* use the panel's modeline to determine the needed pixelclock */ 170 target.timing.pixel_clock = si->ps.p2_timing.pixel_clock; 171 } 172 173 req_pclk = (target.timing.pixel_clock)/1000.0; 174 175 /* signal that we actually want to set the mode */ 176 result = nv_dac2_pix_pll_find(target,&pix_setting,&m,&n,&p, 1); 177 if (result != B_OK) return result; 178 179 /* dump old setup for learning purposes */ 180 nv_dac2_dump_pix_pll(); 181 182 /* some logging for learning purposes */ 183 LOG(4,("DAC2: current NV30_PLLSETUP settings: $%08x\n", DACR(NV30_PLLSETUP))); 184 /* this register seems to (dis)connect functions blocks and PLLs: 185 * there seem to be two PLL types per function block (on some cards), 186 * b16-17 DAC1clk, b18-19 DAC2clk, b20-21 GPUclk, b22-23 MEMclk. */ 187 LOG(4,("DAC2: current (0x0000c040) settings: $%08x\n", NV_REG32(0x0000c040))); 188 189 /* disable spread spectrum modes for the pixelPLLs _first_ */ 190 /* spread spectrum: b0,1 = GPUclk, b2,3 = MEMclk, b4,5 = DAC1clk, b6,7 = DAC2clk; 191 * b16-19 influence clock routing to digital outputs (internal/external LVDS transmitters?) */ 192 if (si->ps.card_arch >= NV30A) 193 DACW(NV30_PLLSETUP, (DACR(NV30_PLLSETUP) & ~0x000000f0)); 194 195 /* we offer this option because some panels have very tight restrictions, 196 * and there's no overlapping settings range that makes them all work. 197 * note: 198 * this assumes the cards BIOS correctly programmed the panel (is likely) */ 199 //fixme: when VESA DDC EDID stuff is implemented, this option can be deleted... 200 if ((si->ps.monitors & CRTC2_TMDS) && !si->settings.pgm_panel) { 201 LOG(4,("DAC2: Not programming DFP refresh (specified in nvidia.settings)\n")); 202 } else { 203 LOG(4,("DAC2: Setting PIX PLL for pixelclock %f\n", req_pclk)); 204 205 /* program new frequency */ 206 DAC2W(PIXPLLC, ((p << 16) | (n << 8) | m)); 207 208 /* program 2nd set N and M scalers if they exist (b31=1 enables them) */ 209 if (si->ps.ext_pll) DAC2W(PIXPLLC2, 0x80000401); 210 211 /* Give the PIXPLL frequency some time to lock... (there's no indication bit available) */ 212 snooze(1000); 213 214 LOG(2,("DAC2: PIX PLL frequency should be locked now...\n")); 215 } 216 217 /* enable programmable PLLs */ 218 /* (confirmed PLLSEL to be a write-only register on NV04 and NV11!) */ 219 /* note: 220 * setup PLL assignment _after_ programming PLL */ 221 if (si->ps.card_arch < NV40A) { 222 DACW(PLLSEL, 0x30000f00); 223 } else { 224 DACW(NV40_PLLSEL2, (DACR(NV40_PLLSEL2) & ~0x10000100)); 225 DACW(PLLSEL, 0x30000f04); 226 } 227 228 return B_OK; 229 } 230 231 static void nv_dac2_dump_pix_pll(void) 232 { 233 uint32 dividers1, dividers2; 234 uint8 m1, n1, p1; 235 uint8 m2 = 1, n2 = 1; 236 float f_vco, f_phase, f_pixel; 237 238 LOG(2,("DAC2: dumping current pixelPLL settings:\n")); 239 240 dividers1 = DAC2R(PIXPLLC); 241 m1 = (dividers1 & 0x000000ff); 242 n1 = (dividers1 & 0x0000ff00) >> 8; 243 p1 = 0x01 << ((dividers1 & 0x00070000) >> 16); 244 LOG(2,("DAC2: divider1 settings ($%08x): M1=%d, N1=%d, P1=%d\n", dividers1, m1, n1, p1)); 245 246 if (si->ps.ext_pll) { 247 dividers2 = DAC2R(PIXPLLC2); 248 if (dividers2 & 0x80000000) { 249 /* the extended PLL part is enabled */ 250 m2 = (dividers2 & 0x000000ff); 251 n2 = (dividers2 & 0x0000ff00) >> 8; 252 LOG(2,("DAC2: divider2 is enabled, settings ($%08x): M2=%d, N2=%d\n", dividers2, m2, n2)); 253 } else { 254 LOG(2,("DAC2: divider2 is disabled ($%08x)\n", dividers2)); 255 } 256 } 257 258 /* log the frequencies found */ 259 f_phase = si->ps.f_ref / (m1 * m2); 260 f_vco = (f_phase * n1 * n2); 261 f_pixel = f_vco / p1; 262 263 LOG(2,("DAC2: phase discriminator frequency is %fMhz\n", f_phase)); 264 LOG(2,("DAC2: VCO frequency is %fMhz\n", f_vco)); 265 LOG(2,("DAC2: pixelclock is %fMhz\n", f_pixel)); 266 LOG(2,("DAC2: end of dump.\n")); 267 268 /* apparantly if a VESA modecall during boot fails we need to explicitly select the PLL's 269 * again (was already done during driver init) if we readout the current PLL setting.. */ 270 DACW(PLLSEL, 0x30000f00); 271 } 272 273 /* find nearest valid pix pll */ 274 status_t nv_dac2_pix_pll_find 275 (display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test) 276 { 277 switch (si->ps.card_type) { 278 default: return nv10_nv20_dac2_pix_pll_find(target, calc_pclk, m_result, n_result, p_result, test); 279 } 280 return B_ERROR; 281 } 282 283 /* find nearest valid pixel PLL setting */ 284 static status_t nv10_nv20_dac2_pix_pll_find( 285 display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test) 286 { 287 int m = 0, n = 0, p = 0/*, m_max*/; 288 float error, error_best = 999999999; 289 int best[3]; 290 float f_vco, max_pclk; 291 float req_pclk = target.timing.pixel_clock/1000.0; 292 293 LOG(4,("DAC2: NV10/NV20 restrictions apply\n")); 294 295 /* determine the max. pixelclock for the current videomode */ 296 switch (target.space) 297 { 298 case B_CMAP8: 299 max_pclk = si->ps.max_dac2_clock_8; 300 break; 301 case B_RGB15_LITTLE: 302 case B_RGB16_LITTLE: 303 max_pclk = si->ps.max_dac2_clock_16; 304 break; 305 case B_RGB24_LITTLE: 306 max_pclk = si->ps.max_dac2_clock_24; 307 break; 308 case B_RGB32_LITTLE: 309 max_pclk = si->ps.max_dac2_clock_32; 310 break; 311 default: 312 /* use fail-safe value */ 313 max_pclk = si->ps.max_dac2_clock_32; 314 break; 315 } 316 /* if some dualhead mode is active, an extra restriction might apply */ 317 if ((target.flags & DUALHEAD_BITS) && (target.space == B_RGB32_LITTLE)) 318 max_pclk = si->ps.max_dac2_clock_32dh; 319 320 /* Make sure the requested pixelclock is within the PLL's operational limits */ 321 /* lower limit is min_pixel_vco divided by highest postscaler-factor */ 322 if (req_pclk < (si->ps.min_video_vco / 16.0)) 323 { 324 LOG(4,("DAC2: clamping pixclock: requested %fMHz, set to %fMHz\n", 325 req_pclk, (float)(si->ps.min_video_vco / 16.0))); 326 req_pclk = (si->ps.min_video_vco / 16.0); 327 } 328 /* upper limit is given by pins in combination with current active mode */ 329 if (req_pclk > max_pclk) 330 { 331 LOG(4,("DAC2: clamping pixclock: requested %fMHz, set to %fMHz\n", 332 req_pclk, (float)max_pclk)); 333 req_pclk = max_pclk; 334 } 335 336 /* iterate through all valid PLL postscaler settings */ 337 for (p=0x01; p < 0x20; p = p<<1) 338 { 339 /* calculate the needed VCO frequency for this postscaler setting */ 340 f_vco = req_pclk * p; 341 342 /* check if this is within range of the VCO specs */ 343 if ((f_vco >= si->ps.min_video_vco) && (f_vco <= si->ps.max_video_vco)) 344 { 345 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 346 if (si->ps.ext_pll) f_vco /= 4; 347 348 /* iterate trough all valid reference-frequency postscaler settings */ 349 for (m = 7; m <= 14; m++) 350 { 351 /* check if phase-discriminator will be within operational limits */ 352 //fixme: PLL calcs will be resetup/splitup/updated... 353 if (si->ps.card_type == NV36) 354 { 355 if (((si->ps.f_ref / m) < 3.2) || ((si->ps.f_ref / m) > 6.4)) continue; 356 } 357 else 358 { 359 if (((si->ps.f_ref / m) < 1.0) || ((si->ps.f_ref / m) > 2.0)) continue; 360 } 361 362 /* calculate VCO postscaler setting for current setup.. */ 363 n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5); 364 /* ..and check for validity */ 365 if ((n < 1) || (n > 255)) continue; 366 367 /* find error in frequency this setting gives */ 368 if (si->ps.ext_pll) 369 { 370 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 371 error = fabs((req_pclk / 4) - (((si->ps.f_ref / m) * n) / p)); 372 } 373 else 374 error = fabs(req_pclk - (((si->ps.f_ref / m) * n) / p)); 375 376 /* note the setting if best yet */ 377 if (error < error_best) 378 { 379 error_best = error; 380 best[0]=m; 381 best[1]=n; 382 best[2]=p; 383 } 384 } 385 } 386 } 387 388 /* setup the scalers programming values for found optimum setting */ 389 m = best[0]; 390 n = best[1]; 391 p = best[2]; 392 393 /* log the VCO frequency found */ 394 f_vco = ((si->ps.f_ref / m) * n); 395 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 396 if (si->ps.ext_pll) f_vco *= 4; 397 398 LOG(2,("DAC2: pix VCO frequency found %fMhz\n", f_vco)); 399 400 /* return the results */ 401 *calc_pclk = (f_vco / p); 402 *m_result = m; 403 *n_result = n; 404 switch(p) 405 { 406 case 1: 407 p = 0x00; 408 break; 409 case 2: 410 p = 0x01; 411 break; 412 case 4: 413 p = 0x02; 414 break; 415 case 8: 416 p = 0x03; 417 break; 418 case 16: 419 p = 0x04; 420 break; 421 } 422 *p_result = p; 423 424 /* display the found pixelclock values */ 425 LOG(2,("DAC2: pix PLL check: requested %fMHz got %fMHz, mnp 0x%02x 0x%02x 0x%02x\n", 426 req_pclk, *calc_pclk, *m_result, *n_result, *p_result)); 427 428 return B_OK; 429 } 430