1 /* program the DAC */ 2 /* Author: 3 Rudolf Cornelissen 12/2003-5/2021 4 */ 5 6 #define MODULE_BIT 0x00010000 7 8 #include "nv_std.h" 9 10 static void nv_dac_dump_pix_pll(void); 11 static status_t nv4_nv10_nv20_dac_pix_pll_find( 12 display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test); 13 14 /* see if an analog VGA monitor is connected to connector #1 */ 15 bool nv_dac_crt_connected(void) 16 { 17 uint32 output, dac; 18 bool present; 19 20 /* save output connector setting */ 21 output = DACR(OUTPUT); 22 /* save DAC state */ 23 dac = DACR(TSTCTRL); 24 25 /* turn on DAC */ 26 DACW(TSTCTRL, (DACR(TSTCTRL) & 0xfffeffff)); 27 if (si->ps.secondary_head) 28 { 29 /* select primary CRTC (head) and turn off CRT (and DVI?) outputs */ 30 DACW(OUTPUT, (output & 0x0000feee)); 31 } 32 else 33 { 34 /* turn off CRT (and DVI?) outputs */ 35 /* note: 36 * Don't touch the CRTC (head) assignment bit, as that would have undefined 37 * results. Confirmed NV15 cards getting into lasting RAM access trouble 38 * otherwise!! (goes for both system gfx RAM access and CRTC/DAC RAM access.) */ 39 DACW(OUTPUT, (output & 0x0000ffee)); 40 } 41 /* wait for signal lines to stabilize */ 42 snooze(1000); 43 /* re-enable CRT output */ 44 DACW(OUTPUT, (DACR(OUTPUT) | 0x00000001)); 45 46 /* setup RGB test signal levels to approx 30% of DAC range and enable them */ 47 DACW(TSTDATA, ((0x2 << 30) | (0x140 << 20) | (0x140 << 10) | (0x140 << 0))); 48 /* route test signals to output */ 49 DACW(TSTCTRL, (DACR(TSTCTRL) | 0x00001000)); 50 /* wait for signal lines to stabilize */ 51 snooze(1000); 52 53 /* do actual detection: all signals paths high == CRT connected */ 54 if (DACR(TSTCTRL) & 0x10000000) 55 { 56 present = true; 57 LOG(4,("DAC: CRT detected on connector #1\n")); 58 } 59 else 60 { 61 present = false; 62 LOG(4,("DAC: no CRT detected on connector #1\n")); 63 } 64 65 /* kill test signal routing */ 66 DACW(TSTCTRL, (DACR(TSTCTRL) & 0xffffefff)); 67 68 /* restore output connector setting */ 69 DACW(OUTPUT, output); 70 /* restore DAC state */ 71 DACW(TSTCTRL, dac); 72 73 return present; 74 } 75 76 /*set the mode, brightness is a value from 0->2 (where 1 is equivalent to direct)*/ 77 status_t nv_dac_mode(int mode,float brightness) 78 { 79 uint8 *r,*g,*b; 80 int i, ri; 81 82 /*set colour arrays to point to space reserved in shared info*/ 83 r = si->color_data; 84 g = r + 256; 85 b = g + 256; 86 87 LOG(4,("DAC: Setting screen mode %d brightness %f\n", mode, brightness)); 88 /* init the palette for brightness specified */ 89 /* (Nvidia cards always use MSbits from screenbuffer as index for PAL) */ 90 for (i = 0; i < 256; i++) 91 { 92 ri = i * brightness; 93 if (ri > 255) ri = 255; 94 b[i] = g[i] = r[i] = ri; 95 } 96 97 if (nv_dac_palette(r,g,b) != B_OK) return B_ERROR; 98 99 /* disable palette RAM adressing mask */ 100 NV_REG8(NV8_PALMASK) = 0xff; 101 LOG(2,("DAC: PAL pixrdmsk readback $%02x\n", NV_REG8(NV8_PALMASK))); 102 103 return B_OK; 104 } 105 106 /* enable/disable dithering */ 107 status_t nv_dac_dither(bool dither) 108 { 109 /* older cards can't do dithering */ 110 if ((si->ps.card_type != NV11) && !si->ps.secondary_head) return B_ERROR; 111 112 if (dither) { 113 LOG(4,("DAC: enabling dithering\n")); 114 115 if (si->ps.card_type == NV11) { 116 /* NV11 apparantly has a fixed dithering pattern */ 117 118 /* enable dithering */ 119 DACW(NV11_DITHER, (DACR(NV11_DITHER) | 0x00010000)); 120 } else { 121 /* setup dithering pattern */ 122 DACW(FP_DITH_PATT1, 0xe4e4e4e4); 123 DACW(FP_DITH_PATT2, 0xe4e4e4e4); 124 DACW(FP_DITH_PATT3, 0xe4e4e4e4); 125 DACW(FP_DITH_PATT4, 0x44444444); 126 DACW(FP_DITH_PATT5, 0x44444444); 127 DACW(FP_DITH_PATT6, 0x44444444); 128 129 /* enable dithering */ 130 DACW(FP_DITHER, (DACR(FP_DITHER) | 0x00000001)); 131 } 132 } else { 133 LOG(4,("DAC: disabling dithering\n")); 134 135 if (si->ps.card_type == NV11) { 136 /* disable dithering */ 137 DACW(NV11_DITHER, (DACR(NV11_DITHER) & ~0x00010000)); 138 } else { 139 /* disable dithering */ 140 DACW(FP_DITHER, (DACR(FP_DITHER) & ~0x00000001)); 141 } 142 } 143 144 return B_OK; 145 } 146 147 /*program the DAC palette using the given r,g,b values*/ 148 status_t nv_dac_palette(uint8 r[256],uint8 g[256],uint8 b[256]) 149 { 150 int i; 151 152 LOG(4,("DAC: setting palette\n")); 153 154 /* select first PAL adress before starting programming */ 155 NV_REG8(NV8_PALINDW) = 0x00; 156 157 /* loop through all 256 to program DAC */ 158 for (i = 0; i < 256; i++) 159 { 160 /* the 6 implemented bits are on b0-b5 of the bus */ 161 NV_REG8(NV8_PALDATA) = r[i]; 162 NV_REG8(NV8_PALDATA) = g[i]; 163 NV_REG8(NV8_PALDATA) = b[i]; 164 } 165 if (NV_REG8(NV8_PALINDW) != 0x00) 166 { 167 LOG(8,("DAC: PAL write index incorrect after programming\n")); 168 return B_ERROR; 169 } 170 if (1) 171 {//reread LUT 172 uint8 R, G, B; 173 174 /* select first PAL adress to read (modulo 3 counter) */ 175 NV_REG8(NV8_PALINDR) = 0x00; 176 for (i = 0; i < 256; i++) 177 { 178 R = NV_REG8(NV8_PALDATA); 179 G = NV_REG8(NV8_PALDATA); 180 B = NV_REG8(NV8_PALDATA); 181 if ((r[i] != R) || (g[i] != G) || (b[i] != B)) 182 LOG(1,("DAC palette %d: w %x %x %x, r %x %x %x\n", i, r[i], g[i], b[i], R, G, B)); // apsed 183 } 184 } 185 186 return B_OK; 187 } 188 189 /*program the pixpll - frequency in kHz*/ 190 status_t nv_dac_set_pix_pll(display_mode target) 191 { 192 uint8 m=0,n=0,p=0; 193 194 float pix_setting, req_pclk; 195 status_t result; 196 197 /* fix a DVI or laptop flatpanel to 60Hz refresh! */ 198 /* Note: 199 * The pixelclock drives the flatpanel modeline, not the CRTC modeline. */ 200 if (si->ps.monitors & CRTC1_TMDS) 201 { 202 LOG(4,("DAC: Fixing DFP refresh to 60Hz!\n")); 203 204 /* use the panel's modeline to determine the needed pixelclock */ 205 target.timing.pixel_clock = si->ps.p1_timing.pixel_clock; 206 } 207 208 req_pclk = (target.timing.pixel_clock)/1000.0; 209 210 /* signal that we actually want to set the mode */ 211 result = nv_dac_pix_pll_find(target,&pix_setting,&m,&n,&p, 1); 212 if (result != B_OK) return result; 213 214 /* dump old setup for learning purposes */ 215 nv_dac_dump_pix_pll(); 216 217 /* some logging for learning purposes */ 218 LOG(4,("DAC: current NV30_PLLSETUP settings: $%08x\n", DACR(NV30_PLLSETUP))); 219 /* this register seems to (dis)connect functions blocks and PLLs: 220 * there seem to be two PLL types per function block (on some cards), 221 * b16-17 DAC1clk, b18-19 DAC2clk, b20-21 GPUclk, b22-23 MEMclk. */ 222 LOG(4,("DAC: current (0x0000c040) settings: $%08x\n", NV_REG32(0x0000c040))); 223 224 /* disable spread spectrum modes for the pixelPLLs _first_ */ 225 /* spread spectrum: b0,1 = GPUclk, b2,3 = MEMclk, b4,5 = DAC1clk, b6,7 = DAC2clk; 226 * b16-19 influence clock routing to digital outputs (internal/external LVDS transmitters?) */ 227 if (si->ps.card_arch >= NV30A) 228 DACW(NV30_PLLSETUP, (DACR(NV30_PLLSETUP) & ~0x000000f0)); 229 230 /* we offer this option because some panels have very tight restrictions, 231 * and there's no overlapping settings range that makes them all work. 232 * note: 233 * this assumes the cards BIOS correctly programmed the panel (is likely) */ 234 //fixme: when VESA DDC EDID stuff is implemented, this option can be deleted... 235 if ((si->ps.monitors & CRTC1_TMDS) && !si->settings.pgm_panel) { 236 LOG(4,("DAC: Not programming DFP refresh (specified in nvidia.settings)\n")); 237 } else { 238 LOG(4,("DAC: Setting PIX PLL for pixelclock %f\n", req_pclk)); 239 240 /* program new frequency */ 241 DACW(PIXPLLC, ((p << 16) | (n << 8) | m)); 242 243 /* program 2nd set N and M scalers if they exist (b31=1 enables them) */ 244 if (si->ps.ext_pll) DACW(PIXPLLC2, 0x80000401); 245 246 /* Give the PIXPLL frequency some time to lock... (there's no indication bit available) */ 247 snooze(1000); 248 249 LOG(2,("DAC: PIX PLL frequency should be locked now...\n")); 250 } 251 252 /* enable programmable PLLs */ 253 /* (confirmed PLLSEL to be a write-only register on NV04 and NV11!) */ 254 /* note: 255 * setup PLL assignment _after_ programming PLL */ 256 if (si->ps.secondary_head) { 257 if (si->ps.card_arch < NV40A) { 258 DACW(PLLSEL, 0x30000f00); 259 } else { 260 DACW(NV40_PLLSEL2, (DACR(NV40_PLLSEL2) & ~0x10000100)); 261 DACW(PLLSEL, 0x30000f04); 262 } 263 } else { 264 DACW(PLLSEL, 0x10000700); 265 } 266 267 return B_OK; 268 } 269 270 static void nv_dac_dump_pix_pll(void) 271 { 272 uint32 dividers1, dividers2; 273 uint8 m1, n1, p1; 274 uint8 m2 = 1, n2 = 1; 275 float f_vco, f_phase, f_pixel; 276 277 LOG(2,("DAC: dumping current pixelPLL settings:\n")); 278 279 dividers1 = DACR(PIXPLLC); 280 m1 = (dividers1 & 0x000000ff); 281 n1 = (dividers1 & 0x0000ff00) >> 8; 282 p1 = 0x01 << ((dividers1 & 0x00070000) >> 16); 283 LOG(2,("DAC: divider1 settings ($%08x): M1=%d, N1=%d, P1=%d\n", dividers1, m1, n1, p1)); 284 285 if (si->ps.ext_pll) { 286 dividers2 = DACR(PIXPLLC2); 287 if (dividers2 & 0x80000000) { 288 /* the extended PLL part is enabled */ 289 m2 = (dividers2 & 0x000000ff); 290 n2 = (dividers2 & 0x0000ff00) >> 8; 291 LOG(2,("DAC: divider2 is enabled, settings ($%08x): M2=%d, N2=%d\n", dividers2, m2, n2)); 292 } else { 293 LOG(2,("DAC: divider2 is disabled ($%08x)\n", dividers2)); 294 } 295 } 296 297 /* log the frequencies found */ 298 f_phase = si->ps.f_ref / (m1 * m2); 299 f_vco = (f_phase * n1 * n2); 300 f_pixel = f_vco / p1; 301 302 LOG(2,("DAC: phase discriminator frequency is %fMhz\n", f_phase)); 303 LOG(2,("DAC: VCO frequency is %fMhz\n", f_vco)); 304 LOG(2,("DAC: pixelclock is %fMhz\n", f_pixel)); 305 LOG(2,("DAC: end of dump.\n")); 306 307 /* apparantly if a VESA modecall during boot fails we need to explicitly select the PLL's 308 * again (was already done during driver init) if we readout the current PLL setting.. */ 309 if (si->ps.secondary_head) 310 DACW(PLLSEL, 0x30000f00); 311 else 312 DACW(PLLSEL, 0x10000700); 313 } 314 315 316 /* find nearest valid pix pll */ 317 status_t nv_dac_pix_pll_find 318 (display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test) 319 { 320 switch (si->ps.card_type) { 321 default: return nv4_nv10_nv20_dac_pix_pll_find(target, calc_pclk, m_result, n_result, p_result, test); 322 } 323 return B_ERROR; 324 } 325 326 327 /* find nearest valid pixel PLL setting */ 328 static status_t nv4_nv10_nv20_dac_pix_pll_find( 329 display_mode target, float* calc_pclk, uint8* m_result, uint8* n_result, 330 uint8* p_result, uint8 test) 331 { 332 int m = 0, n = 0, p = 0, m_min = 7, p_max = 0x10; 333 float error, error_best = INFINITY; 334 int best[3] = {0, 0, 0}; 335 float f_vco, max_pclk; 336 float req_pclk = target.timing.pixel_clock/1000.0; 337 338 LOG(4, ("DAC: NV4/NV10/NV20 restrictions apply\n")); 339 340 /* determine the max. pixelclock for the current videomode */ 341 switch (target.space) 342 { 343 case B_CMAP8: 344 max_pclk = si->ps.max_dac1_clock_8; 345 break; 346 case B_RGB15_LITTLE: 347 case B_RGB16_LITTLE: 348 max_pclk = si->ps.max_dac1_clock_16; 349 break; 350 case B_RGB24_LITTLE: 351 max_pclk = si->ps.max_dac1_clock_24; 352 break; 353 case B_RGB32_LITTLE: 354 max_pclk = si->ps.max_dac1_clock_32; 355 break; 356 default: 357 /* use fail-safe value */ 358 max_pclk = si->ps.max_dac1_clock_32; 359 break; 360 } 361 /* update PLL divider specs for C51 chipset */ 362 if ((CFGR(DEVID) & 0xfff0ffff) == 0x024010de) { 363 m_min = 4; 364 p_max = 0x20; 365 } 366 /* if some dualhead mode is active, an extra restriction might apply */ 367 if ((target.flags & DUALHEAD_BITS) && (target.space == B_RGB32_LITTLE)) 368 max_pclk = si->ps.max_dac1_clock_32dh; 369 370 /* Make sure the requested pixelclock is within the PLL's operational limits */ 371 /* lower limit is min_pixel_vco divided by highest postscaler-factor */ 372 if (req_pclk < (si->ps.min_pixel_vco / p_max)) 373 { 374 LOG(4,("DAC: clamping pixclock: requested %fMHz, set to %fMHz\n", 375 req_pclk, (float)(si->ps.min_pixel_vco / p_max))); 376 req_pclk = (si->ps.min_pixel_vco / p_max); 377 } 378 /* upper limit is given by pins in combination with current active mode */ 379 if (req_pclk > max_pclk) 380 { 381 LOG(4,("DAC: clamping pixclock: requested %fMHz, set to %fMHz\n", 382 req_pclk, (float)max_pclk)); 383 req_pclk = max_pclk; 384 } 385 386 /* iterate through all valid PLL postscaler settings */ 387 for (p=0x01; p <= p_max; p = p<<1) 388 { 389 /* calculate the needed VCO frequency for this postscaler setting */ 390 f_vco = req_pclk * p; 391 392 /* check if this is within range of the VCO specs */ 393 if ((f_vco >= si->ps.min_pixel_vco) && (f_vco <= si->ps.max_pixel_vco)) 394 { 395 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 396 if (si->ps.ext_pll) f_vco /= 4; 397 398 /* iterate trough all valid reference-frequency postscaler settings */ 399 for (m = m_min; m <= 14; m++) 400 { 401 /* check if phase-discriminator will be within operational limits */ 402 //fixme: PLL calcs will be resetup/splitup/updated... 403 if (si->ps.card_type == NV36) { 404 if (((si->ps.f_ref / m) < 3.2) || ((si->ps.f_ref / m) > 6.4)) continue; 405 } else { 406 if ((CFGR(DEVID) & 0xfff0ffff) == 0x024010de) { 407 /* C51 chipset */ 408 if (((si->ps.f_ref / m) < 1.7) || ((si->ps.f_ref / m) > 6.4)) continue; 409 } else { 410 if (((si->ps.f_ref / m) < 1.0) || ((si->ps.f_ref / m) > 2.0)) continue; 411 } 412 } 413 414 /* calculate VCO postscaler setting for current setup.. */ 415 n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5); 416 417 /* ..and check for validity */ 418 if ((n < 1) || (n > 255)) continue; 419 420 /* find error in frequency this setting gives */ 421 if (si->ps.ext_pll) 422 { 423 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 424 error = fabs((req_pclk / 4) - (((si->ps.f_ref / m) * n) / p)); 425 } 426 else 427 error = fabs(req_pclk - (((si->ps.f_ref / m) * n) / p)); 428 429 /* note the setting if best yet */ 430 if (error < error_best) 431 { 432 error_best = error; 433 best[0]=m; 434 best[1]=n; 435 best[2]=p; 436 } 437 } 438 } 439 } 440 441 /* setup the scalers programming values for found optimum setting */ 442 m = best[0]; 443 n = best[1]; 444 p = best[2]; 445 446 /* log the VCO frequency found */ 447 f_vco = ((si->ps.f_ref / m) * n); 448 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 449 if (si->ps.ext_pll) f_vco *= 4; 450 451 LOG(2,("DAC: pix VCO frequency found %fMhz\n", f_vco)); 452 453 /* return the results */ 454 *calc_pclk = (f_vco / p); 455 *m_result = m; 456 *n_result = n; 457 switch(p) 458 { 459 case 1: 460 p = 0x00; 461 break; 462 case 2: 463 p = 0x01; 464 break; 465 case 4: 466 p = 0x02; 467 break; 468 case 8: 469 p = 0x03; 470 break; 471 case 16: 472 p = 0x04; 473 break; 474 case 32: 475 p = 0x05; 476 break; 477 } 478 *p_result = p; 479 480 /* display the found pixelclock values */ 481 LOG(2,("DAC: pix PLL check: requested %fMHz got %fMHz, mnp 0x%02x 0x%02x 0x%02x\n", 482 req_pclk, *calc_pclk, *m_result, *n_result, *p_result)); 483 484 return B_OK; 485 } 486 487 /* find nearest valid system PLL setting */ 488 status_t nv_dac_sys_pll_find( 489 float req_sclk, float* calc_sclk, uint8* m_result, uint8* n_result, 490 uint8* p_result, uint8 test) 491 { 492 int m = 0, n = 0, p = 0, m_max, p_max; 493 float error, error_best = INFINITY; 494 int best[3] = {0, 0, 0}; 495 float f_vco, discr_low, discr_high; 496 497 /* determine the max. reference-frequency postscaler setting for the 498 * current requested clock */ 499 switch (si->ps.card_arch) 500 { 501 case NV04A: 502 LOG(4, ("DAC: NV04 restrictions apply\n")); 503 /* set phase-discriminator frequency range (Mhz) (verified) */ 504 discr_low = 1.0; 505 discr_high = 2.0; 506 /* set max. useable reference frequency postscaler divider factor */ 507 m_max = 14; 508 /* set max. useable VCO output postscaler divider factor */ 509 p_max = 16; 510 break; 511 default: 512 switch (si->ps.card_type) 513 { 514 case NV28: 515 //fixme: how about some other cards??? 516 LOG(4, ("DAC: NV28 restrictions apply\n")); 517 /* set max. useable reference frequency postscaler divider factor; 518 * apparantly we would get distortions on high PLL output frequencies if 519 * we use the phase-discriminator at low frequencies */ 520 if (req_sclk > 340.0) m_max = 2; /* Fpll > 340Mhz */ 521 else if (req_sclk > 200.0) m_max = 4; /* 200Mhz < Fpll <= 340Mhz */ 522 else if (req_sclk > 150.0) m_max = 6; /* 150Mhz < Fpll <= 200Mhz */ 523 else m_max = 14; /* Fpll < 150Mhz */ 524 525 /* set max. useable VCO output postscaler divider factor */ 526 p_max = 32; 527 /* set phase-discriminator frequency range (Mhz) (verified) */ 528 discr_low = 1.0; 529 discr_high = 27.0; 530 break; 531 default: 532 LOG(4, ("DAC: NV10/NV20/NV30 restrictions apply\n")); 533 /* set max. useable reference frequency postscaler divider factor; 534 * apparantly we would get distortions on high PLL output frequencies if 535 * we use the phase-discriminator at low frequencies */ 536 if (req_sclk > 340.0) m_max = 2; /* Fpll > 340Mhz */ 537 else if (req_sclk > 250.0) m_max = 6; /* 250Mhz < Fpll <= 340Mhz */ 538 else m_max = 14; /* Fpll < 250Mhz */ 539 540 /* set max. useable VCO output postscaler divider factor */ 541 p_max = 16; 542 /* set phase-discriminator frequency range (Mhz) (verified) */ 543 if (si->ps.card_type == NV36) discr_low = 3.2; 544 else discr_low = 1.0; 545 /* (high discriminator spec is failsafe) */ 546 discr_high = 14.0; 547 break; 548 } 549 break; 550 } 551 552 LOG(4, ("DAC: PLL reference frequency postscaler divider range is 1 - %d\n", m_max)); 553 LOG(4, ("DAC: PLL VCO output postscaler divider range is 1 - %d\n", p_max)); 554 LOG(4, ("DAC: PLL discriminator input frequency range is %2.2fMhz - %2.2fMhz\n", 555 discr_low, discr_high)); 556 557 /* Make sure the requested clock is within the PLL's operational limits */ 558 /* lower limit is min_system_vco divided by highest postscaler-factor */ 559 if (req_sclk < (si->ps.min_system_vco / ((float)p_max))) 560 { 561 LOG(4, ("DAC: clamping sysclock: requested %fMHz, set to %fMHz\n", 562 req_sclk, (si->ps.min_system_vco / ((float)p_max)))); 563 req_sclk = (si->ps.min_system_vco / ((float)p_max)); 564 } 565 /* upper limit is given by pins */ 566 if (req_sclk > si->ps.max_system_vco) 567 { 568 LOG(4, ("DAC: clamping sysclock: requested %fMHz, set to %fMHz\n", 569 req_sclk, (float)si->ps.max_system_vco)); 570 req_sclk = si->ps.max_system_vco; 571 } 572 573 /* iterate through all valid PLL postscaler settings */ 574 for (p=0x01; p <= p_max; p = p<<1) 575 { 576 /* calculate the needed VCO frequency for this postscaler setting */ 577 f_vco = req_sclk * p; 578 579 /* check if this is within range of the VCO specs */ 580 if ((f_vco >= si->ps.min_system_vco) && (f_vco <= si->ps.max_system_vco)) 581 { 582 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 583 if (si->ps.ext_pll) f_vco /= 4; 584 585 /* iterate trough all valid reference-frequency postscaler settings */ 586 for (m = 1; m <= m_max; m++) 587 { 588 /* check if phase-discriminator will be within operational limits */ 589 if (((si->ps.f_ref / m) < discr_low) || ((si->ps.f_ref / m) > discr_high)) 590 continue; 591 592 /* calculate VCO postscaler setting for current setup.. */ 593 n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5); 594 595 /* ..and check for validity */ 596 if ((n < 1) || (n > 255)) continue; 597 598 /* find error in frequency this setting gives */ 599 if (si->ps.ext_pll) 600 { 601 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 602 error = fabs((req_sclk / 4) - (((si->ps.f_ref / m) * n) / p)); 603 } 604 else 605 error = fabs(req_sclk - (((si->ps.f_ref / m) * n) / p)); 606 607 /* note the setting if best yet */ 608 if (error < error_best) 609 { 610 error_best = error; 611 best[0]=m; 612 best[1]=n; 613 best[2]=p; 614 } 615 } 616 } 617 } 618 619 /* setup the scalers programming values for found optimum setting */ 620 m = best[0]; 621 n = best[1]; 622 p = best[2]; 623 624 /* log the VCO frequency found */ 625 f_vco = ((si->ps.f_ref / m) * n); 626 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 627 if (si->ps.ext_pll) f_vco *= 4; 628 629 LOG(2,("DAC: sys VCO frequency found %fMhz\n", f_vco)); 630 631 /* return the results */ 632 *calc_sclk = (f_vco / p); 633 *m_result = m; 634 *n_result = n; 635 switch(p) 636 { 637 case 1: 638 p = 0x00; 639 break; 640 case 2: 641 p = 0x01; 642 break; 643 case 4: 644 p = 0x02; 645 break; 646 case 8: 647 p = 0x03; 648 break; 649 case 16: 650 p = 0x04; 651 break; 652 case 32: 653 p = 0x05; 654 break; 655 } 656 *p_result = p; 657 658 /* display the found pixelclock values */ 659 LOG(2,("DAC: sys PLL check: requested %fMHz got %fMHz, mnp 0x%02x 0x%02x 0x%02x\n", 660 req_sclk, *calc_sclk, *m_result, *n_result, *p_result)); 661 662 return B_OK; 663 } 664