1 /* program the DAC */ 2 /* Author: 3 Rudolf Cornelissen 12/2003-1/2004 4 */ 5 6 #define MODULE_BIT 0x00010000 7 8 #include "nv_std.h" 9 10 static status_t nv4_nv10_nv20_dac_pix_pll_find( 11 display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test); 12 static status_t g100_g400max_dac_sys_pll_find( 13 float req_sclk,float * calc_sclk,uint8 * m_result,uint8 * n_result,uint8 * p_result); 14 15 /* see if an analog VGA monitor is connected to DAC */ 16 bool nv_dac_crt_connected(void) 17 { 18 uint32 output, dac; 19 bool present; 20 21 //fixme? checkout NV11... 22 /* save output connector setting */ 23 output = DACR(OUTPUT); 24 /* save DAC state */ 25 dac = DACR(TSTCTRL); 26 27 /* turn on DAC */ 28 DACW(TSTCTRL, (DACR(TSTCTRL) & 0xfffeffff)); 29 /* select primary head and turn off CRT (and DVI?) outputs */ 30 DACW(OUTPUT, (output & 0x0000feee)); 31 /* wait for signal lines to stabilize */ 32 snooze(1000); 33 /* re-enable CRT output */ 34 DACW(OUTPUT, (DACR(OUTPUT) | 0x00000001)); 35 36 /* setup RGB test signal levels to approx 30% of DAC range and enable them */ 37 DACW(TSTDATA, ((0x2 << 30) | (0x140 << 20) | (0x140 << 10) | (0x140 << 0))); 38 /* route test signals to output */ 39 DACW(TSTCTRL, (DACR(TSTCTRL) | 0x00001000)); 40 /* wait for signal lines to stabilize */ 41 snooze(1000); 42 43 /* do actual detection: all signals paths high == CRT connected */ 44 if (DACR(TSTCTRL) & 0x10000000) 45 { 46 present = true; 47 LOG(4,("DAC: CRT detected\n")); 48 } 49 else 50 { 51 present = false; 52 LOG(4,("DAC: no CRT detected\n")); 53 } 54 55 /* kill test signal routing */ 56 DACW(TSTCTRL, (DACR(TSTCTRL) & 0xffffefff)); 57 58 /* restore output connector setting */ 59 DACW(OUTPUT, output); 60 /* restore DAC state */ 61 DACW(TSTCTRL, dac); 62 63 return present; 64 } 65 66 /*set the mode, brightness is a value from 0->2 (where 1 is equivalent to direct)*/ 67 status_t nv_dac_mode(int mode,float brightness) 68 { 69 uint8 *r,*g,*b; 70 int i, ri; 71 72 /*set colour arrays to point to space reserved in shared info*/ 73 r = si->color_data; 74 g = r + 256; 75 b = g + 256; 76 77 LOG(4,("DAC: Setting screen mode %d brightness %f\n", mode, brightness)); 78 /* init the palette for brightness specified */ 79 /* (Nvidia cards always use MSbits from screenbuffer as index for PAL) */ 80 for (i = 0; i < 256; i++) 81 { 82 ri = i * brightness; 83 if (ri > 255) ri = 255; 84 b[i] = g[i] = r[i] = ri; 85 } 86 87 if (nv_dac_palette(r,g,b) != B_OK) return B_ERROR; 88 89 /* disable palette RAM adressing mask */ 90 NV_REG8(NV8_PALMASK) = 0xff; 91 LOG(2,("DAC: PAL pixrdmsk readback $%02x\n", NV_REG8(NV8_PALMASK))); 92 93 return B_OK; 94 } 95 96 /*program the DAC palette using the given r,g,b values*/ 97 status_t nv_dac_palette(uint8 r[256],uint8 g[256],uint8 b[256]) 98 { 99 int i; 100 101 LOG(4,("DAC: setting palette\n")); 102 103 /* select first PAL adress before starting programming */ 104 NV_REG8(NV8_PALINDW) = 0x00; 105 106 /* loop through all 256 to program DAC */ 107 for (i = 0; i < 256; i++) 108 { 109 /* the 6 implemented bits are on b0-b5 of the bus */ 110 NV_REG8(NV8_PALDATA) = r[i]; 111 NV_REG8(NV8_PALDATA) = g[i]; 112 NV_REG8(NV8_PALDATA) = b[i]; 113 } 114 if (NV_REG8(NV8_PALINDW) != 0x00) 115 { 116 LOG(8,("DAC: PAL write index incorrect after programming\n")); 117 return B_ERROR; 118 } 119 if (1) 120 {//reread LUT 121 uint8 R, G, B; 122 123 /* select first PAL adress to read (modulo 3 counter) */ 124 NV_REG8(NV8_PALINDR) = 0x00; 125 for (i = 0; i < 256; i++) 126 { 127 R = NV_REG8(NV8_PALDATA); 128 G = NV_REG8(NV8_PALDATA); 129 B = NV_REG8(NV8_PALDATA); 130 if ((r[i] != R) || (g[i] != G) || (b[i] != B)) 131 LOG(1,("DAC palette %d: w %x %x %x, r %x %x %x\n", i, r[i], g[i], b[i], R, G, B)); // apsed 132 } 133 } 134 135 return B_OK; 136 } 137 138 /*program the pixpll - frequency in kHz*/ 139 status_t nv_dac_set_pix_pll(display_mode target) 140 { 141 uint8 m=0,n=0,p=0; 142 // uint time = 0; 143 144 float pix_setting, req_pclk; 145 status_t result; 146 147 req_pclk = (target.timing.pixel_clock)/1000.0; 148 LOG(4,("DAC: Setting PIX PLL for pixelclock %f\n", req_pclk)); 149 150 /* signal that we actually want to set the mode */ 151 result = nv_dac_pix_pll_find(target,&pix_setting,&m,&n,&p, 1); 152 if (result != B_OK) 153 { 154 return result; 155 } 156 157 /*reprogram (disable,select,wait for stability,enable)*/ 158 // DXIW(PIXCLKCTRL,(DXIR(PIXCLKCTRL)&0x0F)|0x04); /*disable the PIXPLL*/ 159 // DXIW(PIXCLKCTRL,(DXIR(PIXCLKCTRL)&0x0C)|0x01); /*select the PIXPLL*/ 160 161 /* program new frequency */ 162 DACW(PIXPLLC, ((p << 16) | (n << 8) | m)); 163 164 /* program 2nd set N and M scalers if they exist (b31=1 enables them) */ 165 if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) 166 DACW(PIXPLLC2, 0x80000401); 167 168 /* Wait for the PIXPLL frequency to lock until timeout occurs */ 169 //fixme: do NV cards have a LOCK indication bit?? 170 /* while((!(DXIR(PIXPLLSTAT)&0x40)) & (time <= 2000)) 171 { 172 time++; 173 snooze(1); 174 } 175 176 if (time > 2000) 177 LOG(2,("DAC: PIX PLL frequency not locked!\n")); 178 else 179 LOG(2,("DAC: PIX PLL frequency locked\n")); 180 DXIW(PIXCLKCTRL,DXIR(PIXCLKCTRL)&0x0B); //enable the PIXPLL 181 */ 182 183 //for now: 184 /* Give the PIXPLL frequency some time to lock... */ 185 snooze(1000); 186 LOG(2,("DAC: PIX PLL frequency should be locked now...\n")); 187 188 return B_OK; 189 } 190 191 /* find nearest valid pix pll */ 192 status_t nv_dac_pix_pll_find 193 (display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test) 194 { 195 switch (si->ps.card_type) { 196 default: return nv4_nv10_nv20_dac_pix_pll_find(target, calc_pclk, m_result, n_result, p_result, test); 197 } 198 return B_ERROR; 199 } 200 201 /* find nearest valid pixel PLL setting */ 202 static status_t nv4_nv10_nv20_dac_pix_pll_find( 203 display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test) 204 { 205 int m = 0, n = 0, p = 0/*, m_max*/; 206 float error, error_best = 999999999; 207 int best[3]; 208 float f_vco, max_pclk; 209 float req_pclk = target.timing.pixel_clock/1000.0; 210 211 /* determine the max. reference-frequency postscaler setting for the 212 * current card (see G100, G200 and G400 specs). */ 213 /* switch(si->ps.card_type) 214 { 215 case G100: 216 LOG(4,("DAC: G100 restrictions apply\n")); 217 m_max = 7; 218 break; 219 case G200: 220 LOG(4,("DAC: G200 restrictions apply\n")); 221 m_max = 7; 222 break; 223 default: 224 LOG(4,("DAC: G400/G400MAX restrictions apply\n")); 225 m_max = 32; 226 break; 227 } 228 */ 229 LOG(4,("DAC: NV4/NV10/NV20 restrictions apply\n")); 230 231 /* determine the max. pixelclock for the current videomode */ 232 switch (target.space) 233 { 234 case B_CMAP8: 235 max_pclk = si->ps.max_dac1_clock_8; 236 break; 237 case B_RGB15_LITTLE: 238 case B_RGB16_LITTLE: 239 max_pclk = si->ps.max_dac1_clock_16; 240 break; 241 case B_RGB24_LITTLE: 242 max_pclk = si->ps.max_dac1_clock_24; 243 break; 244 case B_RGB32_LITTLE: 245 max_pclk = si->ps.max_dac1_clock_32; 246 break; 247 default: 248 /* use fail-safe value */ 249 max_pclk = si->ps.max_dac1_clock_32; 250 break; 251 } 252 /* if some dualhead mode is active, an extra restriction might apply */ 253 if ((target.flags & DUALHEAD_BITS) && (target.space == B_RGB32_LITTLE)) 254 max_pclk = si->ps.max_dac1_clock_32dh; 255 256 /* Make sure the requested pixelclock is within the PLL's operational limits */ 257 /* lower limit is min_pixel_vco divided by highest postscaler-factor */ 258 if (req_pclk < (si->ps.min_pixel_vco / 16.0)) 259 { 260 LOG(4,("DAC: clamping pixclock: requested %fMHz, set to %fMHz\n", 261 req_pclk, (float)(si->ps.min_pixel_vco / 16.0))); 262 req_pclk = (si->ps.min_pixel_vco / 16.0); 263 } 264 /* upper limit is given by pins in combination with current active mode */ 265 if (req_pclk > max_pclk) 266 { 267 LOG(4,("DAC: clamping pixclock: requested %fMHz, set to %fMHz\n", 268 req_pclk, (float)max_pclk)); 269 req_pclk = max_pclk; 270 } 271 272 /* iterate through all valid PLL postscaler settings */ 273 for (p=0x01; p < 0x20; p = p<<1) 274 { 275 /* calculate the needed VCO frequency for this postscaler setting */ 276 f_vco = req_pclk * p; 277 278 /* check if this is within range of the VCO specs */ 279 if ((f_vco >= si->ps.min_pixel_vco) && (f_vco <= si->ps.max_pixel_vco)) 280 { 281 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 282 if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) f_vco /= 4; 283 284 /* iterate trough all valid reference-frequency postscaler settings */ 285 for (m = 7; m <= 14; m++) 286 { 287 /* check if phase-discriminator will be within operational limits */ 288 if (((si->ps.f_ref / m) < 1.0) || ((si->ps.f_ref / m) > 2.0)) continue; 289 290 /* calculate VCO postscaler setting for current setup.. */ 291 n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5); 292 293 /* ..and check for validity */ 294 if ((n < 1) || (n > 255)) continue; 295 296 /* find error in frequency this setting gives */ 297 if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) 298 { 299 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 300 error = fabs((req_pclk / 4) - (((si->ps.f_ref / m) * n) / p)); 301 } 302 else 303 error = fabs(req_pclk - (((si->ps.f_ref / m) * n) / p)); 304 305 /* note the setting if best yet */ 306 if (error < error_best) 307 { 308 error_best = error; 309 best[0]=m; 310 best[1]=n; 311 best[2]=p; 312 } 313 } 314 } 315 } 316 317 /* setup the scalers programming values for found optimum setting */ 318 m = best[0]; 319 n = best[1]; 320 p = best[2]; 321 322 /* log the VCO frequency found */ 323 f_vco = ((si->ps.f_ref / m) * n); 324 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 325 if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) f_vco *= 4; 326 327 LOG(2,("DAC: pix VCO frequency found %fMhz\n", f_vco)); 328 329 /* return the results */ 330 *calc_pclk = (f_vco / p); 331 *m_result = m; 332 *n_result = n; 333 switch(p) 334 { 335 case 1: 336 p = 0x00; 337 break; 338 case 2: 339 p = 0x01; 340 break; 341 case 4: 342 p = 0x02; 343 break; 344 case 8: 345 p = 0x03; 346 break; 347 case 16: 348 p = 0x04; 349 break; 350 } 351 *p_result = p; 352 353 /* display the found pixelclock values */ 354 LOG(2,("DAC: pix PLL check: requested %fMHz got %fMHz, mnp 0x%02x 0x%02x 0x%02x\n", 355 req_pclk, *calc_pclk, *m_result, *n_result, *p_result)); 356 357 return B_OK; 358 } 359 360 /* find nearest valid system PLL setting */ 361 static status_t g100_g400max_dac_sys_pll_find( 362 float req_sclk,float * calc_sclk,uint8 * m_result,uint8 * n_result,uint8 * p_result) 363 { 364 int m = 0, n = 0, p = 0, m_max; 365 float error, error_best = 999999999; 366 int best[3]; 367 float f_vco; 368 369 /* determine the max. reference-frequency postscaler setting for the 370 * current card (see G100, G200 and G400 specs). */ 371 switch(si->ps.card_type) 372 { 373 /* case G100: 374 LOG(4,("DAC: G100 restrictions apply\n")); 375 m_max = 7; 376 break; 377 case G200: 378 LOG(4,("DAC: G200 restrictions apply\n")); 379 m_max = 7; 380 break; 381 */ default: 382 LOG(4,("DAC: G400/G400MAX restrictions apply\n")); 383 m_max = 32; 384 break; 385 } 386 387 /* Make sure the requested systemclock is within the PLL's operational limits */ 388 /* lower limit is min_system_vco divided by highest postscaler-factor */ 389 if (req_sclk < (si->ps.min_system_vco / 8.0)) 390 { 391 LOG(4,("DAC: clamping sysclock: requested %fMHz, set to %fMHz\n", 392 req_sclk, (float)(si->ps.min_system_vco / 8.0))); 393 req_sclk = (si->ps.min_system_vco / 8.0); 394 } 395 /* upper limit is max_system_vco */ 396 if (req_sclk > si->ps.max_system_vco) 397 { 398 LOG(4,("DAC: clamping sysclock: requested %fMHz, set to %fMHz\n", 399 req_sclk, (float)si->ps.max_system_vco)); 400 req_sclk = si->ps.max_system_vco; 401 } 402 403 /* iterate through all valid PLL postscaler settings */ 404 for (p=0x01; p < 0x10; p = p<<1) 405 { 406 /* calculate the needed VCO frequency for this postscaler setting */ 407 f_vco = req_sclk * p; 408 409 /* check if this is within range of the VCO specs */ 410 if ((f_vco >= si->ps.min_system_vco) && (f_vco <= si->ps.max_system_vco)) 411 { 412 /* iterate trough all valid reference-frequency postscaler settings */ 413 for (m = 2; m <= m_max; m++) 414 { 415 /* calculate VCO postscaler setting for current setup.. */ 416 n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5); 417 /* ..and check for validity */ 418 if ((n < 8) || (n > 128)) continue; 419 420 /* find error in frequency this setting gives */ 421 error = fabs(req_sclk - (((si->ps.f_ref / m) * n) / p)); 422 423 /* note the setting if best yet */ 424 if (error < error_best) 425 { 426 error_best = error; 427 best[0]=m; 428 best[1]=n; 429 best[2]=p; 430 } 431 } 432 } 433 } 434 435 /* setup the scalers programming values for found optimum setting */ 436 m=best[0] - 1; 437 n=best[1] - 1; 438 p=best[2] - 1; 439 440 /* calc the needed PLL loopbackfilter setting belonging to current VCO speed, 441 * for the current card (see G100, G200 and G400 specs). */ 442 f_vco = (si->ps.f_ref / (m + 1)) * (n + 1); 443 LOG(2,("DAC: sys VCO frequency found %fMhz\n", f_vco)); 444 445 switch(si->ps.card_type) 446 { 447 default: 448 for(;;) 449 { 450 if (f_vco >= 240) {p |= (0x03 << 3); break;}; 451 if (f_vco >= 170) {p |= (0x02 << 3); break;}; 452 if (f_vco >= 110) {p |= (0x01 << 3); break;}; 453 break; 454 } 455 break; 456 } 457 458 /* return the results */ 459 *calc_sclk = f_vco / ((p & 0x07) + 1); 460 *m_result = m; 461 *n_result = n; 462 *p_result = p; 463 464 /* display the found pixelclock values */ 465 LOG(2,("DAC: sys PLL check: requested %fMHz got %fMHz, mnp 0x%02x 0x%02x 0x%02x\n", 466 req_sclk, *calc_sclk, *m_result, *n_result, *p_result)); 467 468 return B_OK; 469 } 470 471 /*set up system pll - NB mclk is memory clock */ 472 status_t g400_dac_set_sys_pll() 473 { 474 /* values for DAC sys pll registers */ 475 uint8 m, n, p; 476 // uint time = 0; 477 float calc_sclk; 478 479 LOG(1,("DAC: Setting up G400/G400MAX system clock\n")); 480 g100_g400max_dac_sys_pll_find((float)si->ps.std_engine_clock, &calc_sclk, &m, &n, &p); 481 482 /* reprogram the clock - set PCI/AGP, program, set to programmed */ 483 /* clear, so don't o/clock addons */ 484 // CFGW(OPTION2, 0); 485 /* disable the SYSPLL */ 486 // CFGW(OPTION, CFGR(OPTION) | 0x04); 487 /* select the PCI/AGP clock */ 488 // CFGW(OPTION3, 0); 489 /* enable the SYSPLL */ 490 // CFGW(OPTION, CFGR(OPTION) & 0xfffffffb); 491 492 /* program the new clock */ 493 // DXIW(SYSPLLM, m); 494 // DXIW(SYSPLLN, n); 495 // DXIW(SYSPLLP, p); 496 497 /* Wait for the SYSPLL frequency to lock until timeout occurs */ 498 /* while((!(DXIR(SYSPLLSTAT)&0x40)) & (time <= 2000)) 499 { 500 time++; 501 snooze(1); 502 } 503 504 if (time > 2000) 505 LOG(2,("DAC: sys PLL frequency not locked!\n")); 506 else 507 LOG(2,("DAC: sys PLL frequency locked\n")); 508 */ 509 /* disable the SYSPLL */ 510 // CFGW(OPTION, CFGR(OPTION) | 0x04); 511 /* setup Gclk, Mclk and Wclk divs via PINS and select SYSPLL as system clock source */ 512 // CFGW(OPTION3, si->ps.option3_reg); 513 /* make sure the PLLs are not swapped (set default config) */ 514 // CFGW(OPTION, CFGR(OPTION) & 0xffffffbf); 515 /* enable the SYSPLL (and make sure the SYSPLL is indeed powered up) */ 516 // CFGW(OPTION, (CFGR(OPTION) & 0xfffffffb) | 0x20); 517 518 return B_OK; 519 } 520