1 /* program the DAC */ 2 /* Author: 3 Rudolf Cornelissen 12/2003-3/2004 4 */ 5 6 #define MODULE_BIT 0x00010000 7 8 #include "nv_std.h" 9 10 static status_t nv4_nv10_nv20_dac_pix_pll_find( 11 display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test); 12 static status_t g100_g400max_dac_sys_pll_find( 13 float req_sclk,float * calc_sclk,uint8 * m_result,uint8 * n_result,uint8 * p_result); 14 15 /* see if an analog VGA monitor is connected to DAC */ 16 bool nv_dac_crt_connected(void) 17 { 18 uint32 output, dac; 19 bool present; 20 21 //fixme? checkout NV11... 22 /* save output connector setting */ 23 output = DACR(OUTPUT); 24 /* save DAC state */ 25 dac = DACR(TSTCTRL); 26 27 /* turn on DAC */ 28 DACW(TSTCTRL, (DACR(TSTCTRL) & 0xfffeffff)); 29 /* select primary head and turn off CRT (and DVI?) outputs */ 30 DACW(OUTPUT, (output & 0x0000feee)); 31 /* wait for signal lines to stabilize */ 32 snooze(1000); 33 /* re-enable CRT output */ 34 DACW(OUTPUT, (DACR(OUTPUT) | 0x00000001)); 35 36 /* setup RGB test signal levels to approx 30% of DAC range and enable them */ 37 DACW(TSTDATA, ((0x2 << 30) | (0x140 << 20) | (0x140 << 10) | (0x140 << 0))); 38 /* route test signals to output */ 39 DACW(TSTCTRL, (DACR(TSTCTRL) | 0x00001000)); 40 /* wait for signal lines to stabilize */ 41 snooze(1000); 42 43 /* do actual detection: all signals paths high == CRT connected */ 44 if (DACR(TSTCTRL) & 0x10000000) 45 { 46 present = true; 47 LOG(4,("DAC: CRT detected\n")); 48 } 49 else 50 { 51 present = false; 52 LOG(4,("DAC: no CRT detected\n")); 53 } 54 55 /* kill test signal routing */ 56 DACW(TSTCTRL, (DACR(TSTCTRL) & 0xffffefff)); 57 58 /* restore output connector setting */ 59 DACW(OUTPUT, output); 60 /* restore DAC state */ 61 DACW(TSTCTRL, dac); 62 63 return present; 64 } 65 66 /*set the mode, brightness is a value from 0->2 (where 1 is equivalent to direct)*/ 67 status_t nv_dac_mode(int mode,float brightness) 68 { 69 uint8 *r,*g,*b; 70 int i, ri; 71 72 /*set colour arrays to point to space reserved in shared info*/ 73 r = si->color_data; 74 g = r + 256; 75 b = g + 256; 76 77 LOG(4,("DAC: Setting screen mode %d brightness %f\n", mode, brightness)); 78 /* init the palette for brightness specified */ 79 /* (Nvidia cards always use MSbits from screenbuffer as index for PAL) */ 80 for (i = 0; i < 256; i++) 81 { 82 ri = i * brightness; 83 if (ri > 255) ri = 255; 84 b[i] = g[i] = r[i] = ri; 85 } 86 87 if (nv_dac_palette(r,g,b) != B_OK) return B_ERROR; 88 89 /* disable palette RAM adressing mask */ 90 NV_REG8(NV8_PALMASK) = 0xff; 91 LOG(2,("DAC: PAL pixrdmsk readback $%02x\n", NV_REG8(NV8_PALMASK))); 92 93 return B_OK; 94 } 95 96 /*program the DAC palette using the given r,g,b values*/ 97 status_t nv_dac_palette(uint8 r[256],uint8 g[256],uint8 b[256]) 98 { 99 int i; 100 101 LOG(4,("DAC: setting palette\n")); 102 103 /* select first PAL adress before starting programming */ 104 NV_REG8(NV8_PALINDW) = 0x00; 105 106 /* loop through all 256 to program DAC */ 107 for (i = 0; i < 256; i++) 108 { 109 /* the 6 implemented bits are on b0-b5 of the bus */ 110 NV_REG8(NV8_PALDATA) = r[i]; 111 NV_REG8(NV8_PALDATA) = g[i]; 112 NV_REG8(NV8_PALDATA) = b[i]; 113 } 114 if (NV_REG8(NV8_PALINDW) != 0x00) 115 { 116 LOG(8,("DAC: PAL write index incorrect after programming\n")); 117 return B_ERROR; 118 } 119 if (1) 120 {//reread LUT 121 uint8 R, G, B; 122 123 /* select first PAL adress to read (modulo 3 counter) */ 124 NV_REG8(NV8_PALINDR) = 0x00; 125 for (i = 0; i < 256; i++) 126 { 127 R = NV_REG8(NV8_PALDATA); 128 G = NV_REG8(NV8_PALDATA); 129 B = NV_REG8(NV8_PALDATA); 130 if ((r[i] != R) || (g[i] != G) || (b[i] != B)) 131 LOG(1,("DAC palette %d: w %x %x %x, r %x %x %x\n", i, r[i], g[i], b[i], R, G, B)); // apsed 132 } 133 } 134 135 return B_OK; 136 } 137 138 /*program the pixpll - frequency in kHz*/ 139 status_t nv_dac_set_pix_pll(display_mode target) 140 { 141 uint8 m=0,n=0,p=0; 142 // uint time = 0; 143 144 float pix_setting, req_pclk; 145 status_t result; 146 147 /* fix a DVI or laptop flatpanel to 60Hz refresh! */ 148 /* Note: 149 * The pixelclock drives the flatpanel modeline, not the CRTC modeline. */ 150 if (si->ps.tmds1_active) 151 { 152 LOG(4,("DAC: Fixing DFP refresh to 60Hz!\n")); 153 154 /* readout the panel's modeline to determine the needed pixelclock */ 155 target.timing.pixel_clock = ( 156 ((DACR(FP_HTOTAL) & 0x0000ffff) + 1) * 157 ((DACR(FP_VTOTAL) & 0x0000ffff) + 1) * 158 60) / 1000; 159 } 160 161 req_pclk = (target.timing.pixel_clock)/1000.0; 162 LOG(4,("DAC: Setting PIX PLL for pixelclock %f\n", req_pclk)); 163 164 /* signal that we actually want to set the mode */ 165 result = nv_dac_pix_pll_find(target,&pix_setting,&m,&n,&p, 1); 166 if (result != B_OK) 167 { 168 return result; 169 } 170 171 /*reprogram (disable,select,wait for stability,enable)*/ 172 // DXIW(PIXCLKCTRL,(DXIR(PIXCLKCTRL)&0x0F)|0x04); /*disable the PIXPLL*/ 173 // DXIW(PIXCLKCTRL,(DXIR(PIXCLKCTRL)&0x0C)|0x01); /*select the PIXPLL*/ 174 175 /* program new frequency */ 176 DACW(PIXPLLC, ((p << 16) | (n << 8) | m)); 177 178 /* program 2nd set N and M scalers if they exist (b31=1 enables them) */ 179 if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) 180 DACW(PIXPLLC2, 0x80000401); 181 182 /* Wait for the PIXPLL frequency to lock until timeout occurs */ 183 //fixme: do NV cards have a LOCK indication bit?? 184 /* while((!(DXIR(PIXPLLSTAT)&0x40)) & (time <= 2000)) 185 { 186 time++; 187 snooze(1); 188 } 189 190 if (time > 2000) 191 LOG(2,("DAC: PIX PLL frequency not locked!\n")); 192 else 193 LOG(2,("DAC: PIX PLL frequency locked\n")); 194 DXIW(PIXCLKCTRL,DXIR(PIXCLKCTRL)&0x0B); //enable the PIXPLL 195 */ 196 197 //for now: 198 /* Give the PIXPLL frequency some time to lock... */ 199 snooze(1000); 200 LOG(2,("DAC: PIX PLL frequency should be locked now...\n")); 201 202 return B_OK; 203 } 204 205 /* find nearest valid pix pll */ 206 status_t nv_dac_pix_pll_find 207 (display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test) 208 { 209 switch (si->ps.card_type) { 210 default: return nv4_nv10_nv20_dac_pix_pll_find(target, calc_pclk, m_result, n_result, p_result, test); 211 } 212 return B_ERROR; 213 } 214 215 /* find nearest valid pixel PLL setting */ 216 static status_t nv4_nv10_nv20_dac_pix_pll_find( 217 display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test) 218 { 219 int m = 0, n = 0, p = 0/*, m_max*/; 220 float error, error_best = 999999999; 221 int best[3]; 222 float f_vco, max_pclk; 223 float req_pclk = target.timing.pixel_clock/1000.0; 224 225 /* determine the max. reference-frequency postscaler setting for the 226 * current card (see G100, G200 and G400 specs). */ 227 /* switch(si->ps.card_type) 228 { 229 case G100: 230 LOG(4,("DAC: G100 restrictions apply\n")); 231 m_max = 7; 232 break; 233 case G200: 234 LOG(4,("DAC: G200 restrictions apply\n")); 235 m_max = 7; 236 break; 237 default: 238 LOG(4,("DAC: G400/G400MAX restrictions apply\n")); 239 m_max = 32; 240 break; 241 } 242 */ 243 LOG(4,("DAC: NV4/NV10/NV20 restrictions apply\n")); 244 245 /* determine the max. pixelclock for the current videomode */ 246 switch (target.space) 247 { 248 case B_CMAP8: 249 max_pclk = si->ps.max_dac1_clock_8; 250 break; 251 case B_RGB15_LITTLE: 252 case B_RGB16_LITTLE: 253 max_pclk = si->ps.max_dac1_clock_16; 254 break; 255 case B_RGB24_LITTLE: 256 max_pclk = si->ps.max_dac1_clock_24; 257 break; 258 case B_RGB32_LITTLE: 259 max_pclk = si->ps.max_dac1_clock_32; 260 break; 261 default: 262 /* use fail-safe value */ 263 max_pclk = si->ps.max_dac1_clock_32; 264 break; 265 } 266 /* if some dualhead mode is active, an extra restriction might apply */ 267 if ((target.flags & DUALHEAD_BITS) && (target.space == B_RGB32_LITTLE)) 268 max_pclk = si->ps.max_dac1_clock_32dh; 269 270 /* Make sure the requested pixelclock is within the PLL's operational limits */ 271 /* lower limit is min_pixel_vco divided by highest postscaler-factor */ 272 if (req_pclk < (si->ps.min_pixel_vco / 16.0)) 273 { 274 LOG(4,("DAC: clamping pixclock: requested %fMHz, set to %fMHz\n", 275 req_pclk, (float)(si->ps.min_pixel_vco / 16.0))); 276 req_pclk = (si->ps.min_pixel_vco / 16.0); 277 } 278 /* upper limit is given by pins in combination with current active mode */ 279 if (req_pclk > max_pclk) 280 { 281 LOG(4,("DAC: clamping pixclock: requested %fMHz, set to %fMHz\n", 282 req_pclk, (float)max_pclk)); 283 req_pclk = max_pclk; 284 } 285 286 /* iterate through all valid PLL postscaler settings */ 287 for (p=0x01; p < 0x20; p = p<<1) 288 { 289 /* calculate the needed VCO frequency for this postscaler setting */ 290 f_vco = req_pclk * p; 291 292 /* check if this is within range of the VCO specs */ 293 if ((f_vco >= si->ps.min_pixel_vco) && (f_vco <= si->ps.max_pixel_vco)) 294 { 295 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 296 if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) f_vco /= 4; 297 298 /* iterate trough all valid reference-frequency postscaler settings */ 299 for (m = 7; m <= 14; m++) 300 { 301 /* check if phase-discriminator will be within operational limits */ 302 //fixme: PLL calcs will be resetup/splitup/updated... 303 if (si->ps.card_type == NV36) 304 { 305 if (((si->ps.f_ref / m) < 3.2) || ((si->ps.f_ref / m) > 6.4)) continue; 306 } 307 else 308 { 309 if (((si->ps.f_ref / m) < 1.0) || ((si->ps.f_ref / m) > 2.0)) continue; 310 } 311 312 /* calculate VCO postscaler setting for current setup.. */ 313 n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5); 314 315 /* ..and check for validity */ 316 if ((n < 1) || (n > 255)) continue; 317 318 /* find error in frequency this setting gives */ 319 if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) 320 { 321 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 322 error = fabs((req_pclk / 4) - (((si->ps.f_ref / m) * n) / p)); 323 } 324 else 325 error = fabs(req_pclk - (((si->ps.f_ref / m) * n) / p)); 326 327 /* note the setting if best yet */ 328 if (error < error_best) 329 { 330 error_best = error; 331 best[0]=m; 332 best[1]=n; 333 best[2]=p; 334 } 335 } 336 } 337 } 338 339 /* setup the scalers programming values for found optimum setting */ 340 m = best[0]; 341 n = best[1]; 342 p = best[2]; 343 344 /* log the VCO frequency found */ 345 f_vco = ((si->ps.f_ref / m) * n); 346 /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ 347 if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) f_vco *= 4; 348 349 LOG(2,("DAC: pix VCO frequency found %fMhz\n", f_vco)); 350 351 /* return the results */ 352 *calc_pclk = (f_vco / p); 353 *m_result = m; 354 *n_result = n; 355 switch(p) 356 { 357 case 1: 358 p = 0x00; 359 break; 360 case 2: 361 p = 0x01; 362 break; 363 case 4: 364 p = 0x02; 365 break; 366 case 8: 367 p = 0x03; 368 break; 369 case 16: 370 p = 0x04; 371 break; 372 } 373 *p_result = p; 374 375 /* display the found pixelclock values */ 376 LOG(2,("DAC: pix PLL check: requested %fMHz got %fMHz, mnp 0x%02x 0x%02x 0x%02x\n", 377 req_pclk, *calc_pclk, *m_result, *n_result, *p_result)); 378 379 return B_OK; 380 } 381 382 /* find nearest valid system PLL setting */ 383 static status_t g100_g400max_dac_sys_pll_find( 384 float req_sclk,float * calc_sclk,uint8 * m_result,uint8 * n_result,uint8 * p_result) 385 { 386 int m = 0, n = 0, p = 0, m_max; 387 float error, error_best = 999999999; 388 int best[3]; 389 float f_vco; 390 391 /* determine the max. reference-frequency postscaler setting for the 392 * current card (see G100, G200 and G400 specs). */ 393 switch(si->ps.card_type) 394 { 395 /* case G100: 396 LOG(4,("DAC: G100 restrictions apply\n")); 397 m_max = 7; 398 break; 399 case G200: 400 LOG(4,("DAC: G200 restrictions apply\n")); 401 m_max = 7; 402 break; 403 */ default: 404 LOG(4,("DAC: G400/G400MAX restrictions apply\n")); 405 m_max = 32; 406 break; 407 } 408 409 /* Make sure the requested systemclock is within the PLL's operational limits */ 410 /* lower limit is min_system_vco divided by highest postscaler-factor */ 411 if (req_sclk < (si->ps.min_system_vco / 8.0)) 412 { 413 LOG(4,("DAC: clamping sysclock: requested %fMHz, set to %fMHz\n", 414 req_sclk, (float)(si->ps.min_system_vco / 8.0))); 415 req_sclk = (si->ps.min_system_vco / 8.0); 416 } 417 /* upper limit is max_system_vco */ 418 if (req_sclk > si->ps.max_system_vco) 419 { 420 LOG(4,("DAC: clamping sysclock: requested %fMHz, set to %fMHz\n", 421 req_sclk, (float)si->ps.max_system_vco)); 422 req_sclk = si->ps.max_system_vco; 423 } 424 425 /* iterate through all valid PLL postscaler settings */ 426 for (p=0x01; p < 0x10; p = p<<1) 427 { 428 /* calculate the needed VCO frequency for this postscaler setting */ 429 f_vco = req_sclk * p; 430 431 /* check if this is within range of the VCO specs */ 432 if ((f_vco >= si->ps.min_system_vco) && (f_vco <= si->ps.max_system_vco)) 433 { 434 /* iterate trough all valid reference-frequency postscaler settings */ 435 for (m = 2; m <= m_max; m++) 436 { 437 /* calculate VCO postscaler setting for current setup.. */ 438 n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5); 439 /* ..and check for validity */ 440 if ((n < 8) || (n > 128)) continue; 441 442 /* find error in frequency this setting gives */ 443 error = fabs(req_sclk - (((si->ps.f_ref / m) * n) / p)); 444 445 /* note the setting if best yet */ 446 if (error < error_best) 447 { 448 error_best = error; 449 best[0]=m; 450 best[1]=n; 451 best[2]=p; 452 } 453 } 454 } 455 } 456 457 /* setup the scalers programming values for found optimum setting */ 458 m=best[0] - 1; 459 n=best[1] - 1; 460 p=best[2] - 1; 461 462 /* calc the needed PLL loopbackfilter setting belonging to current VCO speed, 463 * for the current card (see G100, G200 and G400 specs). */ 464 f_vco = (si->ps.f_ref / (m + 1)) * (n + 1); 465 LOG(2,("DAC: sys VCO frequency found %fMhz\n", f_vco)); 466 467 switch(si->ps.card_type) 468 { 469 default: 470 for(;;) 471 { 472 if (f_vco >= 240) {p |= (0x03 << 3); break;}; 473 if (f_vco >= 170) {p |= (0x02 << 3); break;}; 474 if (f_vco >= 110) {p |= (0x01 << 3); break;}; 475 break; 476 } 477 break; 478 } 479 480 /* return the results */ 481 *calc_sclk = f_vco / ((p & 0x07) + 1); 482 *m_result = m; 483 *n_result = n; 484 *p_result = p; 485 486 /* display the found pixelclock values */ 487 LOG(2,("DAC: sys PLL check: requested %fMHz got %fMHz, mnp 0x%02x 0x%02x 0x%02x\n", 488 req_sclk, *calc_sclk, *m_result, *n_result, *p_result)); 489 490 return B_OK; 491 } 492 493 /*set up system pll - NB mclk is memory clock */ 494 status_t g400_dac_set_sys_pll() 495 { 496 /* values for DAC sys pll registers */ 497 uint8 m, n, p; 498 // uint time = 0; 499 float calc_sclk; 500 501 LOG(1,("DAC: Setting up G400/G400MAX system clock\n")); 502 g100_g400max_dac_sys_pll_find((float)si->ps.std_engine_clock, &calc_sclk, &m, &n, &p); 503 504 /* reprogram the clock - set PCI/AGP, program, set to programmed */ 505 /* clear, so don't o/clock addons */ 506 // CFGW(OPTION2, 0); 507 /* disable the SYSPLL */ 508 // CFGW(OPTION, CFGR(OPTION) | 0x04); 509 /* select the PCI/AGP clock */ 510 // CFGW(OPTION3, 0); 511 /* enable the SYSPLL */ 512 // CFGW(OPTION, CFGR(OPTION) & 0xfffffffb); 513 514 /* program the new clock */ 515 // DXIW(SYSPLLM, m); 516 // DXIW(SYSPLLN, n); 517 // DXIW(SYSPLLP, p); 518 519 /* Wait for the SYSPLL frequency to lock until timeout occurs */ 520 /* while((!(DXIR(SYSPLLSTAT)&0x40)) & (time <= 2000)) 521 { 522 time++; 523 snooze(1); 524 } 525 526 if (time > 2000) 527 LOG(2,("DAC: sys PLL frequency not locked!\n")); 528 else 529 LOG(2,("DAC: sys PLL frequency locked\n")); 530 */ 531 /* disable the SYSPLL */ 532 // CFGW(OPTION, CFGR(OPTION) | 0x04); 533 /* setup Gclk, Mclk and Wclk divs via PINS and select SYSPLL as system clock source */ 534 // CFGW(OPTION3, si->ps.option3_reg); 535 /* make sure the PLLs are not swapped (set default config) */ 536 // CFGW(OPTION, CFGR(OPTION) & 0xffffffbf); 537 /* enable the SYSPLL (and make sure the SYSPLL is indeed powered up) */ 538 // CFGW(OPTION, (CFGR(OPTION) & 0xfffffffb) | 0x20); 539 540 return B_OK; 541 } 542