1 /* second CTRC functionality for GeForce cards */ 2 /* Author: 3 Rudolf Cornelissen 11/2002-6/2009 4 */ 5 6 #define MODULE_BIT 0x00020000 7 8 #include "nv_std.h" 9 10 /* 11 Enable/Disable interrupts. Just a wrapper around the 12 ioctl() to the kernel driver. 13 */ 14 status_t nv_crtc2_interrupt_enable(bool flag) 15 { 16 status_t result = B_OK; 17 nv_set_vblank_int svi; 18 19 if (si->ps.int_assigned) 20 { 21 /* set the magic number so the driver knows we're for real */ 22 svi.magic = NV_PRIVATE_DATA_MAGIC; 23 svi.crtc = 1; 24 svi.do_it = flag; 25 /* contact driver and get a pointer to the registers and shared data */ 26 result = ioctl(fd, NV_RUN_INTERRUPTS, &svi, sizeof(svi)); 27 } 28 29 return result; 30 } 31 32 /* doing general fail-safe default setup here */ 33 //fixme: this is a _very_ basic setup, and it's preliminary... 34 status_t nv_crtc2_update_fifo() 35 { 36 uint8 bytes_per_pixel = 1; 37 uint32 drain; 38 39 /* we are only using this on >>coldstarted<< cards which really need this */ 40 //fixme: re-enable or remove after general user confirmation of behaviour... 41 if (/*(si->settings.usebios) ||*/ (si->ps.card_type != NV11)) return B_OK; 42 43 /* enable access to secondary head */ 44 set_crtc_owner(1); 45 46 /* set CRTC FIFO low watermark according to memory drain */ 47 switch(si->dm.space) 48 { 49 case B_CMAP8: 50 bytes_per_pixel = 1; 51 break; 52 case B_RGB15_LITTLE: 53 case B_RGB16_LITTLE: 54 bytes_per_pixel = 2; 55 break; 56 case B_RGB24_LITTLE: 57 bytes_per_pixel = 3; 58 break; 59 case B_RGB32_LITTLE: 60 bytes_per_pixel = 4; 61 break; 62 } 63 /* fixme: 64 * - I should probably include the refreshrate as well; 65 * - and the memory clocking speed, core clocking speed, RAM buswidth.. */ 66 drain = si->dm.timing.h_display * si->dm.timing.v_display * bytes_per_pixel; 67 68 /* Doesn't work for other than 32bit space (yet?) */ 69 if (si->dm.space != B_RGB32_LITTLE) 70 { 71 /* BIOS defaults */ 72 CRTC2W(FIFO, 0x03); 73 CRTC2W(FIFO_LWM, 0x20); 74 LOG(4,("CRTC2: FIFO low-watermark set to $20, burst size 256 (BIOS defaults)\n")); 75 return B_OK; 76 } 77 78 if (drain > (((uint32)1280) * 1024 * 4)) 79 { 80 /* set CRTC FIFO burst size for 'smaller' bursts */ 81 CRTC2W(FIFO, 0x01); 82 /* Instruct CRTC to fetch new data 'earlier' */ 83 CRTC2W(FIFO_LWM, 0x40); 84 LOG(4,("CRTC2: FIFO low-watermark set to $40, burst size 64\n")); 85 } 86 else 87 { 88 if (drain > (((uint32)1024) * 768 * 4)) 89 { 90 /* BIOS default */ 91 CRTC2W(FIFO, 0x02); 92 /* Instruct CRTC to fetch new data 'earlier' */ 93 CRTC2W(FIFO_LWM, 0x40); 94 LOG(4,("CRTC2: FIFO low-watermark set to $40, burst size 128\n")); 95 } 96 else 97 { 98 /* BIOS defaults */ 99 CRTC2W(FIFO, 0x03); 100 CRTC2W(FIFO_LWM, 0x20); 101 LOG(4,("CRTC2: FIFO low-watermark set to $20, burst size 256 (BIOS defaults)\n")); 102 } 103 } 104 105 return B_OK; 106 } 107 108 /* Adjust passed parameters to a valid mode line */ 109 status_t nv_crtc2_validate_timing( 110 uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht, 111 uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt 112 ) 113 { 114 /* horizontal */ 115 /* make all parameters multiples of 8 */ 116 *hd_e &= 0xfff8; 117 *hs_s &= 0xfff8; 118 *hs_e &= 0xfff8; 119 *ht &= 0xfff8; 120 121 /* confine to required number of bits, taking logic into account */ 122 if (*hd_e > ((0x01ff - 2) << 3)) *hd_e = ((0x01ff - 2) << 3); 123 if (*hs_s > ((0x01ff - 1) << 3)) *hs_s = ((0x01ff - 1) << 3); 124 if (*hs_e > ( 0x01ff << 3)) *hs_e = ( 0x01ff << 3); 125 if (*ht > ((0x01ff + 5) << 3)) *ht = ((0x01ff + 5) << 3); 126 127 /* NOTE: keep horizontal timing at multiples of 8! */ 128 /* confine to a reasonable width */ 129 if (*hd_e < 640) *hd_e = 640; 130 if (*hd_e > 2048) *hd_e = 2048; 131 132 /* if hor. total does not leave room for a sensible sync pulse, increase it! */ 133 if (*ht < (*hd_e + 80)) *ht = (*hd_e + 80); 134 135 /* if hor. total does not adhere to max. blanking pulse width, decrease it! */ 136 if (*ht > (*hd_e + 0x3f8)) *ht = (*hd_e + 0x3f8); 137 138 /* make sure sync pulse is not during display */ 139 if (*hs_e > (*ht - 8)) *hs_e = (*ht - 8); 140 if (*hs_s < (*hd_e + 8)) *hs_s = (*hd_e + 8); 141 142 /* correct sync pulse if it is too long: 143 * there are only 5 bits available to save this in the card registers! */ 144 if (*hs_e > (*hs_s + 0xf8)) *hs_e = (*hs_s + 0xf8); 145 146 /*vertical*/ 147 /* confine to required number of bits, taking logic into account */ 148 //fixme if needed: on GeForce cards there are 12 instead of 11 bits... 149 if (*vd_e > (0x7ff - 2)) *vd_e = (0x7ff - 2); 150 if (*vs_s > (0x7ff - 1)) *vs_s = (0x7ff - 1); 151 if (*vs_e > 0x7ff ) *vs_e = 0x7ff ; 152 if (*vt > (0x7ff + 2)) *vt = (0x7ff + 2); 153 154 /* confine to a reasonable height */ 155 if (*vd_e < 480) *vd_e = 480; 156 if (*vd_e > 1536) *vd_e = 1536; 157 158 /*if vertical total does not leave room for a sync pulse, increase it!*/ 159 if (*vt < (*vd_e + 3)) *vt = (*vd_e + 3); 160 161 /* if vert. total does not adhere to max. blanking pulse width, decrease it! */ 162 if (*vt > (*vd_e + 0xff)) *vt = (*vd_e + 0xff); 163 164 /* make sure sync pulse is not during display */ 165 if (*vs_e > (*vt - 1)) *vs_e = (*vt - 1); 166 if (*vs_s < (*vd_e + 1)) *vs_s = (*vd_e + 1); 167 168 /* correct sync pulse if it is too long: 169 * there are only 4 bits available to save this in the card registers! */ 170 if (*vs_e > (*vs_s + 0x0f)) *vs_e = (*vs_s + 0x0f); 171 172 return B_OK; 173 } 174 175 /*set a mode line - inputs are in pixels*/ 176 status_t nv_crtc2_set_timing(display_mode target) 177 { 178 uint8 temp; 179 180 uint32 htotal; /*total horizontal total VCLKs*/ 181 uint32 hdisp_e; /*end of horizontal display (begins at 0)*/ 182 uint32 hsync_s; /*begin of horizontal sync pulse*/ 183 uint32 hsync_e; /*end of horizontal sync pulse*/ 184 uint32 hblnk_s; /*begin horizontal blanking*/ 185 uint32 hblnk_e; /*end horizontal blanking*/ 186 187 uint32 vtotal; /*total vertical total scanlines*/ 188 uint32 vdisp_e; /*end of vertical display*/ 189 uint32 vsync_s; /*begin of vertical sync pulse*/ 190 uint32 vsync_e; /*end of vertical sync pulse*/ 191 uint32 vblnk_s; /*begin vertical blanking*/ 192 uint32 vblnk_e; /*end vertical blanking*/ 193 194 uint32 linecomp; /*split screen and vdisp_e interrupt*/ 195 196 LOG(4,("CRTC2: setting timing\n")); 197 198 /* setup tuned internal modeline for flatpanel if connected and active */ 199 /* notes: 200 * - the CRTC modeline must end earlier than the panel modeline to keep correct 201 * sync going; 202 * - if the CRTC modeline ends too soon, pixelnoise will occur in 8 (or so) pixel 203 * wide horizontal stripes. This can be observed earliest on fullscreen overlay, 204 * and if it gets worse, also normal desktop output will suffer. The stripes 205 * are mainly visible at the left of the screen, over the entire screen height. */ 206 if (si->ps.monitors & CRTC2_TMDS) 207 { 208 LOG(2,("CRTC2: DFP active: tuning modeline\n")); 209 210 /* horizontal timing */ 211 target.timing.h_sync_start = 212 ((uint16)((si->ps.p2_timing.h_sync_start / ((float)si->ps.p2_timing.h_display)) * 213 target.timing.h_display)) & 0xfff8; 214 215 target.timing.h_sync_end = 216 ((uint16)((si->ps.p2_timing.h_sync_end / ((float)si->ps.p2_timing.h_display)) * 217 target.timing.h_display)) & 0xfff8; 218 219 target.timing.h_total = 220 (((uint16)((si->ps.p2_timing.h_total / ((float)si->ps.p2_timing.h_display)) * 221 target.timing.h_display)) & 0xfff8) - 8; 222 223 /* in native mode the CRTC needs some extra time to keep synced correctly; 224 * OTOH the overlay unit distorts if we reserve too much time! */ 225 if (target.timing.h_display == si->ps.p2_timing.h_display) 226 { 227 /* NV11 timing has different constraints than later cards */ 228 if (si->ps.card_type == NV11) 229 target.timing.h_total -= 56; 230 else 231 /* confirmed NV34 with 1680x1050 panel */ 232 target.timing.h_total -= 32; 233 } 234 235 if (target.timing.h_sync_start == target.timing.h_display) 236 target.timing.h_sync_start += 8; 237 if (target.timing.h_sync_end == target.timing.h_total) 238 target.timing.h_sync_end -= 8; 239 240 /* vertical timing */ 241 target.timing.v_sync_start = 242 ((uint16)((si->ps.p2_timing.v_sync_start / ((float)si->ps.p2_timing.v_display)) * 243 target.timing.v_display)); 244 245 target.timing.v_sync_end = 246 ((uint16)((si->ps.p2_timing.v_sync_end / ((float)si->ps.p2_timing.v_display)) * 247 target.timing.v_display)); 248 249 target.timing.v_total = 250 ((uint16)((si->ps.p2_timing.v_total / ((float)si->ps.p2_timing.v_display)) * 251 target.timing.v_display)) - 1; 252 253 if (target.timing.v_sync_start == target.timing.v_display) 254 target.timing.v_sync_start += 1; 255 if (target.timing.v_sync_end == target.timing.v_total) 256 target.timing.v_sync_end -= 1; 257 258 /* disable GPU scaling testmode so automatic scaling will be done */ 259 DAC2W(FP_DEBUG1, 0); 260 } 261 262 /* Modify parameters as required by standard VGA */ 263 htotal = ((target.timing.h_total >> 3) - 5); 264 hdisp_e = ((target.timing.h_display >> 3) - 1); 265 hblnk_s = hdisp_e; 266 hblnk_e = (htotal + 4); 267 hsync_s = (target.timing.h_sync_start >> 3); 268 hsync_e = (target.timing.h_sync_end >> 3); 269 270 vtotal = target.timing.v_total - 2; 271 vdisp_e = target.timing.v_display - 1; 272 vblnk_s = vdisp_e; 273 vblnk_e = (vtotal + 1); 274 vsync_s = target.timing.v_sync_start; 275 vsync_e = target.timing.v_sync_end; 276 277 /* prevent memory adress counter from being reset (linecomp may not occur) */ 278 linecomp = target.timing.v_display; 279 280 /* enable access to secondary head */ 281 set_crtc_owner(1); 282 283 /* Note for laptop and DVI flatpanels: 284 * CRTC timing has a seperate set of registers from flatpanel timing. 285 * The flatpanel timing registers have scaling registers that are used to match 286 * these two modelines. */ 287 { 288 LOG(4,("CRTC2: Setting full timing...\n")); 289 290 /* log the mode that will be set */ 291 LOG(2,("CRTC2:\n\tHTOT:%x\n\tHDISPEND:%x\n\tHBLNKS:%x\n\tHBLNKE:%x\n\tHSYNCS:%x\n\tHSYNCE:%x\n\t",htotal,hdisp_e,hblnk_s,hblnk_e,hsync_s,hsync_e)); 292 LOG(2,("VTOT:%x\n\tVDISPEND:%x\n\tVBLNKS:%x\n\tVBLNKE:%x\n\tVSYNCS:%x\n\tVSYNCE:%x\n",vtotal,vdisp_e,vblnk_s,vblnk_e,vsync_s,vsync_e)); 293 294 /* actually program the card! */ 295 /* unlock CRTC registers at index 0-7 */ 296 CRTC2W(VSYNCE, (CRTC2R(VSYNCE) & 0x7f)); 297 /* horizontal standard VGA regs */ 298 CRTC2W(HTOTAL, (htotal & 0xff)); 299 CRTC2W(HDISPE, (hdisp_e & 0xff)); 300 CRTC2W(HBLANKS, (hblnk_s & 0xff)); 301 /* also unlock vertical retrace registers in advance */ 302 CRTC2W(HBLANKE, ((hblnk_e & 0x1f) | 0x80)); 303 CRTC2W(HSYNCS, (hsync_s & 0xff)); 304 CRTC2W(HSYNCE, ((hsync_e & 0x1f) | ((hblnk_e & 0x20) << 2))); 305 306 /* vertical standard VGA regs */ 307 CRTC2W(VTOTAL, (vtotal & 0xff)); 308 CRTC2W(OVERFLOW, 309 ( 310 ((vtotal & 0x100) >> (8 - 0)) | ((vtotal & 0x200) >> (9 - 5)) | 311 ((vdisp_e & 0x100) >> (8 - 1)) | ((vdisp_e & 0x200) >> (9 - 6)) | 312 ((vsync_s & 0x100) >> (8 - 2)) | ((vsync_s & 0x200) >> (9 - 7)) | 313 ((vblnk_s & 0x100) >> (8 - 3)) | ((linecomp & 0x100) >> (8 - 4)) 314 )); 315 CRTC2W(PRROWSCN, 0x00); /* not used */ 316 CRTC2W(MAXSCLIN, (((vblnk_s & 0x200) >> (9 - 5)) | ((linecomp & 0x200) >> (9 - 6)))); 317 CRTC2W(VSYNCS, (vsync_s & 0xff)); 318 CRTC2W(VSYNCE, ((CRTC2R(VSYNCE) & 0xf0) | (vsync_e & 0x0f))); 319 CRTC2W(VDISPE, (vdisp_e & 0xff)); 320 CRTC2W(VBLANKS, (vblnk_s & 0xff)); 321 CRTC2W(VBLANKE, (vblnk_e & 0xff)); 322 CRTC2W(LINECOMP, (linecomp & 0xff)); 323 324 /* horizontal extended regs */ 325 //fixme: we reset bit4. is this correct?? 326 CRTC2W(HEB, (CRTC2R(HEB) & 0xe0) | 327 ( 328 ((htotal & 0x100) >> (8 - 0)) | 329 ((hdisp_e & 0x100) >> (8 - 1)) | 330 ((hblnk_s & 0x100) >> (8 - 2)) | 331 ((hsync_s & 0x100) >> (8 - 3)) 332 )); 333 334 /* (mostly) vertical extended regs */ 335 CRTC2W(LSR, 336 ( 337 ((vtotal & 0x400) >> (10 - 0)) | 338 ((vdisp_e & 0x400) >> (10 - 1)) | 339 ((vsync_s & 0x400) >> (10 - 2)) | 340 ((vblnk_s & 0x400) >> (10 - 3)) | 341 ((hblnk_e & 0x040) >> (6 - 4)) 342 //fixme: we still miss one linecomp bit!?! is this it?? 343 //| ((linecomp & 0x400) >> 3) 344 )); 345 346 /* more vertical extended regs */ 347 CRTC2W(EXTRA, 348 ( 349 ((vtotal & 0x800) >> (11 - 0)) | 350 ((vdisp_e & 0x800) >> (11 - 2)) | 351 ((vsync_s & 0x800) >> (11 - 4)) | 352 ((vblnk_s & 0x800) >> (11 - 6)) 353 //fixme: do we miss another linecomp bit!?! 354 )); 355 356 /* setup 'large screen' mode */ 357 if (target.timing.h_display >= 1280) 358 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xfb)); 359 else 360 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x04)); 361 362 /* setup HSYNC & VSYNC polarity */ 363 LOG(2,("CRTC2: sync polarity: ")); 364 temp = NV_REG8(NV8_MISCR); 365 if (target.timing.flags & B_POSITIVE_HSYNC) 366 { 367 LOG(2,("H:pos ")); 368 temp &= ~0x40; 369 } 370 else 371 { 372 LOG(2,("H:neg ")); 373 temp |= 0x40; 374 } 375 if (target.timing.flags & B_POSITIVE_VSYNC) 376 { 377 LOG(2,("V:pos ")); 378 temp &= ~0x80; 379 } 380 else 381 { 382 LOG(2,("V:neg ")); 383 temp |= 0x80; 384 } 385 NV_REG8(NV8_MISCW) = temp; 386 387 LOG(2,(", MISC reg readback: $%02x\n", NV_REG8(NV8_MISCR))); 388 } 389 390 /* always disable interlaced operation */ 391 /* (interlace is supported on upto and including NV10, NV15, and NV30 and up) */ 392 CRTC2W(INTERLACE, 0xff); 393 394 /* disable CRTC slaved mode unless a panel is in use */ 395 // fixme: this kills TVout when it was in use... 396 if (!(si->ps.monitors & CRTC2_TMDS)) CRTC2W(PIXEL, (CRTC2R(PIXEL) & 0x7f)); 397 398 /* setup flatpanel if connected and active */ 399 if (si->ps.monitors & CRTC2_TMDS) 400 { 401 uint32 iscale_x, iscale_y; 402 403 /* calculate inverse scaling factors used by hardware in 20.12 format */ 404 iscale_x = (((1 << 12) * target.timing.h_display) / si->ps.p2_timing.h_display); 405 iscale_y = (((1 << 12) * target.timing.v_display) / si->ps.p2_timing.v_display); 406 407 /* unblock flatpanel timing programming (or something like that..) */ 408 CRTC2W(FP_HTIMING, 0); 409 CRTC2W(FP_VTIMING, 0); 410 LOG(2,("CRTC2: FP_HTIMING reg readback: $%02x\n", CRTC2R(FP_HTIMING))); 411 LOG(2,("CRTC2: FP_VTIMING reg readback: $%02x\n", CRTC2R(FP_VTIMING))); 412 413 /* enable full width visibility on flatpanel */ 414 DAC2W(FP_HVALID_S, 0); 415 DAC2W(FP_HVALID_E, (si->ps.p2_timing.h_display - 1)); 416 /* enable full height visibility on flatpanel */ 417 DAC2W(FP_VVALID_S, 0); 418 DAC2W(FP_VVALID_E, (si->ps.p2_timing.v_display - 1)); 419 420 /* nVidia cards support upscaling except on ??? */ 421 /* NV11 cards can upscale after all! */ 422 if (0)//si->ps.card_type == NV11) 423 { 424 /* disable last fetched line limiting */ 425 DAC2W(FP_DEBUG2, 0x00000000); 426 /* inform panel to scale if needed */ 427 if ((iscale_x != (1 << 12)) || (iscale_y != (1 << 12))) 428 { 429 LOG(2,("CRTC2: DFP needs to do scaling\n")); 430 DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) | 0x00000100)); 431 } 432 else 433 { 434 LOG(2,("CRTC2: no scaling for DFP needed\n")); 435 DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) & 0xfffffeff)); 436 } 437 } 438 else 439 { 440 float dm_aspect; 441 442 LOG(2,("CRTC2: GPU scales for DFP if needed\n")); 443 444 /* calculate display mode aspect */ 445 dm_aspect = (target.timing.h_display / ((float)target.timing.v_display)); 446 447 /* limit last fetched line if vertical scaling is done */ 448 if (iscale_y != (1 << 12)) 449 DAC2W(FP_DEBUG2, ((1 << 28) | ((target.timing.v_display - 1) << 16))); 450 else 451 DAC2W(FP_DEBUG2, 0x00000000); 452 453 /* inform panel not to scale */ 454 DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) & 0xfffffeff)); 455 456 /* GPU scaling is automatically setup by hardware, so only modify this 457 * scalingfactor for non 4:3 (1.33) aspect panels; 458 * let's consider 1280x1024 1:33 aspect (it's 1.25 aspect actually!) */ 459 460 /* correct for widescreen panels relative to mode... 461 * (so if panel is more widescreen than mode being set) */ 462 /* BTW: known widescreen panels: 463 * 1280 x 800 (1.60), 464 * 1440 x 900 (1.60), 465 * 1680 x 1050 (1.60), 466 * 1920 x 1200 (1.60). */ 467 /* known 4:3 aspect non-standard resolution panels: 468 * 1400 x 1050 (1.33). */ 469 /* NOTE: 470 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */ 471 if ((iscale_x != (1 << 12)) && (si->ps.crtc2_screen.aspect > (dm_aspect + 0.10))) 472 { 473 uint16 diff; 474 475 LOG(2,("CRTC2: (relative) widescreen panel: tuning horizontal scaling\n")); 476 477 /* X-scaling should be the same as Y-scaling */ 478 iscale_x = iscale_y; 479 /* enable testmode (b12) and program new X-scaling factor */ 480 DAC2W(FP_DEBUG1, (((iscale_x >> 1) & 0x00000fff) | (1 << 12))); 481 /* center/cut-off left and right side of screen */ 482 diff = ((si->ps.p2_timing.h_display - 483 ((target.timing.h_display * (1 << 12)) / iscale_x)) 484 / 2); 485 DAC2W(FP_HVALID_S, diff); 486 DAC2W(FP_HVALID_E, ((si->ps.p2_timing.h_display - diff) - 1)); 487 } 488 /* correct for portrait panels... */ 489 /* NOTE: 490 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */ 491 if ((iscale_y != (1 << 12)) && (si->ps.crtc2_screen.aspect < (dm_aspect - 0.10))) 492 { 493 LOG(2,("CRTC2: (relative) portrait panel: should tune vertical scaling\n")); 494 /* fixme: implement if this kind of portrait panels exist on nVidia... */ 495 } 496 } 497 498 /* do some logging.. */ 499 LOG(2,("CRTC2: FP_HVALID_S reg readback: $%08x\n", DAC2R(FP_HVALID_S))); 500 LOG(2,("CRTC2: FP_HVALID_E reg readback: $%08x\n", DAC2R(FP_HVALID_E))); 501 LOG(2,("CRTC2: FP_VVALID_S reg readback: $%08x\n", DAC2R(FP_VVALID_S))); 502 LOG(2,("CRTC2: FP_VVALID_E reg readback: $%08x\n", DAC2R(FP_VVALID_E))); 503 LOG(2,("CRTC2: FP_DEBUG0 reg readback: $%08x\n", DAC2R(FP_DEBUG0))); 504 LOG(2,("CRTC2: FP_DEBUG1 reg readback: $%08x\n", DAC2R(FP_DEBUG1))); 505 LOG(2,("CRTC2: FP_DEBUG2 reg readback: $%08x\n", DAC2R(FP_DEBUG2))); 506 LOG(2,("CRTC2: FP_DEBUG3 reg readback: $%08x\n", DAC2R(FP_DEBUG3))); 507 LOG(2,("CRTC2: FP_TG_CTRL reg readback: $%08x\n", DAC2R(FP_TG_CTRL))); 508 } 509 510 return B_OK; 511 } 512 513 status_t nv_crtc2_depth(int mode) 514 { 515 uint8 viddelay = 0; 516 uint32 genctrl = 0; 517 518 /* set VCLK scaling */ 519 switch(mode) 520 { 521 case BPP8: 522 viddelay = 0x01; 523 /* genctrl b4 & b5 reset: 'direct mode' */ 524 genctrl = 0x00101100; 525 break; 526 case BPP15: 527 viddelay = 0x02; 528 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 529 genctrl = 0x00100130; 530 break; 531 case BPP16: 532 viddelay = 0x02; 533 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 534 genctrl = 0x00101130; 535 break; 536 case BPP24: 537 viddelay = 0x03; 538 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 539 genctrl = 0x00100130; 540 break; 541 case BPP32: 542 viddelay = 0x03; 543 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 544 genctrl = 0x00101130; 545 break; 546 } 547 /* enable access to secondary head */ 548 set_crtc_owner(1); 549 550 CRTC2W(PIXEL, ((CRTC2R(PIXEL) & 0xfc) | viddelay)); 551 DAC2W(GENCTRL, genctrl); 552 553 return B_OK; 554 } 555 556 status_t nv_crtc2_dpms(bool display, bool h, bool v, bool do_panel) 557 { 558 uint8 temp; 559 char msg[100]; 560 561 sprintf(msg, "CRTC2: setting DPMS: "); 562 563 /* enable access to secondary head */ 564 set_crtc_owner(1); 565 566 /* start synchronous reset: required before turning screen off! */ 567 SEQW(RESET, 0x01); 568 569 temp = SEQR(CLKMODE); 570 if (display) 571 { 572 /* turn screen on */ 573 SEQW(CLKMODE, (temp & ~0x20)); 574 575 /* end synchronous reset because display should be enabled */ 576 SEQW(RESET, 0x03); 577 578 if (do_panel && (si->ps.monitors & CRTC2_TMDS)) 579 { 580 if (!si->ps.laptop) 581 { 582 /* restore original panelsync and panel-enable */ 583 uint32 panelsync = 0x00000000; 584 if(si->ps.p2_timing.flags & B_POSITIVE_VSYNC) panelsync |= 0x00000001; 585 if(si->ps.p2_timing.flags & B_POSITIVE_HSYNC) panelsync |= 0x00000010; 586 /* display enable polarity (not an official flag) */ 587 if(si->ps.p2_timing.flags & B_BLANK_PEDESTAL) panelsync |= 0x10000000; 588 DAC2W(FP_TG_CTRL, ((DAC2R(FP_TG_CTRL) & 0xcfffffcc) | panelsync)); 589 590 //fixme?: looks like we don't need this after all: 591 /* powerup both LVDS (laptop panellink) and TMDS (DVI panellink) 592 * internal transmitters... */ 593 /* note: 594 * the powerbits in this register are hardwired to the DVI connectors, 595 * instead of to the DACs! (confirmed NV34) */ 596 //fixme... 597 //DAC2W(FP_DEBUG0, (DAC2R(FP_DEBUG0) & 0xcfffffff)); 598 /* ... and powerup external TMDS transmitter if it exists */ 599 /* (confirmed OK on NV28 and NV34) */ 600 //CRTC2W(0x59, (CRTC2R(0x59) | 0x01)); 601 602 sprintf(msg, "%s(panel-)", msg); 603 } 604 else 605 { 606 //fixme: see if LVDS head can be determined with two panels there... 607 if (!(si->ps.monitors & CRTC1_TMDS) && (si->ps.card_type != NV11)) 608 { 609 /* b2 = 0 = enable laptop panel backlight */ 610 /* note: this seems to be a write-only register. */ 611 NV_REG32(NV32_LVDS_PWR) = 0x00000003; 612 613 sprintf(msg, "%s(panel-)", msg); 614 } 615 } 616 } 617 618 sprintf(msg, "%sdisplay on, ", msg); 619 } 620 else 621 { 622 /* turn screen off */ 623 SEQW(CLKMODE, (temp | 0x20)); 624 625 if (do_panel && (si->ps.monitors & CRTC2_TMDS)) 626 { 627 if (!si->ps.laptop) 628 { 629 /* shutoff panelsync and disable panel */ 630 DAC2W(FP_TG_CTRL, ((DAC2R(FP_TG_CTRL) & 0xcfffffcc) | 0x20000022)); 631 632 //fixme?: looks like we don't need this after all: 633 /* powerdown both LVDS (laptop panellink) and TMDS (DVI panellink) 634 * internal transmitters... */ 635 /* note: 636 * the powerbits in this register are hardwired to the DVI connectors, 637 * instead of to the DACs! (confirmed NV34) */ 638 //fixme... 639 //DAC2W(FP_DEBUG0, (DAC2R(FP_DEBUG0) | 0x30000000)); 640 /* ... and powerdown external TMDS transmitter if it exists */ 641 /* (confirmed OK on NV28 and NV34) */ 642 //CRTC2W(0x59, (CRTC2R(0x59) & 0xfe)); 643 644 sprintf(msg, "%s(panel-)", msg); 645 } 646 else 647 { 648 //fixme: see if LVDS head can be determined with two panels there... 649 if (!(si->ps.monitors & CRTC1_TMDS) && (si->ps.card_type != NV11)) 650 { 651 /* b2 = 1 = disable laptop panel backlight */ 652 /* note: this seems to be a write-only register. */ 653 NV_REG32(NV32_LVDS_PWR) = 0x00000007; 654 655 sprintf(msg, "%s(panel-)", msg); 656 } 657 } 658 } 659 660 sprintf(msg, "%sdisplay off, ", msg); 661 } 662 663 if (h) 664 { 665 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0x7f)); 666 sprintf(msg, "%shsync enabled, ", msg); 667 } 668 else 669 { 670 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x80)); 671 sprintf(msg, "%shsync disabled, ", msg); 672 } 673 if (v) 674 { 675 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xbf)); 676 sprintf(msg, "%svsync enabled\n", msg); 677 } 678 else 679 { 680 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x40)); 681 sprintf(msg, "%svsync disabled\n", msg); 682 } 683 684 LOG(4, (msg)); 685 686 return B_OK; 687 } 688 689 status_t nv_crtc2_set_display_pitch() 690 { 691 uint32 offset; 692 693 LOG(4,("CRTC2: setting card pitch (offset between lines)\n")); 694 695 /* figure out offset value hardware needs */ 696 offset = si->fbc.bytes_per_row / 8; 697 698 LOG(2,("CRTC2: offset register set to: $%04x\n", offset)); 699 700 /* enable access to secondary head */ 701 set_crtc_owner(1); 702 703 /* program the card */ 704 CRTC2W(PITCHL, (offset & 0x00ff)); 705 CRTC2W(REPAINT0, ((CRTC2R(REPAINT0) & 0x1f) | ((offset & 0x0700) >> 3))); 706 707 return B_OK; 708 } 709 710 status_t nv_crtc2_set_display_start(uint32 startadd,uint8 bpp) 711 { 712 uint32 timeout = 0; 713 714 LOG(4,("CRTC2: setting card RAM to be displayed bpp %d\n", bpp)); 715 716 LOG(2,("CRTC2: startadd: $%08x\n", startadd)); 717 LOG(2,("CRTC2: frameRAM: $%08x\n", si->framebuffer)); 718 LOG(2,("CRTC2: framebuffer: $%08x\n", si->fbc.frame_buffer)); 719 720 /* we might have no retraces during setmode! */ 721 /* wait 25mS max. for retrace to occur (refresh > 40Hz) */ 722 while (((NV_REG32(NV32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) && 723 (timeout < (25000/10))) 724 { 725 /* don't snooze much longer or retrace might get missed! */ 726 snooze(10); 727 timeout++; 728 } 729 730 /* enable access to secondary head */ 731 set_crtc_owner(1); 732 733 /* upto 4Gb RAM adressing: must be used on NV10 and later! */ 734 /* NOTE: 735 * While this register also exists on pre-NV10 cards, it will 736 * wrap-around at 16Mb boundaries!! */ 737 738 /* 30bit adress in 32bit words */ 739 NV_REG32(NV32_NV10FB2STADD32) = (startadd & 0xfffffffc); 740 741 /* set byte adress: (b0 - 1) */ 742 ATB2W(HORPIXPAN, ((startadd & 0x00000003) << 1)); 743 744 return B_OK; 745 } 746 747 status_t nv_crtc2_cursor_init() 748 { 749 int i; 750 vuint32 * fb; 751 /* cursor bitmap will be stored at the start of the framebuffer */ 752 const uint32 curadd = 0; 753 754 /* enable access to secondary head */ 755 set_crtc_owner(1); 756 757 /* set cursor bitmap adress ... */ 758 if (si->ps.laptop) 759 { 760 /* must be used this way on pre-NV10 and on all 'Go' cards! */ 761 762 /* cursorbitmap must start on 2Kbyte boundary: */ 763 /* set adress bit11-16, and set 'no doublescan' (registerbit 1 = 0) */ 764 CRTC2W(CURCTL0, ((curadd & 0x0001f800) >> 9)); 765 /* set adress bit17-23, and set graphics mode cursor(?) (registerbit 7 = 1) */ 766 CRTC2W(CURCTL1, (((curadd & 0x00fe0000) >> 17) | 0x80)); 767 /* set adress bit24-31 */ 768 CRTC2W(CURCTL2, ((curadd & 0xff000000) >> 24)); 769 } 770 else 771 { 772 /* upto 4Gb RAM adressing: 773 * can be used on NV10 and later (except for 'Go' cards)! */ 774 /* NOTE: 775 * This register does not exist on pre-NV10 and 'Go' cards. */ 776 777 /* cursorbitmap must still start on 2Kbyte boundary: */ 778 NV_REG32(NV32_NV10CUR2ADD32) = (curadd & 0xfffff800); 779 } 780 781 /* set cursor colour: not needed because of direct nature of cursor bitmap. */ 782 783 /*clear cursor*/ 784 fb = (vuint32 *) si->framebuffer + curadd; 785 for (i=0;i<(2048/4);i++) 786 { 787 fb[i]=0; 788 } 789 790 /* select 32x32 pixel, 16bit color cursorbitmap, no doublescan */ 791 NV_REG32(NV32_2CURCONF) = 0x02000100; 792 793 /* activate hardware-sync between cursor updates and vertical retrace */ 794 DAC2W(NV10_CURSYNC, (DAC2R(NV10_CURSYNC) | 0x02000000)); 795 796 /* activate hardware cursor */ 797 nv_crtc2_cursor_show(); 798 799 return B_OK; 800 } 801 802 status_t nv_crtc2_cursor_show() 803 { 804 LOG(4,("CRTC2: enabling cursor\n")); 805 806 /* enable access to secondary head */ 807 set_crtc_owner(1); 808 809 /* b0 = 1 enables cursor */ 810 CRTC2W(CURCTL0, (CRTC2R(CURCTL0) | 0x01)); 811 812 /* workaround for hardware bug confirmed existing on NV43: 813 * Cursor visibility is not updated without a position update if its hardware 814 * retrace sync is enabled. */ 815 if (si->ps.card_arch == NV40A) DAC2W(CURPOS, (DAC2R(CURPOS))); 816 817 return B_OK; 818 } 819 820 status_t nv_crtc2_cursor_hide() 821 { 822 LOG(4,("CRTC2: disabling cursor\n")); 823 824 /* enable access to secondary head */ 825 set_crtc_owner(1); 826 827 /* b0 = 0 disables cursor */ 828 CRTC2W(CURCTL0, (CRTC2R(CURCTL0) & 0xfe)); 829 830 /* workaround for hardware bug confirmed existing on NV43: 831 * Cursor visibility is not updated without a position update if its hardware 832 * retrace sync is enabled. */ 833 if (si->ps.card_arch == NV40A) DAC2W(CURPOS, (DAC2R(CURPOS))); 834 835 return B_OK; 836 } 837 838 /*set up cursor shape*/ 839 status_t nv_crtc2_cursor_define(uint8* andMask,uint8* xorMask) 840 { 841 int x, y; 842 uint8 b; 843 vuint16 *cursor; 844 uint16 pixel; 845 846 /* get a pointer to the cursor */ 847 cursor = (vuint16*) si->framebuffer; 848 849 /* draw the cursor */ 850 /* (Nvidia cards have a RGB15 direct color cursor bitmap, bit #16 is transparancy) */ 851 for (y = 0; y < 16; y++) 852 { 853 b = 0x80; 854 for (x = 0; x < 8; x++) 855 { 856 /* preset transparant */ 857 pixel = 0x0000; 858 /* set white if requested */ 859 if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; 860 /* set black if requested */ 861 if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; 862 /* set invert if requested */ 863 if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; 864 /* place the pixel in the bitmap */ 865 cursor[x + (y * 32)] = pixel; 866 b >>= 1; 867 } 868 xorMask++; 869 andMask++; 870 b = 0x80; 871 for (; x < 16; x++) 872 { 873 /* preset transparant */ 874 pixel = 0x0000; 875 /* set white if requested */ 876 if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; 877 /* set black if requested */ 878 if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; 879 /* set invert if requested */ 880 if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; 881 /* place the pixel in the bitmap */ 882 cursor[x + (y * 32)] = pixel; 883 b >>= 1; 884 } 885 xorMask++; 886 andMask++; 887 } 888 889 return B_OK; 890 } 891 892 /* position the cursor */ 893 status_t nv_crtc2_cursor_position(uint16 x, uint16 y) 894 { 895 /* the cursor position is updated during retrace by card hardware */ 896 897 /* update cursorposition */ 898 DAC2W(CURPOS, ((x & 0x0fff) | ((y & 0x0fff) << 16))); 899 900 return B_OK; 901 } 902 903 status_t nv_crtc2_stop_tvout(void) 904 { 905 uint16 cnt; 906 907 LOG(4,("CRTC2: stopping TV output\n")); 908 909 /* enable access to secondary head */ 910 set_crtc_owner(1); 911 912 /* just to be sure Vsync is _really_ enabled */ 913 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xbf)); 914 915 /* wait for one image to be generated to make sure VGA has kicked in and is 916 * running OK before continuing... 917 * (Kicking in will fail often if we do not wait here) */ 918 /* Note: 919 * The used CRTC's Vsync is required to be enabled here. The DPMS state 920 * programming in the driver makes sure this is the case. 921 * (except for driver startup: see nv_general.c.) */ 922 923 /* make sure we are 'in' active VGA picture: wait with timeout! */ 924 cnt = 1; 925 while ((NV_REG8(NV8_INSTAT1) & 0x08) && cnt) 926 { 927 snooze(1); 928 cnt++; 929 } 930 /* wait for next vertical retrace start on VGA: wait with timeout! */ 931 cnt = 1; 932 while ((!(NV_REG8(NV8_INSTAT1) & 0x08)) && cnt) 933 { 934 snooze(1); 935 cnt++; 936 } 937 /* now wait until we are 'in' active VGA picture again: wait with timeout! */ 938 cnt = 1; 939 while ((NV_REG8(NV8_INSTAT1) & 0x08) && cnt) 940 { 941 snooze(1); 942 cnt++; 943 } 944 945 /* set CRTC to master mode (b7 = 0) if it wasn't slaved for a panel before */ 946 if (!(si->ps.slaved_tmds2)) CRTC2W(PIXEL, (CRTC2R(PIXEL) & 0x03)); 947 948 /* CAUTION: 949 * On old cards, PLLSEL (and TV_SETUP?) cannot be read (sometimes?), but 950 * write actions do succeed ... 951 * This is confirmed for both ISA and PCI access, on NV04 and NV11. */ 952 953 /* setup TVencoder connection */ 954 /* b1-0 = %00: encoder type is SLAVE; 955 * b24 = 1: VIP datapos is b0-7 */ 956 //fixme if needed: setup completely instead of relying on pre-init by BIOS.. 957 //(it seems to work OK on NV04 and NV11 although read reg. doesn't seem to work) 958 DAC2W(TV_SETUP, ((DAC2R(TV_SETUP) & ~0x00000003) | 0x01000000)); 959 960 /* tell GPU to use pixelclock from internal source instead of using TVencoder */ 961 DACW(PLLSEL, 0x30000f00); 962 963 /* HTOTAL, VTOTAL and OVERFLOW return their default CRTC use, instead of 964 * H, V-low and V-high 'shadow' counters(?)(b0, 4 and 6 = 0) (b7 use = unknown) */ 965 CRTC2W(TREG, 0x00); 966 967 /* select panel encoder, not TV encoder if needed (b0 = 1). 968 * Note: 969 * Both are devices (often) using the CRTC in slaved mode. */ 970 if (si->ps.slaved_tmds2) CRTC2W(LCD, (CRTC2R(LCD) | 0x01)); 971 972 return B_OK; 973 } 974 975 status_t nv_crtc2_start_tvout(void) 976 { 977 LOG(4,("CRTC2: starting TV output\n")); 978 979 /* switch TV encoder to CRTC2 */ 980 NV_REG32(NV32_FUNCSEL) &= ~0x00000100; 981 NV_REG32(NV32_2FUNCSEL) |= 0x00000100; 982 983 /* enable access to secondary head */ 984 set_crtc_owner(1); 985 986 /* CAUTION: 987 * On old cards, PLLSEL (and TV_SETUP?) cannot be read (sometimes?), but 988 * write actions do succeed ... 989 * This is confirmed for both ISA and PCI access, on NV04 and NV11. */ 990 991 /* setup TVencoder connection */ 992 /* b1-0 = %01: encoder type is MASTER; 993 * b24 = 1: VIP datapos is b0-7 */ 994 //fixme if needed: setup completely instead of relying on pre-init by BIOS.. 995 //(it seems to work OK on NV04 and NV11 although read reg. doesn't seem to work) 996 DAC2W(TV_SETUP, ((DAC2R(TV_SETUP) & ~0x00000002) | 0x01000001)); 997 998 /* tell GPU to use pixelclock from TVencoder instead of using internal source */ 999 /* (nessecary or display will 'shiver' on both TV and VGA.) */ 1000 DACW(PLLSEL, 0x100c0f00); 1001 1002 /* Set overscan color to 'black' */ 1003 /* note: 1004 * Change this instruction for a visible overscan color if you're trying to 1005 * center the output on TV. Use it as a guide-'line' then ;-) */ 1006 ATB2W(OSCANCOLOR, 0x00); 1007 1008 /* set CRTC to slaved mode (b7 = 1) and clear TVadjust (b3-5 = %000) */ 1009 CRTC2W(PIXEL, ((CRTC2R(PIXEL) & 0xc7) | 0x80)); 1010 /* select TV encoder, not panel encoder (b0 = 0). 1011 * Note: 1012 * Both are devices (often) using the CRTC in slaved mode. */ 1013 CRTC2W(LCD, (CRTC2R(LCD) & 0xfe)); 1014 1015 /* HTOTAL, VTOTAL and OVERFLOW return their default CRTC use, instead of 1016 * H, V-low and V-high 'shadow' counters(?)(b0, 4 and 6 = 0) (b7 use = unknown) */ 1017 CRTC2W(TREG, 0x80); 1018 1019 return B_OK; 1020 } 1021