1 /* second CTRC functionality for GeForce cards */ 2 /* Author: 3 Rudolf Cornelissen 11/2002-11/2005 4 */ 5 6 #define MODULE_BIT 0x00020000 7 8 #include "nv_std.h" 9 10 /* Adjust passed parameters to a valid mode line */ 11 status_t nv_crtc2_validate_timing( 12 uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht, 13 uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt 14 ) 15 { 16 /* horizontal */ 17 /* make all parameters multiples of 8 */ 18 *hd_e &= 0xfff8; 19 *hs_s &= 0xfff8; 20 *hs_e &= 0xfff8; 21 *ht &= 0xfff8; 22 23 /* confine to required number of bits, taking logic into account */ 24 if (*hd_e > ((0x01ff - 2) << 3)) *hd_e = ((0x01ff - 2) << 3); 25 if (*hs_s > ((0x01ff - 1) << 3)) *hs_s = ((0x01ff - 1) << 3); 26 if (*hs_e > ( 0x01ff << 3)) *hs_e = ( 0x01ff << 3); 27 if (*ht > ((0x01ff + 5) << 3)) *ht = ((0x01ff + 5) << 3); 28 29 /* NOTE: keep horizontal timing at multiples of 8! */ 30 /* confine to a reasonable width */ 31 if (*hd_e < 640) *hd_e = 640; 32 if (*hd_e > 2048) *hd_e = 2048; 33 34 /* if hor. total does not leave room for a sensible sync pulse, increase it! */ 35 if (*ht < (*hd_e + 80)) *ht = (*hd_e + 80); 36 37 /* if hor. total does not adhere to max. blanking pulse width, decrease it! */ 38 if (*ht > (*hd_e + 0x3f8)) *ht = (*hd_e + 0x3f8); 39 40 /* make sure sync pulse is not during display */ 41 if (*hs_e > (*ht - 8)) *hs_e = (*ht - 8); 42 if (*hs_s < (*hd_e + 8)) *hs_s = (*hd_e + 8); 43 44 /* correct sync pulse if it is too long: 45 * there are only 5 bits available to save this in the card registers! */ 46 if (*hs_e > (*hs_s + 0xf8)) *hs_e = (*hs_s + 0xf8); 47 48 /*vertical*/ 49 /* confine to required number of bits, taking logic into account */ 50 //fixme if needed: on GeForce cards there are 12 instead of 11 bits... 51 if (*vd_e > (0x7ff - 2)) *vd_e = (0x7ff - 2); 52 if (*vs_s > (0x7ff - 1)) *vs_s = (0x7ff - 1); 53 if (*vs_e > 0x7ff ) *vs_e = 0x7ff ; 54 if (*vt > (0x7ff + 2)) *vt = (0x7ff + 2); 55 56 /* confine to a reasonable height */ 57 if (*vd_e < 480) *vd_e = 480; 58 if (*vd_e > 1536) *vd_e = 1536; 59 60 /*if vertical total does not leave room for a sync pulse, increase it!*/ 61 if (*vt < (*vd_e + 3)) *vt = (*vd_e + 3); 62 63 /* if vert. total does not adhere to max. blanking pulse width, decrease it! */ 64 if (*vt > (*vd_e + 0xff)) *vt = (*vd_e + 0xff); 65 66 /* make sure sync pulse is not during display */ 67 if (*vs_e > (*vt - 1)) *vs_e = (*vt - 1); 68 if (*vs_s < (*vd_e + 1)) *vs_s = (*vd_e + 1); 69 70 /* correct sync pulse if it is too long: 71 * there are only 4 bits available to save this in the card registers! */ 72 if (*vs_e > (*vs_s + 0x0f)) *vs_e = (*vs_s + 0x0f); 73 74 return B_OK; 75 } 76 77 /*set a mode line - inputs are in pixels*/ 78 status_t nv_crtc2_set_timing(display_mode target) 79 { 80 uint8 temp; 81 82 uint32 htotal; /*total horizontal total VCLKs*/ 83 uint32 hdisp_e; /*end of horizontal display (begins at 0)*/ 84 uint32 hsync_s; /*begin of horizontal sync pulse*/ 85 uint32 hsync_e; /*end of horizontal sync pulse*/ 86 uint32 hblnk_s; /*begin horizontal blanking*/ 87 uint32 hblnk_e; /*end horizontal blanking*/ 88 89 uint32 vtotal; /*total vertical total scanlines*/ 90 uint32 vdisp_e; /*end of vertical display*/ 91 uint32 vsync_s; /*begin of vertical sync pulse*/ 92 uint32 vsync_e; /*end of vertical sync pulse*/ 93 uint32 vblnk_s; /*begin vertical blanking*/ 94 uint32 vblnk_e; /*end vertical blanking*/ 95 96 uint32 linecomp; /*split screen and vdisp_e interrupt*/ 97 98 LOG(4,("CRTC2: setting timing\n")); 99 100 /* setup tuned internal modeline for flatpanel if connected and active */ 101 /* notes: 102 * - the CRTC modeline must end earlier than the panel modeline to keep correct 103 * sync going; 104 * - if the CRTC modeline ends too soon, pixelnoise will occur in 8 (or so) pixel 105 * wide horizontal stripes. This can be observed earliest on fullscreen overlay, 106 * and if it gets worse, also normal desktop output will suffer. The stripes 107 * are mainly visible at the left of the screen, over the entire screen height. */ 108 if (si->ps.tmds2_active) 109 { 110 LOG(2,("CRTC2: DFP active: tuning modeline\n")); 111 112 /* horizontal timing */ 113 target.timing.h_sync_start = 114 ((uint16)((si->ps.p2_timing.h_sync_start / ((float)si->ps.p2_timing.h_display)) * 115 target.timing.h_display)) & 0xfff8; 116 117 target.timing.h_sync_end = 118 ((uint16)((si->ps.p2_timing.h_sync_end / ((float)si->ps.p2_timing.h_display)) * 119 target.timing.h_display)) & 0xfff8; 120 121 target.timing.h_total = 122 (((uint16)((si->ps.p2_timing.h_total / ((float)si->ps.p2_timing.h_display)) * 123 target.timing.h_display)) & 0xfff8) - 8; 124 125 /* in native mode the CRTC needs some extra time to keep synced correctly; 126 * OTOH the overlay unit distorts if we reserve too much time! */ 127 if (target.timing.h_display == si->ps.p2_timing.h_display) 128 { 129 /* NV11 timing has different constraints than later cards */ 130 if (si->ps.card_type == NV11) 131 target.timing.h_total -= 56; 132 else 133 /* confirmed NV34 with 1680x1050 panel */ 134 target.timing.h_total -= 32; 135 } 136 137 if (target.timing.h_sync_start == target.timing.h_display) 138 target.timing.h_sync_start += 8; 139 if (target.timing.h_sync_end == target.timing.h_total) 140 target.timing.h_sync_end -= 8; 141 142 /* vertical timing */ 143 target.timing.v_sync_start = 144 ((uint16)((si->ps.p2_timing.v_sync_start / ((float)si->ps.p2_timing.v_display)) * 145 target.timing.v_display)); 146 147 target.timing.v_sync_end = 148 ((uint16)((si->ps.p2_timing.v_sync_end / ((float)si->ps.p2_timing.v_display)) * 149 target.timing.v_display)); 150 151 target.timing.v_total = 152 ((uint16)((si->ps.p2_timing.v_total / ((float)si->ps.p2_timing.v_display)) * 153 target.timing.v_display)) - 1; 154 155 if (target.timing.v_sync_start == target.timing.v_display) 156 target.timing.v_sync_start += 1; 157 if (target.timing.v_sync_end == target.timing.v_total) 158 target.timing.v_sync_end -= 1; 159 160 /* disable GPU scaling testmode so automatic scaling will be done */ 161 DAC2W(FP_DEBUG1, 0); 162 } 163 164 /* Modify parameters as required by standard VGA */ 165 htotal = ((target.timing.h_total >> 3) - 5); 166 hdisp_e = ((target.timing.h_display >> 3) - 1); 167 hblnk_s = hdisp_e; 168 hblnk_e = (htotal + 4); 169 hsync_s = (target.timing.h_sync_start >> 3); 170 hsync_e = (target.timing.h_sync_end >> 3); 171 172 vtotal = target.timing.v_total - 2; 173 vdisp_e = target.timing.v_display - 1; 174 vblnk_s = vdisp_e; 175 vblnk_e = (vtotal + 1); 176 vsync_s = target.timing.v_sync_start; 177 vsync_e = target.timing.v_sync_end; 178 179 /* prevent memory adress counter from being reset (linecomp may not occur) */ 180 linecomp = target.timing.v_display; 181 182 /* enable access to secondary head */ 183 set_crtc_owner(1); 184 185 /* Note for laptop and DVI flatpanels: 186 * CRTC timing has a seperate set of registers from flatpanel timing. 187 * The flatpanel timing registers have scaling registers that are used to match 188 * these two modelines. */ 189 { 190 LOG(4,("CRTC2: Setting full timing...\n")); 191 192 /* log the mode that will be set */ 193 LOG(2,("CRTC2:\n\tHTOT:%x\n\tHDISPEND:%x\n\tHBLNKS:%x\n\tHBLNKE:%x\n\tHSYNCS:%x\n\tHSYNCE:%x\n\t",htotal,hdisp_e,hblnk_s,hblnk_e,hsync_s,hsync_e)); 194 LOG(2,("VTOT:%x\n\tVDISPEND:%x\n\tVBLNKS:%x\n\tVBLNKE:%x\n\tVSYNCS:%x\n\tVSYNCE:%x\n",vtotal,vdisp_e,vblnk_s,vblnk_e,vsync_s,vsync_e)); 195 196 /* actually program the card! */ 197 /* unlock CRTC registers at index 0-7 */ 198 CRTC2W(VSYNCE, (CRTC2R(VSYNCE) & 0x7f)); 199 /* horizontal standard VGA regs */ 200 CRTC2W(HTOTAL, (htotal & 0xff)); 201 CRTC2W(HDISPE, (hdisp_e & 0xff)); 202 CRTC2W(HBLANKS, (hblnk_s & 0xff)); 203 /* also unlock vertical retrace registers in advance */ 204 CRTC2W(HBLANKE, ((hblnk_e & 0x1f) | 0x80)); 205 CRTC2W(HSYNCS, (hsync_s & 0xff)); 206 CRTC2W(HSYNCE, ((hsync_e & 0x1f) | ((hblnk_e & 0x20) << 2))); 207 208 /* vertical standard VGA regs */ 209 CRTC2W(VTOTAL, (vtotal & 0xff)); 210 CRTC2W(OVERFLOW, 211 ( 212 ((vtotal & 0x100) >> (8 - 0)) | ((vtotal & 0x200) >> (9 - 5)) | 213 ((vdisp_e & 0x100) >> (8 - 1)) | ((vdisp_e & 0x200) >> (9 - 6)) | 214 ((vsync_s & 0x100) >> (8 - 2)) | ((vsync_s & 0x200) >> (9 - 7)) | 215 ((vblnk_s & 0x100) >> (8 - 3)) | ((linecomp & 0x100) >> (8 - 4)) 216 )); 217 CRTC2W(PRROWSCN, 0x00); /* not used */ 218 CRTC2W(MAXSCLIN, (((vblnk_s & 0x200) >> (9 - 5)) | ((linecomp & 0x200) >> (9 - 6)))); 219 CRTC2W(VSYNCS, (vsync_s & 0xff)); 220 CRTC2W(VSYNCE, ((CRTC2R(VSYNCE) & 0xf0) | (vsync_e & 0x0f))); 221 CRTC2W(VDISPE, (vdisp_e & 0xff)); 222 CRTC2W(VBLANKS, (vblnk_s & 0xff)); 223 CRTC2W(VBLANKE, (vblnk_e & 0xff)); 224 CRTC2W(LINECOMP, (linecomp & 0xff)); 225 226 /* horizontal extended regs */ 227 //fixme: we reset bit4. is this correct?? 228 CRTC2W(HEB, (CRTC2R(HEB) & 0xe0) | 229 ( 230 ((htotal & 0x100) >> (8 - 0)) | 231 ((hdisp_e & 0x100) >> (8 - 1)) | 232 ((hblnk_s & 0x100) >> (8 - 2)) | 233 ((hsync_s & 0x100) >> (8 - 3)) 234 )); 235 236 /* (mostly) vertical extended regs */ 237 CRTC2W(LSR, 238 ( 239 ((vtotal & 0x400) >> (10 - 0)) | 240 ((vdisp_e & 0x400) >> (10 - 1)) | 241 ((vsync_s & 0x400) >> (10 - 2)) | 242 ((vblnk_s & 0x400) >> (10 - 3)) | 243 ((hblnk_e & 0x040) >> (6 - 4)) 244 //fixme: we still miss one linecomp bit!?! is this it?? 245 //| ((linecomp & 0x400) >> 3) 246 )); 247 248 /* more vertical extended regs */ 249 CRTC2W(EXTRA, 250 ( 251 ((vtotal & 0x800) >> (11 - 0)) | 252 ((vdisp_e & 0x800) >> (11 - 2)) | 253 ((vsync_s & 0x800) >> (11 - 4)) | 254 ((vblnk_s & 0x800) >> (11 - 6)) 255 //fixme: do we miss another linecomp bit!?! 256 )); 257 258 /* setup 'large screen' mode */ 259 if (target.timing.h_display >= 1280) 260 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xfb)); 261 else 262 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x04)); 263 264 /* setup HSYNC & VSYNC polarity */ 265 LOG(2,("CRTC2: sync polarity: ")); 266 temp = NV_REG8(NV8_MISCR); 267 if (target.timing.flags & B_POSITIVE_HSYNC) 268 { 269 LOG(2,("H:pos ")); 270 temp &= ~0x40; 271 } 272 else 273 { 274 LOG(2,("H:neg ")); 275 temp |= 0x40; 276 } 277 if (target.timing.flags & B_POSITIVE_VSYNC) 278 { 279 LOG(2,("V:pos ")); 280 temp &= ~0x80; 281 } 282 else 283 { 284 LOG(2,("V:neg ")); 285 temp |= 0x80; 286 } 287 NV_REG8(NV8_MISCW) = temp; 288 289 LOG(2,(", MISC reg readback: $%02x\n", NV_REG8(NV8_MISCR))); 290 } 291 292 /* always disable interlaced operation */ 293 /* (interlace is supported on upto and including NV10, NV15, and NV30 and up) */ 294 CRTC2W(INTERLACE, 0xff); 295 296 /* disable CRTC slaved mode unless a panel is in use */ 297 // fixme: this kills TVout when it was in use... 298 if (!si->ps.tmds2_active) CRTC2W(PIXEL, (CRTC2R(PIXEL) & 0x7f)); 299 300 /* setup flatpanel if connected and active */ 301 if (si->ps.tmds2_active) 302 { 303 uint32 iscale_x, iscale_y; 304 305 /* calculate inverse scaling factors used by hardware in 20.12 format */ 306 iscale_x = (((1 << 12) * target.timing.h_display) / si->ps.p2_timing.h_display); 307 iscale_y = (((1 << 12) * target.timing.v_display) / si->ps.p2_timing.v_display); 308 309 /* unblock flatpanel timing programming (or something like that..) */ 310 CRTC2W(FP_HTIMING, 0); 311 CRTC2W(FP_VTIMING, 0); 312 LOG(2,("CRTC2: FP_HTIMING reg readback: $%02x\n", CRTC2R(FP_HTIMING))); 313 LOG(2,("CRTC2: FP_VTIMING reg readback: $%02x\n", CRTC2R(FP_VTIMING))); 314 315 /* enable full width visibility on flatpanel */ 316 DAC2W(FP_HVALID_S, 0); 317 DAC2W(FP_HVALID_E, (si->ps.p2_timing.h_display - 1)); 318 /* enable full height visibility on flatpanel */ 319 DAC2W(FP_VVALID_S, 0); 320 DAC2W(FP_VVALID_E, (si->ps.p2_timing.v_display - 1)); 321 322 /* nVidia cards support upscaling except on ??? */ 323 /* NV11 cards can upscale after all! */ 324 if (0)//si->ps.card_type == NV11) 325 { 326 /* disable last fetched line limiting */ 327 DAC2W(FP_DEBUG2, 0x00000000); 328 /* inform panel to scale if needed */ 329 if ((iscale_x != (1 << 12)) || (iscale_y != (1 << 12))) 330 { 331 LOG(2,("CRTC2: DFP needs to do scaling\n")); 332 DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) | 0x00000100)); 333 } 334 else 335 { 336 LOG(2,("CRTC2: no scaling for DFP needed\n")); 337 DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) & 0xfffffeff)); 338 } 339 } 340 else 341 { 342 float dm_aspect; 343 344 LOG(2,("CRTC2: GPU scales for DFP if needed\n")); 345 346 /* calculate display mode aspect */ 347 dm_aspect = (target.timing.h_display / ((float)target.timing.v_display)); 348 349 /* limit last fetched line if vertical scaling is done */ 350 if (iscale_y != (1 << 12)) 351 DAC2W(FP_DEBUG2, ((1 << 28) | ((target.timing.v_display - 1) << 16))); 352 else 353 DAC2W(FP_DEBUG2, 0x00000000); 354 355 /* inform panel not to scale */ 356 DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) & 0xfffffeff)); 357 358 /* GPU scaling is automatically setup by hardware, so only modify this 359 * scalingfactor for non 4:3 (1.33) aspect panels; 360 * let's consider 1280x1024 1:33 aspect (it's 1.25 aspect actually!) */ 361 362 /* correct for widescreen panels relative to mode... 363 * (so if panel is more widescreen than mode being set) */ 364 /* BTW: known widescreen panels: 365 * 1280 x 800 (1.60), 366 * 1440 x 900 (1.60), 367 * 1680 x 1050 (1.60), 368 * 1920 x 1200 (1.60). */ 369 /* known 4:3 aspect non-standard resolution panels: 370 * 1400 x 1050 (1.33). */ 371 /* NOTE: 372 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */ 373 if ((iscale_x != (1 << 12)) && (si->ps.panel2_aspect > (dm_aspect + 0.10))) 374 { 375 uint16 diff; 376 377 LOG(2,("CRTC2: (relative) widescreen panel: tuning horizontal scaling\n")); 378 379 /* X-scaling should be the same as Y-scaling */ 380 iscale_x = iscale_y; 381 /* enable testmode (b12) and program new X-scaling factor */ 382 DAC2W(FP_DEBUG1, (((iscale_x >> 1) & 0x00000fff) | (1 << 12))); 383 /* center/cut-off left and right side of screen */ 384 diff = ((si->ps.p2_timing.h_display - 385 ((target.timing.h_display * (1 << 12)) / iscale_x)) 386 / 2); 387 DAC2W(FP_HVALID_S, diff); 388 DAC2W(FP_HVALID_E, ((si->ps.p2_timing.h_display - diff) - 1)); 389 } 390 /* correct for portrait panels... */ 391 /* NOTE: 392 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */ 393 if ((iscale_y != (1 << 12)) && (si->ps.panel2_aspect < (dm_aspect - 0.10))) 394 { 395 LOG(2,("CRTC2: (relative) portrait panel: should tune vertical scaling\n")); 396 /* fixme: implement if this kind of portrait panels exist on nVidia... */ 397 } 398 } 399 400 /* do some logging.. */ 401 LOG(2,("CRTC2: FP_HVALID_S reg readback: $%08x\n", DAC2R(FP_HVALID_S))); 402 LOG(2,("CRTC2: FP_HVALID_E reg readback: $%08x\n", DAC2R(FP_HVALID_E))); 403 LOG(2,("CRTC2: FP_VVALID_S reg readback: $%08x\n", DAC2R(FP_VVALID_S))); 404 LOG(2,("CRTC2: FP_VVALID_E reg readback: $%08x\n", DAC2R(FP_VVALID_E))); 405 LOG(2,("CRTC2: FP_DEBUG0 reg readback: $%08x\n", DAC2R(FP_DEBUG0))); 406 LOG(2,("CRTC2: FP_DEBUG1 reg readback: $%08x\n", DAC2R(FP_DEBUG1))); 407 LOG(2,("CRTC2: FP_DEBUG2 reg readback: $%08x\n", DAC2R(FP_DEBUG2))); 408 LOG(2,("CRTC2: FP_DEBUG3 reg readback: $%08x\n", DAC2R(FP_DEBUG3))); 409 LOG(2,("CRTC2: FP_TG_CTRL reg readback: $%08x\n", DAC2R(FP_TG_CTRL))); 410 } 411 412 return B_OK; 413 } 414 415 status_t nv_crtc2_depth(int mode) 416 { 417 uint8 viddelay = 0; 418 uint32 genctrl = 0; 419 420 /* set VCLK scaling */ 421 switch(mode) 422 { 423 case BPP8: 424 viddelay = 0x01; 425 /* genctrl b4 & b5 reset: 'direct mode' */ 426 genctrl = 0x00101100; 427 break; 428 case BPP15: 429 viddelay = 0x02; 430 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 431 genctrl = 0x00100130; 432 break; 433 case BPP16: 434 viddelay = 0x02; 435 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 436 genctrl = 0x00101130; 437 break; 438 case BPP24: 439 viddelay = 0x03; 440 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 441 genctrl = 0x00100130; 442 break; 443 case BPP32: 444 viddelay = 0x03; 445 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 446 genctrl = 0x00101130; 447 break; 448 } 449 /* enable access to secondary head */ 450 set_crtc_owner(1); 451 452 CRTC2W(PIXEL, ((CRTC2R(PIXEL) & 0xfc) | viddelay)); 453 DAC2W(GENCTRL, genctrl); 454 455 return B_OK; 456 } 457 458 status_t nv_crtc2_dpms(bool display, bool h, bool v) 459 { 460 uint8 temp; 461 462 LOG(4,("CRTC2: setting DPMS: ")); 463 464 /* enable access to secondary head */ 465 set_crtc_owner(1); 466 467 /* start synchronous reset: required before turning screen off! */ 468 SEQW(RESET, 0x01); 469 470 temp = SEQR(CLKMODE); 471 if (display) 472 { 473 /* turn screen on */ 474 SEQW(CLKMODE, (temp & ~0x20)); 475 476 /* end synchronous reset because display should be enabled */ 477 SEQW(RESET, 0x03); 478 479 if (si->ps.tmds2_active && !si->ps.laptop) 480 { 481 /* restore original panelsync and panel-enable */ 482 uint32 panelsync = 0x00000000; 483 if(si->ps.p2_timing.flags & B_POSITIVE_VSYNC) panelsync |= 0x00000001; 484 if(si->ps.p2_timing.flags & B_POSITIVE_HSYNC) panelsync |= 0x00000010; 485 /* display enable polarity (not an official flag) */ 486 if(si->ps.p2_timing.flags & B_BLANK_PEDESTAL) panelsync |= 0x10000000; 487 DAC2W(FP_TG_CTRL, ((DAC2R(FP_TG_CTRL) & 0xcfffffcc) | panelsync)); 488 489 //fixme?: looks like we don't need this after all: 490 /* powerup both LVDS (laptop panellink) and TMDS (DVI panellink) 491 * internal transmitters... */ 492 /* note: 493 * the powerbits in this register are hardwired to the DVI connectors, 494 * instead of to the DACs! (confirmed NV34) */ 495 //fixme... 496 //DAC2W(FP_DEBUG0, (DAC2R(FP_DEBUG0) & 0xcfffffff)); 497 /* ... and powerup external TMDS transmitter if it exists */ 498 /* (confirmed OK on NV28 and NV34) */ 499 //CRTC2W(0x59, (CRTC2R(0x59) | 0x01)); 500 } 501 502 LOG(4,("display on, ")); 503 } 504 else 505 { 506 /* turn screen off */ 507 SEQW(CLKMODE, (temp | 0x20)); 508 509 if (si->ps.tmds2_active && !si->ps.laptop) 510 { 511 /* shutoff panelsync and disable panel */ 512 DAC2W(FP_TG_CTRL, ((DAC2R(FP_TG_CTRL) & 0xcfffffcc) | 0x20000022)); 513 514 //fixme?: looks like we don't need this after all: 515 /* powerdown both LVDS (laptop panellink) and TMDS (DVI panellink) 516 * internal transmitters... */ 517 /* note: 518 * the powerbits in this register are hardwired to the DVI connectors, 519 * instead of to the DACs! (confirmed NV34) */ 520 //fixme... 521 //DAC2W(FP_DEBUG0, (DAC2R(FP_DEBUG0) | 0x30000000)); 522 /* ... and powerdown external TMDS transmitter if it exists */ 523 /* (confirmed OK on NV28 and NV34) */ 524 //CRTC2W(0x59, (CRTC2R(0x59) & 0xfe)); 525 } 526 527 LOG(4,("display off, ")); 528 } 529 530 if (h) 531 { 532 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0x7f)); 533 LOG(4,("hsync enabled, ")); 534 } 535 else 536 { 537 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x80)); 538 LOG(4,("hsync disabled, ")); 539 } 540 if (v) 541 { 542 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xbf)); 543 LOG(4,("vsync enabled\n")); 544 } 545 else 546 { 547 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x40)); 548 LOG(4,("vsync disabled\n")); 549 } 550 551 return B_OK; 552 } 553 554 status_t nv_crtc2_set_display_pitch() 555 { 556 uint32 offset; 557 558 LOG(4,("CRTC2: setting card pitch (offset between lines)\n")); 559 560 /* figure out offset value hardware needs */ 561 offset = si->fbc.bytes_per_row / 8; 562 563 LOG(2,("CRTC2: offset register set to: $%04x\n", offset)); 564 565 /* enable access to secondary head */ 566 set_crtc_owner(1); 567 568 /* program the card */ 569 CRTC2W(PITCHL, (offset & 0x00ff)); 570 CRTC2W(REPAINT0, ((CRTC2R(REPAINT0) & 0x1f) | ((offset & 0x0700) >> 3))); 571 572 return B_OK; 573 } 574 575 status_t nv_crtc2_set_display_start(uint32 startadd,uint8 bpp) 576 { 577 uint32 timeout = 0; 578 579 LOG(4,("CRTC2: setting card RAM to be displayed bpp %d\n", bpp)); 580 581 LOG(2,("CRTC2: startadd: $%08x\n", startadd)); 582 LOG(2,("CRTC2: frameRAM: $%08x\n", si->framebuffer)); 583 LOG(2,("CRTC2: framebuffer: $%08x\n", si->fbc.frame_buffer)); 584 585 /* we might have no retraces during setmode! */ 586 /* wait 25mS max. for retrace to occur (refresh > 40Hz) */ 587 while (((NV_REG32(NV32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) && 588 (timeout < (25000/10))) 589 { 590 /* don't snooze much longer or retrace might get missed! */ 591 snooze(10); 592 timeout++; 593 } 594 595 /* enable access to secondary head */ 596 set_crtc_owner(1); 597 598 /* upto 4Gb RAM adressing: must be used on NV10 and later! */ 599 /* NOTE: 600 * While this register also exists on pre-NV10 cards, it will 601 * wrap-around at 16Mb boundaries!! */ 602 603 /* 30bit adress in 32bit words */ 604 NV_REG32(NV32_NV10FB2STADD32) = (startadd & 0xfffffffc); 605 606 /* set byte adress: (b0 - 1) */ 607 ATB2W(HORPIXPAN, ((startadd & 0x00000003) << 1)); 608 609 return B_OK; 610 } 611 612 status_t nv_crtc2_cursor_init() 613 { 614 int i; 615 uint32 * fb; 616 /* cursor bitmap will be stored at the start of the framebuffer */ 617 const uint32 curadd = 0; 618 619 /* enable access to secondary head */ 620 set_crtc_owner(1); 621 622 /* set cursor bitmap adress ... */ 623 if (si->ps.laptop) 624 { 625 /* must be used this way on pre-NV10 and on all 'Go' cards! */ 626 627 /* cursorbitmap must start on 2Kbyte boundary: */ 628 /* set adress bit11-16, and set 'no doublescan' (registerbit 1 = 0) */ 629 CRTC2W(CURCTL0, ((curadd & 0x0001f800) >> 9)); 630 /* set adress bit17-23, and set graphics mode cursor(?) (registerbit 7 = 1) */ 631 CRTC2W(CURCTL1, (((curadd & 0x00fe0000) >> 17) | 0x80)); 632 /* set adress bit24-31 */ 633 CRTC2W(CURCTL2, ((curadd & 0xff000000) >> 24)); 634 } 635 else 636 { 637 /* upto 4Gb RAM adressing: 638 * can be used on NV10 and later (except for 'Go' cards)! */ 639 /* NOTE: 640 * This register does not exist on pre-NV10 and 'Go' cards. */ 641 642 /* cursorbitmap must still start on 2Kbyte boundary: */ 643 NV_REG32(NV32_NV10CUR2ADD32) = (curadd & 0xfffff800); 644 } 645 646 /* set cursor colour: not needed because of direct nature of cursor bitmap. */ 647 648 /*clear cursor*/ 649 fb = (uint32 *) si->framebuffer + curadd; 650 for (i=0;i<(2048/4);i++) 651 { 652 fb[i]=0; 653 } 654 655 /* select 32x32 pixel, 16bit color cursorbitmap, no doublescan */ 656 NV_REG32(NV32_2CURCONF) = 0x02000100; 657 658 /* activate hardware-sync between cursor updates and vertical retrace */ 659 DAC2W(NV10_CURSYNC, (DAC2R(NV10_CURSYNC) | 0x02000000)); 660 661 /* activate hardware cursor */ 662 nv_crtc2_cursor_show(); 663 664 return B_OK; 665 } 666 667 status_t nv_crtc2_cursor_show() 668 { 669 LOG(4,("CRTC2: enabling cursor\n")); 670 671 /* enable access to secondary head */ 672 set_crtc_owner(1); 673 674 /* b0 = 1 enables cursor */ 675 CRTC2W(CURCTL0, (CRTC2R(CURCTL0) | 0x01)); 676 677 /* workaround for hardware bug confirmed existing on NV43: 678 * Cursor visibility is not updated without a position update if its hardware 679 * retrace sync is enabled. */ 680 if (si->ps.card_arch == NV40A) DAC2W(CURPOS, (DAC2R(CURPOS))); 681 682 return B_OK; 683 } 684 685 status_t nv_crtc2_cursor_hide() 686 { 687 LOG(4,("CRTC2: disabling cursor\n")); 688 689 /* enable access to secondary head */ 690 set_crtc_owner(1); 691 692 /* b0 = 0 disables cursor */ 693 CRTC2W(CURCTL0, (CRTC2R(CURCTL0) & 0xfe)); 694 695 /* workaround for hardware bug confirmed existing on NV43: 696 * Cursor visibility is not updated without a position update if its hardware 697 * retrace sync is enabled. */ 698 if (si->ps.card_arch == NV40A) DAC2W(CURPOS, (DAC2R(CURPOS))); 699 700 return B_OK; 701 } 702 703 /*set up cursor shape*/ 704 status_t nv_crtc2_cursor_define(uint8* andMask,uint8* xorMask) 705 { 706 int x, y; 707 uint8 b; 708 uint16 *cursor; 709 uint16 pixel; 710 711 /* get a pointer to the cursor */ 712 cursor = (uint16*) si->framebuffer; 713 714 /* draw the cursor */ 715 /* (Nvidia cards have a RGB15 direct color cursor bitmap, bit #16 is transparancy) */ 716 for (y = 0; y < 16; y++) 717 { 718 b = 0x80; 719 for (x = 0; x < 8; x++) 720 { 721 /* preset transparant */ 722 pixel = 0x0000; 723 /* set white if requested */ 724 if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; 725 /* set black if requested */ 726 if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; 727 /* set invert if requested */ 728 if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; 729 /* place the pixel in the bitmap */ 730 cursor[x + (y * 32)] = pixel; 731 b >>= 1; 732 } 733 xorMask++; 734 andMask++; 735 b = 0x80; 736 for (; x < 16; x++) 737 { 738 /* preset transparant */ 739 pixel = 0x0000; 740 /* set white if requested */ 741 if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; 742 /* set black if requested */ 743 if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; 744 /* set invert if requested */ 745 if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; 746 /* place the pixel in the bitmap */ 747 cursor[x + (y * 32)] = pixel; 748 b >>= 1; 749 } 750 xorMask++; 751 andMask++; 752 } 753 754 return B_OK; 755 } 756 757 /* position the cursor */ 758 status_t nv_crtc2_cursor_position(uint16 x, uint16 y) 759 { 760 /* the cursor position is updated during retrace by card hardware */ 761 762 /* update cursorposition */ 763 DAC2W(CURPOS, ((x & 0x0fff) | ((y & 0x0fff) << 16))); 764 765 return B_OK; 766 } 767 768 status_t nv_crtc2_stop_tvout(void) 769 { 770 LOG(4,("CRTC2: stopping TV output\n")); 771 772 /* enable access to secondary head */ 773 set_crtc_owner(1); 774 775 /* just to be sure Vsync is _really_ enabled */ 776 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xbf)); 777 778 /* wait for one image to be generated to make sure VGA has kicked in and is 779 * running OK before continuing... 780 * (Kicking in will fail often if we do not wait here) */ 781 /* Note: 782 * The used CRTC's Vsync is required to be enabled here. The DPMS state 783 * programming in the driver makes sure this is the case. 784 * (except for driver startup: see nv_general.c.) */ 785 786 /* make sure we are 'in' active VGA picture */ 787 while (NV_REG8(NV8_INSTAT1) & 0x08) snooze(1); 788 /* wait for next vertical retrace start on VGA */ 789 while (!(NV_REG8(NV8_INSTAT1) & 0x08)) snooze(1); 790 /* now wait until we are 'in' active VGA picture again */ 791 while (NV_REG8(NV8_INSTAT1) & 0x08) snooze(1); 792 793 794 /* set CRTC to master mode (b7 = 0) if it wasn't slaved for a panel before */ 795 if (!(si->ps.slaved_tmds2)) CRTC2W(PIXEL, (CRTC2R(PIXEL) & 0x03)); 796 797 /* CAUTION: 798 * On old cards, PLLSEL (and TV_SETUP?) cannot be read (sometimes?), but 799 * write actions do succeed ... 800 * This is confirmed for both ISA and PCI access, on NV04 and NV11. */ 801 802 /* setup TVencoder connection */ 803 /* b1-0 = %00: encoder type is SLAVE; 804 * b24 = 1: VIP datapos is b0-7 */ 805 //fixme if needed: setup completely instead of relying on pre-init by BIOS.. 806 //(it seems to work OK on NV04 and NV11 although read reg. doesn't seem to work) 807 DAC2W(TV_SETUP, ((DAC2R(TV_SETUP) & ~0x00000003) | 0x01000000)); 808 809 /* tell GPU to use pixelclock from internal source instead of using TVencoder */ 810 DACW(PLLSEL, 0x30000f00); 811 812 /* HTOTAL, VTOTAL and OVERFLOW return their default CRTC use, instead of 813 * H, V-low and V-high 'shadow' counters(?)(b0, 4 and 6 = 0) (b7 use = unknown) */ 814 CRTC2W(TREG, 0x00); 815 816 /* select panel encoder, not TV encoder if needed (b0 = 1). 817 * Note: 818 * Both are devices (often) using the CRTC in slaved mode. */ 819 if (si->ps.slaved_tmds2) CRTC2W(LCD, (CRTC2R(LCD) | 0x01)); 820 821 return B_OK; 822 } 823 824 status_t nv_crtc2_start_tvout(void) 825 { 826 LOG(4,("CRTC2: starting TV output\n")); 827 828 /* switch TV encoder to CRTC2 */ 829 NV_REG32(NV32_FUNCSEL) &= ~0x00000100; 830 NV_REG32(NV32_2FUNCSEL) |= 0x00000100; 831 832 /* enable access to secondary head */ 833 set_crtc_owner(1); 834 835 /* CAUTION: 836 * On old cards, PLLSEL (and TV_SETUP?) cannot be read (sometimes?), but 837 * write actions do succeed ... 838 * This is confirmed for both ISA and PCI access, on NV04 and NV11. */ 839 840 /* setup TVencoder connection */ 841 /* b1-0 = %01: encoder type is MASTER; 842 * b24 = 1: VIP datapos is b0-7 */ 843 //fixme if needed: setup completely instead of relying on pre-init by BIOS.. 844 //(it seems to work OK on NV04 and NV11 although read reg. doesn't seem to work) 845 DAC2W(TV_SETUP, ((DAC2R(TV_SETUP) & ~0x00000002) | 0x01000001)); 846 847 /* tell GPU to use pixelclock from TVencoder instead of using internal source */ 848 /* (nessecary or display will 'shiver' on both TV and VGA.) */ 849 DACW(PLLSEL, 0x100c0f00); 850 851 /* Set overscan color to 'black' */ 852 /* note: 853 * Change this instruction for a visible overscan color if you're trying to 854 * center the output on TV. Use it as a guide-'line' then ;-) */ 855 ATB2W(OSCANCOLOR, 0x00); 856 857 /* set CRTC to slaved mode (b7 = 1) and clear TVadjust (b3-5 = %000) */ 858 CRTC2W(PIXEL, ((CRTC2R(PIXEL) & 0xc7) | 0x80)); 859 /* select TV encoder, not panel encoder (b0 = 0). 860 * Note: 861 * Both are devices (often) using the CRTC in slaved mode. */ 862 CRTC2W(LCD, (CRTC2R(LCD) & 0xfe)); 863 864 /* HTOTAL, VTOTAL and OVERFLOW return their default CRTC use, instead of 865 * H, V-low and V-high 'shadow' counters(?)(b0, 4 and 6 = 0) (b7 use = unknown) */ 866 CRTC2W(TREG, 0x80); 867 868 return B_OK; 869 } 870