1 /* second CTRC functionality for GeForce cards */ 2 /* Author: 3 Rudolf Cornelissen 11/2002-1/2006 4 */ 5 6 #define MODULE_BIT 0x00020000 7 8 #include "nv_std.h" 9 10 /* doing general fail-safe default setup here */ 11 //fixme: this is a _very_ basic setup, and it's preliminary... 12 status_t nv_crtc2_update_fifo() 13 { 14 uint8 bytes_per_pixel = 1; 15 uint32 drain; 16 17 /* we are only using this on >>coldstarted<< cards which really need this */ 18 //fixme: re-enable or remove after general user confirmation of behaviour... 19 if (/*(si->settings.usebios) ||*/ (si->ps.card_type != NV11)) return B_OK; 20 21 /* enable access to secondary head */ 22 set_crtc_owner(1); 23 24 /* set CRTC FIFO low watermark according to memory drain */ 25 switch(si->dm.space) 26 { 27 case B_CMAP8: 28 bytes_per_pixel = 1; 29 break; 30 case B_RGB15_LITTLE: 31 case B_RGB16_LITTLE: 32 bytes_per_pixel = 2; 33 break; 34 case B_RGB24_LITTLE: 35 bytes_per_pixel = 3; 36 break; 37 case B_RGB32_LITTLE: 38 bytes_per_pixel = 4; 39 break; 40 } 41 /* fixme: 42 * - I should probably include the refreshrate as well; 43 * - and the memory clocking speed, core clocking speed, RAM buswidth.. */ 44 drain = si->dm.timing.h_display * si->dm.timing.v_display * bytes_per_pixel; 45 46 /* Doesn't work for other than 32bit space (yet?) */ 47 if (si->dm.space != B_RGB32_LITTLE) 48 { 49 /* BIOS defaults */ 50 CRTC2W(FIFO, 0x03); 51 CRTC2W(FIFO_LWM, 0x20); 52 LOG(4,("CRTC2: FIFO low-watermark set to $20, burst size 256 (BIOS defaults)\n")); 53 return B_OK; 54 } 55 56 if (drain > (((uint32)1280) * 1024 * 4)) 57 { 58 /* set CRTC FIFO burst size for 'smaller' bursts */ 59 CRTC2W(FIFO, 0x01); 60 /* Instruct CRTC to fetch new data 'earlier' */ 61 CRTC2W(FIFO_LWM, 0x40); 62 LOG(4,("CRTC2: FIFO low-watermark set to $40, burst size 64\n")); 63 } 64 else 65 { 66 if (drain > (((uint32)1024) * 768 * 4)) 67 { 68 /* BIOS default */ 69 CRTC2W(FIFO, 0x02); 70 /* Instruct CRTC to fetch new data 'earlier' */ 71 CRTC2W(FIFO_LWM, 0x40); 72 LOG(4,("CRTC2: FIFO low-watermark set to $40, burst size 128\n")); 73 } 74 else 75 { 76 /* BIOS defaults */ 77 CRTC2W(FIFO, 0x03); 78 CRTC2W(FIFO_LWM, 0x20); 79 LOG(4,("CRTC2: FIFO low-watermark set to $20, burst size 256 (BIOS defaults)\n")); 80 } 81 } 82 83 return B_OK; 84 } 85 86 /* Adjust passed parameters to a valid mode line */ 87 status_t nv_crtc2_validate_timing( 88 uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht, 89 uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt 90 ) 91 { 92 /* horizontal */ 93 /* make all parameters multiples of 8 */ 94 *hd_e &= 0xfff8; 95 *hs_s &= 0xfff8; 96 *hs_e &= 0xfff8; 97 *ht &= 0xfff8; 98 99 /* confine to required number of bits, taking logic into account */ 100 if (*hd_e > ((0x01ff - 2) << 3)) *hd_e = ((0x01ff - 2) << 3); 101 if (*hs_s > ((0x01ff - 1) << 3)) *hs_s = ((0x01ff - 1) << 3); 102 if (*hs_e > ( 0x01ff << 3)) *hs_e = ( 0x01ff << 3); 103 if (*ht > ((0x01ff + 5) << 3)) *ht = ((0x01ff + 5) << 3); 104 105 /* NOTE: keep horizontal timing at multiples of 8! */ 106 /* confine to a reasonable width */ 107 if (*hd_e < 640) *hd_e = 640; 108 if (*hd_e > 2048) *hd_e = 2048; 109 110 /* if hor. total does not leave room for a sensible sync pulse, increase it! */ 111 if (*ht < (*hd_e + 80)) *ht = (*hd_e + 80); 112 113 /* if hor. total does not adhere to max. blanking pulse width, decrease it! */ 114 if (*ht > (*hd_e + 0x3f8)) *ht = (*hd_e + 0x3f8); 115 116 /* make sure sync pulse is not during display */ 117 if (*hs_e > (*ht - 8)) *hs_e = (*ht - 8); 118 if (*hs_s < (*hd_e + 8)) *hs_s = (*hd_e + 8); 119 120 /* correct sync pulse if it is too long: 121 * there are only 5 bits available to save this in the card registers! */ 122 if (*hs_e > (*hs_s + 0xf8)) *hs_e = (*hs_s + 0xf8); 123 124 /*vertical*/ 125 /* confine to required number of bits, taking logic into account */ 126 //fixme if needed: on GeForce cards there are 12 instead of 11 bits... 127 if (*vd_e > (0x7ff - 2)) *vd_e = (0x7ff - 2); 128 if (*vs_s > (0x7ff - 1)) *vs_s = (0x7ff - 1); 129 if (*vs_e > 0x7ff ) *vs_e = 0x7ff ; 130 if (*vt > (0x7ff + 2)) *vt = (0x7ff + 2); 131 132 /* confine to a reasonable height */ 133 if (*vd_e < 480) *vd_e = 480; 134 if (*vd_e > 1536) *vd_e = 1536; 135 136 /*if vertical total does not leave room for a sync pulse, increase it!*/ 137 if (*vt < (*vd_e + 3)) *vt = (*vd_e + 3); 138 139 /* if vert. total does not adhere to max. blanking pulse width, decrease it! */ 140 if (*vt > (*vd_e + 0xff)) *vt = (*vd_e + 0xff); 141 142 /* make sure sync pulse is not during display */ 143 if (*vs_e > (*vt - 1)) *vs_e = (*vt - 1); 144 if (*vs_s < (*vd_e + 1)) *vs_s = (*vd_e + 1); 145 146 /* correct sync pulse if it is too long: 147 * there are only 4 bits available to save this in the card registers! */ 148 if (*vs_e > (*vs_s + 0x0f)) *vs_e = (*vs_s + 0x0f); 149 150 return B_OK; 151 } 152 153 /*set a mode line - inputs are in pixels*/ 154 status_t nv_crtc2_set_timing(display_mode target) 155 { 156 uint8 temp; 157 158 uint32 htotal; /*total horizontal total VCLKs*/ 159 uint32 hdisp_e; /*end of horizontal display (begins at 0)*/ 160 uint32 hsync_s; /*begin of horizontal sync pulse*/ 161 uint32 hsync_e; /*end of horizontal sync pulse*/ 162 uint32 hblnk_s; /*begin horizontal blanking*/ 163 uint32 hblnk_e; /*end horizontal blanking*/ 164 165 uint32 vtotal; /*total vertical total scanlines*/ 166 uint32 vdisp_e; /*end of vertical display*/ 167 uint32 vsync_s; /*begin of vertical sync pulse*/ 168 uint32 vsync_e; /*end of vertical sync pulse*/ 169 uint32 vblnk_s; /*begin vertical blanking*/ 170 uint32 vblnk_e; /*end vertical blanking*/ 171 172 uint32 linecomp; /*split screen and vdisp_e interrupt*/ 173 174 LOG(4,("CRTC2: setting timing\n")); 175 176 /* setup tuned internal modeline for flatpanel if connected and active */ 177 /* notes: 178 * - the CRTC modeline must end earlier than the panel modeline to keep correct 179 * sync going; 180 * - if the CRTC modeline ends too soon, pixelnoise will occur in 8 (or so) pixel 181 * wide horizontal stripes. This can be observed earliest on fullscreen overlay, 182 * and if it gets worse, also normal desktop output will suffer. The stripes 183 * are mainly visible at the left of the screen, over the entire screen height. */ 184 if (si->ps.tmds2_active) 185 { 186 LOG(2,("CRTC2: DFP active: tuning modeline\n")); 187 188 /* horizontal timing */ 189 target.timing.h_sync_start = 190 ((uint16)((si->ps.p2_timing.h_sync_start / ((float)si->ps.p2_timing.h_display)) * 191 target.timing.h_display)) & 0xfff8; 192 193 target.timing.h_sync_end = 194 ((uint16)((si->ps.p2_timing.h_sync_end / ((float)si->ps.p2_timing.h_display)) * 195 target.timing.h_display)) & 0xfff8; 196 197 target.timing.h_total = 198 (((uint16)((si->ps.p2_timing.h_total / ((float)si->ps.p2_timing.h_display)) * 199 target.timing.h_display)) & 0xfff8) - 8; 200 201 /* in native mode the CRTC needs some extra time to keep synced correctly; 202 * OTOH the overlay unit distorts if we reserve too much time! */ 203 if (target.timing.h_display == si->ps.p2_timing.h_display) 204 { 205 /* NV11 timing has different constraints than later cards */ 206 if (si->ps.card_type == NV11) 207 target.timing.h_total -= 56; 208 else 209 /* confirmed NV34 with 1680x1050 panel */ 210 target.timing.h_total -= 32; 211 } 212 213 if (target.timing.h_sync_start == target.timing.h_display) 214 target.timing.h_sync_start += 8; 215 if (target.timing.h_sync_end == target.timing.h_total) 216 target.timing.h_sync_end -= 8; 217 218 /* vertical timing */ 219 target.timing.v_sync_start = 220 ((uint16)((si->ps.p2_timing.v_sync_start / ((float)si->ps.p2_timing.v_display)) * 221 target.timing.v_display)); 222 223 target.timing.v_sync_end = 224 ((uint16)((si->ps.p2_timing.v_sync_end / ((float)si->ps.p2_timing.v_display)) * 225 target.timing.v_display)); 226 227 target.timing.v_total = 228 ((uint16)((si->ps.p2_timing.v_total / ((float)si->ps.p2_timing.v_display)) * 229 target.timing.v_display)) - 1; 230 231 if (target.timing.v_sync_start == target.timing.v_display) 232 target.timing.v_sync_start += 1; 233 if (target.timing.v_sync_end == target.timing.v_total) 234 target.timing.v_sync_end -= 1; 235 236 /* disable GPU scaling testmode so automatic scaling will be done */ 237 DAC2W(FP_DEBUG1, 0); 238 } 239 240 /* Modify parameters as required by standard VGA */ 241 htotal = ((target.timing.h_total >> 3) - 5); 242 hdisp_e = ((target.timing.h_display >> 3) - 1); 243 hblnk_s = hdisp_e; 244 hblnk_e = (htotal + 4); 245 hsync_s = (target.timing.h_sync_start >> 3); 246 hsync_e = (target.timing.h_sync_end >> 3); 247 248 vtotal = target.timing.v_total - 2; 249 vdisp_e = target.timing.v_display - 1; 250 vblnk_s = vdisp_e; 251 vblnk_e = (vtotal + 1); 252 vsync_s = target.timing.v_sync_start; 253 vsync_e = target.timing.v_sync_end; 254 255 /* prevent memory adress counter from being reset (linecomp may not occur) */ 256 linecomp = target.timing.v_display; 257 258 /* enable access to secondary head */ 259 set_crtc_owner(1); 260 261 /* Note for laptop and DVI flatpanels: 262 * CRTC timing has a seperate set of registers from flatpanel timing. 263 * The flatpanel timing registers have scaling registers that are used to match 264 * these two modelines. */ 265 { 266 LOG(4,("CRTC2: Setting full timing...\n")); 267 268 /* log the mode that will be set */ 269 LOG(2,("CRTC2:\n\tHTOT:%x\n\tHDISPEND:%x\n\tHBLNKS:%x\n\tHBLNKE:%x\n\tHSYNCS:%x\n\tHSYNCE:%x\n\t",htotal,hdisp_e,hblnk_s,hblnk_e,hsync_s,hsync_e)); 270 LOG(2,("VTOT:%x\n\tVDISPEND:%x\n\tVBLNKS:%x\n\tVBLNKE:%x\n\tVSYNCS:%x\n\tVSYNCE:%x\n",vtotal,vdisp_e,vblnk_s,vblnk_e,vsync_s,vsync_e)); 271 272 /* actually program the card! */ 273 /* unlock CRTC registers at index 0-7 */ 274 CRTC2W(VSYNCE, (CRTC2R(VSYNCE) & 0x7f)); 275 /* horizontal standard VGA regs */ 276 CRTC2W(HTOTAL, (htotal & 0xff)); 277 CRTC2W(HDISPE, (hdisp_e & 0xff)); 278 CRTC2W(HBLANKS, (hblnk_s & 0xff)); 279 /* also unlock vertical retrace registers in advance */ 280 CRTC2W(HBLANKE, ((hblnk_e & 0x1f) | 0x80)); 281 CRTC2W(HSYNCS, (hsync_s & 0xff)); 282 CRTC2W(HSYNCE, ((hsync_e & 0x1f) | ((hblnk_e & 0x20) << 2))); 283 284 /* vertical standard VGA regs */ 285 CRTC2W(VTOTAL, (vtotal & 0xff)); 286 CRTC2W(OVERFLOW, 287 ( 288 ((vtotal & 0x100) >> (8 - 0)) | ((vtotal & 0x200) >> (9 - 5)) | 289 ((vdisp_e & 0x100) >> (8 - 1)) | ((vdisp_e & 0x200) >> (9 - 6)) | 290 ((vsync_s & 0x100) >> (8 - 2)) | ((vsync_s & 0x200) >> (9 - 7)) | 291 ((vblnk_s & 0x100) >> (8 - 3)) | ((linecomp & 0x100) >> (8 - 4)) 292 )); 293 CRTC2W(PRROWSCN, 0x00); /* not used */ 294 CRTC2W(MAXSCLIN, (((vblnk_s & 0x200) >> (9 - 5)) | ((linecomp & 0x200) >> (9 - 6)))); 295 CRTC2W(VSYNCS, (vsync_s & 0xff)); 296 CRTC2W(VSYNCE, ((CRTC2R(VSYNCE) & 0xf0) | (vsync_e & 0x0f))); 297 CRTC2W(VDISPE, (vdisp_e & 0xff)); 298 CRTC2W(VBLANKS, (vblnk_s & 0xff)); 299 CRTC2W(VBLANKE, (vblnk_e & 0xff)); 300 CRTC2W(LINECOMP, (linecomp & 0xff)); 301 302 /* horizontal extended regs */ 303 //fixme: we reset bit4. is this correct?? 304 CRTC2W(HEB, (CRTC2R(HEB) & 0xe0) | 305 ( 306 ((htotal & 0x100) >> (8 - 0)) | 307 ((hdisp_e & 0x100) >> (8 - 1)) | 308 ((hblnk_s & 0x100) >> (8 - 2)) | 309 ((hsync_s & 0x100) >> (8 - 3)) 310 )); 311 312 /* (mostly) vertical extended regs */ 313 CRTC2W(LSR, 314 ( 315 ((vtotal & 0x400) >> (10 - 0)) | 316 ((vdisp_e & 0x400) >> (10 - 1)) | 317 ((vsync_s & 0x400) >> (10 - 2)) | 318 ((vblnk_s & 0x400) >> (10 - 3)) | 319 ((hblnk_e & 0x040) >> (6 - 4)) 320 //fixme: we still miss one linecomp bit!?! is this it?? 321 //| ((linecomp & 0x400) >> 3) 322 )); 323 324 /* more vertical extended regs */ 325 CRTC2W(EXTRA, 326 ( 327 ((vtotal & 0x800) >> (11 - 0)) | 328 ((vdisp_e & 0x800) >> (11 - 2)) | 329 ((vsync_s & 0x800) >> (11 - 4)) | 330 ((vblnk_s & 0x800) >> (11 - 6)) 331 //fixme: do we miss another linecomp bit!?! 332 )); 333 334 /* setup 'large screen' mode */ 335 if (target.timing.h_display >= 1280) 336 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xfb)); 337 else 338 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x04)); 339 340 /* setup HSYNC & VSYNC polarity */ 341 LOG(2,("CRTC2: sync polarity: ")); 342 temp = NV_REG8(NV8_MISCR); 343 if (target.timing.flags & B_POSITIVE_HSYNC) 344 { 345 LOG(2,("H:pos ")); 346 temp &= ~0x40; 347 } 348 else 349 { 350 LOG(2,("H:neg ")); 351 temp |= 0x40; 352 } 353 if (target.timing.flags & B_POSITIVE_VSYNC) 354 { 355 LOG(2,("V:pos ")); 356 temp &= ~0x80; 357 } 358 else 359 { 360 LOG(2,("V:neg ")); 361 temp |= 0x80; 362 } 363 NV_REG8(NV8_MISCW) = temp; 364 365 LOG(2,(", MISC reg readback: $%02x\n", NV_REG8(NV8_MISCR))); 366 } 367 368 /* always disable interlaced operation */ 369 /* (interlace is supported on upto and including NV10, NV15, and NV30 and up) */ 370 CRTC2W(INTERLACE, 0xff); 371 372 /* disable CRTC slaved mode unless a panel is in use */ 373 // fixme: this kills TVout when it was in use... 374 if (!si->ps.tmds2_active) CRTC2W(PIXEL, (CRTC2R(PIXEL) & 0x7f)); 375 376 /* setup flatpanel if connected and active */ 377 if (si->ps.tmds2_active) 378 { 379 uint32 iscale_x, iscale_y; 380 381 /* calculate inverse scaling factors used by hardware in 20.12 format */ 382 iscale_x = (((1 << 12) * target.timing.h_display) / si->ps.p2_timing.h_display); 383 iscale_y = (((1 << 12) * target.timing.v_display) / si->ps.p2_timing.v_display); 384 385 /* unblock flatpanel timing programming (or something like that..) */ 386 CRTC2W(FP_HTIMING, 0); 387 CRTC2W(FP_VTIMING, 0); 388 LOG(2,("CRTC2: FP_HTIMING reg readback: $%02x\n", CRTC2R(FP_HTIMING))); 389 LOG(2,("CRTC2: FP_VTIMING reg readback: $%02x\n", CRTC2R(FP_VTIMING))); 390 391 /* enable full width visibility on flatpanel */ 392 DAC2W(FP_HVALID_S, 0); 393 DAC2W(FP_HVALID_E, (si->ps.p2_timing.h_display - 1)); 394 /* enable full height visibility on flatpanel */ 395 DAC2W(FP_VVALID_S, 0); 396 DAC2W(FP_VVALID_E, (si->ps.p2_timing.v_display - 1)); 397 398 /* nVidia cards support upscaling except on ??? */ 399 /* NV11 cards can upscale after all! */ 400 if (0)//si->ps.card_type == NV11) 401 { 402 /* disable last fetched line limiting */ 403 DAC2W(FP_DEBUG2, 0x00000000); 404 /* inform panel to scale if needed */ 405 if ((iscale_x != (1 << 12)) || (iscale_y != (1 << 12))) 406 { 407 LOG(2,("CRTC2: DFP needs to do scaling\n")); 408 DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) | 0x00000100)); 409 } 410 else 411 { 412 LOG(2,("CRTC2: no scaling for DFP needed\n")); 413 DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) & 0xfffffeff)); 414 } 415 } 416 else 417 { 418 float dm_aspect; 419 420 LOG(2,("CRTC2: GPU scales for DFP if needed\n")); 421 422 /* calculate display mode aspect */ 423 dm_aspect = (target.timing.h_display / ((float)target.timing.v_display)); 424 425 /* limit last fetched line if vertical scaling is done */ 426 if (iscale_y != (1 << 12)) 427 DAC2W(FP_DEBUG2, ((1 << 28) | ((target.timing.v_display - 1) << 16))); 428 else 429 DAC2W(FP_DEBUG2, 0x00000000); 430 431 /* inform panel not to scale */ 432 DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) & 0xfffffeff)); 433 434 /* GPU scaling is automatically setup by hardware, so only modify this 435 * scalingfactor for non 4:3 (1.33) aspect panels; 436 * let's consider 1280x1024 1:33 aspect (it's 1.25 aspect actually!) */ 437 438 /* correct for widescreen panels relative to mode... 439 * (so if panel is more widescreen than mode being set) */ 440 /* BTW: known widescreen panels: 441 * 1280 x 800 (1.60), 442 * 1440 x 900 (1.60), 443 * 1680 x 1050 (1.60), 444 * 1920 x 1200 (1.60). */ 445 /* known 4:3 aspect non-standard resolution panels: 446 * 1400 x 1050 (1.33). */ 447 /* NOTE: 448 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */ 449 if ((iscale_x != (1 << 12)) && (si->ps.panel2_aspect > (dm_aspect + 0.10))) 450 { 451 uint16 diff; 452 453 LOG(2,("CRTC2: (relative) widescreen panel: tuning horizontal scaling\n")); 454 455 /* X-scaling should be the same as Y-scaling */ 456 iscale_x = iscale_y; 457 /* enable testmode (b12) and program new X-scaling factor */ 458 DAC2W(FP_DEBUG1, (((iscale_x >> 1) & 0x00000fff) | (1 << 12))); 459 /* center/cut-off left and right side of screen */ 460 diff = ((si->ps.p2_timing.h_display - 461 ((target.timing.h_display * (1 << 12)) / iscale_x)) 462 / 2); 463 DAC2W(FP_HVALID_S, diff); 464 DAC2W(FP_HVALID_E, ((si->ps.p2_timing.h_display - diff) - 1)); 465 } 466 /* correct for portrait panels... */ 467 /* NOTE: 468 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */ 469 if ((iscale_y != (1 << 12)) && (si->ps.panel2_aspect < (dm_aspect - 0.10))) 470 { 471 LOG(2,("CRTC2: (relative) portrait panel: should tune vertical scaling\n")); 472 /* fixme: implement if this kind of portrait panels exist on nVidia... */ 473 } 474 } 475 476 /* do some logging.. */ 477 LOG(2,("CRTC2: FP_HVALID_S reg readback: $%08x\n", DAC2R(FP_HVALID_S))); 478 LOG(2,("CRTC2: FP_HVALID_E reg readback: $%08x\n", DAC2R(FP_HVALID_E))); 479 LOG(2,("CRTC2: FP_VVALID_S reg readback: $%08x\n", DAC2R(FP_VVALID_S))); 480 LOG(2,("CRTC2: FP_VVALID_E reg readback: $%08x\n", DAC2R(FP_VVALID_E))); 481 LOG(2,("CRTC2: FP_DEBUG0 reg readback: $%08x\n", DAC2R(FP_DEBUG0))); 482 LOG(2,("CRTC2: FP_DEBUG1 reg readback: $%08x\n", DAC2R(FP_DEBUG1))); 483 LOG(2,("CRTC2: FP_DEBUG2 reg readback: $%08x\n", DAC2R(FP_DEBUG2))); 484 LOG(2,("CRTC2: FP_DEBUG3 reg readback: $%08x\n", DAC2R(FP_DEBUG3))); 485 LOG(2,("CRTC2: FP_TG_CTRL reg readback: $%08x\n", DAC2R(FP_TG_CTRL))); 486 } 487 488 return B_OK; 489 } 490 491 status_t nv_crtc2_depth(int mode) 492 { 493 uint8 viddelay = 0; 494 uint32 genctrl = 0; 495 496 /* set VCLK scaling */ 497 switch(mode) 498 { 499 case BPP8: 500 viddelay = 0x01; 501 /* genctrl b4 & b5 reset: 'direct mode' */ 502 genctrl = 0x00101100; 503 break; 504 case BPP15: 505 viddelay = 0x02; 506 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 507 genctrl = 0x00100130; 508 break; 509 case BPP16: 510 viddelay = 0x02; 511 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 512 genctrl = 0x00101130; 513 break; 514 case BPP24: 515 viddelay = 0x03; 516 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 517 genctrl = 0x00100130; 518 break; 519 case BPP32: 520 viddelay = 0x03; 521 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 522 genctrl = 0x00101130; 523 break; 524 } 525 /* enable access to secondary head */ 526 set_crtc_owner(1); 527 528 CRTC2W(PIXEL, ((CRTC2R(PIXEL) & 0xfc) | viddelay)); 529 DAC2W(GENCTRL, genctrl); 530 531 return B_OK; 532 } 533 534 status_t nv_crtc2_dpms(bool display, bool h, bool v, bool do_panel) 535 { 536 uint8 temp; 537 char msg[100]; 538 539 sprintf(msg, "CRTC2: setting DPMS: "); 540 541 /* enable access to secondary head */ 542 set_crtc_owner(1); 543 544 /* start synchronous reset: required before turning screen off! */ 545 SEQW(RESET, 0x01); 546 547 temp = SEQR(CLKMODE); 548 if (display) 549 { 550 /* turn screen on */ 551 SEQW(CLKMODE, (temp & ~0x20)); 552 553 /* end synchronous reset because display should be enabled */ 554 SEQW(RESET, 0x03); 555 556 if (do_panel && si->ps.tmds2_active) 557 { 558 if (!si->ps.laptop) 559 { 560 /* restore original panelsync and panel-enable */ 561 uint32 panelsync = 0x00000000; 562 if(si->ps.p2_timing.flags & B_POSITIVE_VSYNC) panelsync |= 0x00000001; 563 if(si->ps.p2_timing.flags & B_POSITIVE_HSYNC) panelsync |= 0x00000010; 564 /* display enable polarity (not an official flag) */ 565 if(si->ps.p2_timing.flags & B_BLANK_PEDESTAL) panelsync |= 0x10000000; 566 DAC2W(FP_TG_CTRL, ((DAC2R(FP_TG_CTRL) & 0xcfffffcc) | panelsync)); 567 568 //fixme?: looks like we don't need this after all: 569 /* powerup both LVDS (laptop panellink) and TMDS (DVI panellink) 570 * internal transmitters... */ 571 /* note: 572 * the powerbits in this register are hardwired to the DVI connectors, 573 * instead of to the DACs! (confirmed NV34) */ 574 //fixme... 575 //DAC2W(FP_DEBUG0, (DAC2R(FP_DEBUG0) & 0xcfffffff)); 576 /* ... and powerup external TMDS transmitter if it exists */ 577 /* (confirmed OK on NV28 and NV34) */ 578 //CRTC2W(0x59, (CRTC2R(0x59) | 0x01)); 579 580 sprintf(msg, "%s(panel-)", msg); 581 } 582 else 583 { 584 //fixme: see if LVDS head can be determined with two panels there... 585 if (!si->ps.tmds1_active && (si->ps.card_type != NV11)) 586 { 587 /* b2 = 0 = enable laptop panel backlight */ 588 /* note: this seems to be a write-only register. */ 589 NV_REG32(NV32_LVDS_PWR) = 0x00000003; 590 591 sprintf(msg, "%s(panel-)", msg); 592 } 593 } 594 } 595 596 sprintf(msg, "%sdisplay on, ", msg); 597 } 598 else 599 { 600 /* turn screen off */ 601 SEQW(CLKMODE, (temp | 0x20)); 602 603 if (do_panel && si->ps.tmds2_active) 604 { 605 if (!si->ps.laptop) 606 { 607 /* shutoff panelsync and disable panel */ 608 DAC2W(FP_TG_CTRL, ((DAC2R(FP_TG_CTRL) & 0xcfffffcc) | 0x20000022)); 609 610 //fixme?: looks like we don't need this after all: 611 /* powerdown both LVDS (laptop panellink) and TMDS (DVI panellink) 612 * internal transmitters... */ 613 /* note: 614 * the powerbits in this register are hardwired to the DVI connectors, 615 * instead of to the DACs! (confirmed NV34) */ 616 //fixme... 617 //DAC2W(FP_DEBUG0, (DAC2R(FP_DEBUG0) | 0x30000000)); 618 /* ... and powerdown external TMDS transmitter if it exists */ 619 /* (confirmed OK on NV28 and NV34) */ 620 //CRTC2W(0x59, (CRTC2R(0x59) & 0xfe)); 621 622 sprintf(msg, "%s(panel-)", msg); 623 } 624 else 625 { 626 //fixme: see if LVDS head can be determined with two panels there... 627 if (!si->ps.tmds1_active && (si->ps.card_type != NV11)) 628 { 629 /* b2 = 1 = disable laptop panel backlight */ 630 /* note: this seems to be a write-only register. */ 631 NV_REG32(NV32_LVDS_PWR) = 0x00000007; 632 633 sprintf(msg, "%s(panel-)", msg); 634 } 635 } 636 } 637 638 sprintf(msg, "%sdisplay off, ", msg); 639 } 640 641 if (h) 642 { 643 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0x7f)); 644 sprintf(msg, "%shsync enabled, ", msg); 645 } 646 else 647 { 648 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x80)); 649 sprintf(msg, "%shsync disabled, ", msg); 650 } 651 if (v) 652 { 653 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xbf)); 654 sprintf(msg, "%svsync enabled\n", msg); 655 } 656 else 657 { 658 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x40)); 659 sprintf(msg, "%svsync disabled\n", msg); 660 } 661 662 LOG(4, (msg)); 663 664 return B_OK; 665 } 666 667 status_t nv_crtc2_set_display_pitch() 668 { 669 uint32 offset; 670 671 LOG(4,("CRTC2: setting card pitch (offset between lines)\n")); 672 673 /* figure out offset value hardware needs */ 674 offset = si->fbc.bytes_per_row / 8; 675 676 LOG(2,("CRTC2: offset register set to: $%04x\n", offset)); 677 678 /* enable access to secondary head */ 679 set_crtc_owner(1); 680 681 /* program the card */ 682 CRTC2W(PITCHL, (offset & 0x00ff)); 683 CRTC2W(REPAINT0, ((CRTC2R(REPAINT0) & 0x1f) | ((offset & 0x0700) >> 3))); 684 685 return B_OK; 686 } 687 688 status_t nv_crtc2_set_display_start(uint32 startadd,uint8 bpp) 689 { 690 uint32 timeout = 0; 691 692 LOG(4,("CRTC2: setting card RAM to be displayed bpp %d\n", bpp)); 693 694 LOG(2,("CRTC2: startadd: $%08x\n", startadd)); 695 LOG(2,("CRTC2: frameRAM: $%08x\n", si->framebuffer)); 696 LOG(2,("CRTC2: framebuffer: $%08x\n", si->fbc.frame_buffer)); 697 698 /* we might have no retraces during setmode! */ 699 /* wait 25mS max. for retrace to occur (refresh > 40Hz) */ 700 while (((NV_REG32(NV32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) && 701 (timeout < (25000/10))) 702 { 703 /* don't snooze much longer or retrace might get missed! */ 704 snooze(10); 705 timeout++; 706 } 707 708 /* enable access to secondary head */ 709 set_crtc_owner(1); 710 711 /* upto 4Gb RAM adressing: must be used on NV10 and later! */ 712 /* NOTE: 713 * While this register also exists on pre-NV10 cards, it will 714 * wrap-around at 16Mb boundaries!! */ 715 716 /* 30bit adress in 32bit words */ 717 NV_REG32(NV32_NV10FB2STADD32) = (startadd & 0xfffffffc); 718 719 /* set byte adress: (b0 - 1) */ 720 ATB2W(HORPIXPAN, ((startadd & 0x00000003) << 1)); 721 722 return B_OK; 723 } 724 725 status_t nv_crtc2_cursor_init() 726 { 727 int i; 728 uint32 * fb; 729 /* cursor bitmap will be stored at the start of the framebuffer */ 730 const uint32 curadd = 0; 731 732 /* enable access to secondary head */ 733 set_crtc_owner(1); 734 735 /* set cursor bitmap adress ... */ 736 if (si->ps.laptop) 737 { 738 /* must be used this way on pre-NV10 and on all 'Go' cards! */ 739 740 /* cursorbitmap must start on 2Kbyte boundary: */ 741 /* set adress bit11-16, and set 'no doublescan' (registerbit 1 = 0) */ 742 CRTC2W(CURCTL0, ((curadd & 0x0001f800) >> 9)); 743 /* set adress bit17-23, and set graphics mode cursor(?) (registerbit 7 = 1) */ 744 CRTC2W(CURCTL1, (((curadd & 0x00fe0000) >> 17) | 0x80)); 745 /* set adress bit24-31 */ 746 CRTC2W(CURCTL2, ((curadd & 0xff000000) >> 24)); 747 } 748 else 749 { 750 /* upto 4Gb RAM adressing: 751 * can be used on NV10 and later (except for 'Go' cards)! */ 752 /* NOTE: 753 * This register does not exist on pre-NV10 and 'Go' cards. */ 754 755 /* cursorbitmap must still start on 2Kbyte boundary: */ 756 NV_REG32(NV32_NV10CUR2ADD32) = (curadd & 0xfffff800); 757 } 758 759 /* set cursor colour: not needed because of direct nature of cursor bitmap. */ 760 761 /*clear cursor*/ 762 fb = (uint32 *) si->framebuffer + curadd; 763 for (i=0;i<(2048/4);i++) 764 { 765 fb[i]=0; 766 } 767 768 /* select 32x32 pixel, 16bit color cursorbitmap, no doublescan */ 769 NV_REG32(NV32_2CURCONF) = 0x02000100; 770 771 /* activate hardware-sync between cursor updates and vertical retrace */ 772 DAC2W(NV10_CURSYNC, (DAC2R(NV10_CURSYNC) | 0x02000000)); 773 774 /* activate hardware cursor */ 775 nv_crtc2_cursor_show(); 776 777 return B_OK; 778 } 779 780 status_t nv_crtc2_cursor_show() 781 { 782 LOG(4,("CRTC2: enabling cursor\n")); 783 784 /* enable access to secondary head */ 785 set_crtc_owner(1); 786 787 /* b0 = 1 enables cursor */ 788 CRTC2W(CURCTL0, (CRTC2R(CURCTL0) | 0x01)); 789 790 /* workaround for hardware bug confirmed existing on NV43: 791 * Cursor visibility is not updated without a position update if its hardware 792 * retrace sync is enabled. */ 793 if (si->ps.card_arch == NV40A) DAC2W(CURPOS, (DAC2R(CURPOS))); 794 795 return B_OK; 796 } 797 798 status_t nv_crtc2_cursor_hide() 799 { 800 LOG(4,("CRTC2: disabling cursor\n")); 801 802 /* enable access to secondary head */ 803 set_crtc_owner(1); 804 805 /* b0 = 0 disables cursor */ 806 CRTC2W(CURCTL0, (CRTC2R(CURCTL0) & 0xfe)); 807 808 /* workaround for hardware bug confirmed existing on NV43: 809 * Cursor visibility is not updated without a position update if its hardware 810 * retrace sync is enabled. */ 811 if (si->ps.card_arch == NV40A) DAC2W(CURPOS, (DAC2R(CURPOS))); 812 813 return B_OK; 814 } 815 816 /*set up cursor shape*/ 817 status_t nv_crtc2_cursor_define(uint8* andMask,uint8* xorMask) 818 { 819 int x, y; 820 uint8 b; 821 uint16 *cursor; 822 uint16 pixel; 823 824 /* get a pointer to the cursor */ 825 cursor = (uint16*) si->framebuffer; 826 827 /* draw the cursor */ 828 /* (Nvidia cards have a RGB15 direct color cursor bitmap, bit #16 is transparancy) */ 829 for (y = 0; y < 16; y++) 830 { 831 b = 0x80; 832 for (x = 0; x < 8; x++) 833 { 834 /* preset transparant */ 835 pixel = 0x0000; 836 /* set white if requested */ 837 if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; 838 /* set black if requested */ 839 if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; 840 /* set invert if requested */ 841 if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; 842 /* place the pixel in the bitmap */ 843 cursor[x + (y * 32)] = pixel; 844 b >>= 1; 845 } 846 xorMask++; 847 andMask++; 848 b = 0x80; 849 for (; x < 16; x++) 850 { 851 /* preset transparant */ 852 pixel = 0x0000; 853 /* set white if requested */ 854 if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; 855 /* set black if requested */ 856 if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; 857 /* set invert if requested */ 858 if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; 859 /* place the pixel in the bitmap */ 860 cursor[x + (y * 32)] = pixel; 861 b >>= 1; 862 } 863 xorMask++; 864 andMask++; 865 } 866 867 return B_OK; 868 } 869 870 /* position the cursor */ 871 status_t nv_crtc2_cursor_position(uint16 x, uint16 y) 872 { 873 /* the cursor position is updated during retrace by card hardware */ 874 875 /* update cursorposition */ 876 DAC2W(CURPOS, ((x & 0x0fff) | ((y & 0x0fff) << 16))); 877 878 return B_OK; 879 } 880 881 status_t nv_crtc2_stop_tvout(void) 882 { 883 uint16 cnt; 884 885 LOG(4,("CRTC2: stopping TV output\n")); 886 887 /* enable access to secondary head */ 888 set_crtc_owner(1); 889 890 /* just to be sure Vsync is _really_ enabled */ 891 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xbf)); 892 893 /* wait for one image to be generated to make sure VGA has kicked in and is 894 * running OK before continuing... 895 * (Kicking in will fail often if we do not wait here) */ 896 /* Note: 897 * The used CRTC's Vsync is required to be enabled here. The DPMS state 898 * programming in the driver makes sure this is the case. 899 * (except for driver startup: see nv_general.c.) */ 900 901 /* make sure we are 'in' active VGA picture: wait with timeout! */ 902 cnt = 1; 903 while ((NV_REG8(NV8_INSTAT1) & 0x08) && cnt) 904 { 905 snooze(1); 906 cnt++; 907 } 908 /* wait for next vertical retrace start on VGA: wait with timeout! */ 909 cnt = 1; 910 while ((!(NV_REG8(NV8_INSTAT1) & 0x08)) && cnt) 911 { 912 snooze(1); 913 cnt++; 914 } 915 /* now wait until we are 'in' active VGA picture again: wait with timeout! */ 916 cnt = 1; 917 while ((NV_REG8(NV8_INSTAT1) & 0x08) && cnt) 918 { 919 snooze(1); 920 cnt++; 921 } 922 923 /* set CRTC to master mode (b7 = 0) if it wasn't slaved for a panel before */ 924 if (!(si->ps.slaved_tmds2)) CRTC2W(PIXEL, (CRTC2R(PIXEL) & 0x03)); 925 926 /* CAUTION: 927 * On old cards, PLLSEL (and TV_SETUP?) cannot be read (sometimes?), but 928 * write actions do succeed ... 929 * This is confirmed for both ISA and PCI access, on NV04 and NV11. */ 930 931 /* setup TVencoder connection */ 932 /* b1-0 = %00: encoder type is SLAVE; 933 * b24 = 1: VIP datapos is b0-7 */ 934 //fixme if needed: setup completely instead of relying on pre-init by BIOS.. 935 //(it seems to work OK on NV04 and NV11 although read reg. doesn't seem to work) 936 DAC2W(TV_SETUP, ((DAC2R(TV_SETUP) & ~0x00000003) | 0x01000000)); 937 938 /* tell GPU to use pixelclock from internal source instead of using TVencoder */ 939 DACW(PLLSEL, 0x30000f00); 940 941 /* HTOTAL, VTOTAL and OVERFLOW return their default CRTC use, instead of 942 * H, V-low and V-high 'shadow' counters(?)(b0, 4 and 6 = 0) (b7 use = unknown) */ 943 CRTC2W(TREG, 0x00); 944 945 /* select panel encoder, not TV encoder if needed (b0 = 1). 946 * Note: 947 * Both are devices (often) using the CRTC in slaved mode. */ 948 if (si->ps.slaved_tmds2) CRTC2W(LCD, (CRTC2R(LCD) | 0x01)); 949 950 return B_OK; 951 } 952 953 status_t nv_crtc2_start_tvout(void) 954 { 955 LOG(4,("CRTC2: starting TV output\n")); 956 957 /* switch TV encoder to CRTC2 */ 958 NV_REG32(NV32_FUNCSEL) &= ~0x00000100; 959 NV_REG32(NV32_2FUNCSEL) |= 0x00000100; 960 961 /* enable access to secondary head */ 962 set_crtc_owner(1); 963 964 /* CAUTION: 965 * On old cards, PLLSEL (and TV_SETUP?) cannot be read (sometimes?), but 966 * write actions do succeed ... 967 * This is confirmed for both ISA and PCI access, on NV04 and NV11. */ 968 969 /* setup TVencoder connection */ 970 /* b1-0 = %01: encoder type is MASTER; 971 * b24 = 1: VIP datapos is b0-7 */ 972 //fixme if needed: setup completely instead of relying on pre-init by BIOS.. 973 //(it seems to work OK on NV04 and NV11 although read reg. doesn't seem to work) 974 DAC2W(TV_SETUP, ((DAC2R(TV_SETUP) & ~0x00000002) | 0x01000001)); 975 976 /* tell GPU to use pixelclock from TVencoder instead of using internal source */ 977 /* (nessecary or display will 'shiver' on both TV and VGA.) */ 978 DACW(PLLSEL, 0x100c0f00); 979 980 /* Set overscan color to 'black' */ 981 /* note: 982 * Change this instruction for a visible overscan color if you're trying to 983 * center the output on TV. Use it as a guide-'line' then ;-) */ 984 ATB2W(OSCANCOLOR, 0x00); 985 986 /* set CRTC to slaved mode (b7 = 1) and clear TVadjust (b3-5 = %000) */ 987 CRTC2W(PIXEL, ((CRTC2R(PIXEL) & 0xc7) | 0x80)); 988 /* select TV encoder, not panel encoder (b0 = 0). 989 * Note: 990 * Both are devices (often) using the CRTC in slaved mode. */ 991 CRTC2W(LCD, (CRTC2R(LCD) & 0xfe)); 992 993 /* HTOTAL, VTOTAL and OVERFLOW return their default CRTC use, instead of 994 * H, V-low and V-high 'shadow' counters(?)(b0, 4 and 6 = 0) (b7 use = unknown) */ 995 CRTC2W(TREG, 0x80); 996 997 return B_OK; 998 } 999