1 /* second CTRC functionality for GeForce cards */ 2 /* Author: 3 Rudolf Cornelissen 11/2002-5/2004 4 */ 5 6 #define MODULE_BIT 0x00020000 7 8 #include "nv_std.h" 9 10 /*Adjust passed parameters to a valid mode line*/ 11 status_t nv_crtc2_validate_timing( 12 uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht, 13 uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt 14 ) 15 { 16 /* horizontal */ 17 /* make all parameters multiples of 8 */ 18 *hd_e &= 0xfff8; 19 *hs_s &= 0xfff8; 20 *hs_e &= 0xfff8; 21 *ht &= 0xfff8; 22 23 /* confine to required number of bits, taking logic into account */ 24 if (*hd_e > ((0x01ff - 2) << 3)) *hd_e = ((0x01ff - 2) << 3); 25 if (*hs_s > ((0x01ff - 1) << 3)) *hs_s = ((0x01ff - 1) << 3); 26 if (*hs_e > ( 0x01ff << 3)) *hs_e = ( 0x01ff << 3); 27 if (*ht > ((0x01ff + 5) << 3)) *ht = ((0x01ff + 5) << 3); 28 29 /* NOTE: keep horizontal timing at multiples of 8! */ 30 /* confine to a reasonable width */ 31 if (*hd_e < 640) *hd_e = 640; 32 if (*hd_e > 2048) *hd_e = 2048; 33 34 /* if hor. total does not leave room for a sensible sync pulse, increase it! */ 35 if (*ht < (*hd_e + 80)) *ht = (*hd_e + 80); 36 37 /* make sure sync pulse is not during display */ 38 if (*hs_e > (*ht - 8)) *hs_e = (*ht - 8); 39 if (*hs_s < (*hd_e + 8)) *hs_s = (*hd_e + 8); 40 41 /* correct sync pulse if it is too long: 42 * there are only 5 bits available to save this in the card registers! */ 43 if (*hs_e > (*hs_s + 0xf8)) *hs_e = (*hs_s + 0xf8); 44 45 /*vertical*/ 46 /* confine to required number of bits, taking logic into account */ 47 //fixme if needed: on GeForce cards there are 12 instead of 11 bits... 48 if (*vd_e > (0x7ff - 2)) *vd_e = (0x7ff - 2); 49 if (*vs_s > (0x7ff - 1)) *vs_s = (0x7ff - 1); 50 if (*vs_e > 0x7ff ) *vs_e = 0x7ff ; 51 if (*vt > (0x7ff + 2)) *vt = (0x7ff + 2); 52 53 /* confine to a reasonable height */ 54 if (*vd_e < 480) *vd_e = 480; 55 if (*vd_e > 1536) *vd_e = 1536; 56 57 /*if vertical total does not leave room for a sync pulse, increase it!*/ 58 if (*vt < (*vd_e + 3)) *vt = (*vd_e + 3); 59 60 /* make sure sync pulse is not during display */ 61 if (*vs_e > (*vt - 1)) *vs_e = (*vt - 1); 62 if (*vs_s < (*vd_e + 1)) *vs_s = (*vd_e + 1); 63 64 /* correct sync pulse if it is too long: 65 * there are only 4 bits available to save this in the card registers! */ 66 if (*vs_e > (*vs_s + 0x0f)) *vs_e = (*vs_s + 0x0f); 67 68 return B_OK; 69 } 70 71 /*set a mode line - inputs are in pixels*/ 72 status_t nv_crtc2_set_timing(display_mode target) 73 { 74 uint8 temp; 75 76 uint32 htotal; /*total horizontal total VCLKs*/ 77 uint32 hdisp_e; /*end of horizontal display (begins at 0)*/ 78 uint32 hsync_s; /*begin of horizontal sync pulse*/ 79 uint32 hsync_e; /*end of horizontal sync pulse*/ 80 uint32 hblnk_s; /*begin horizontal blanking*/ 81 uint32 hblnk_e; /*end horizontal blanking*/ 82 83 uint32 vtotal; /*total vertical total scanlines*/ 84 uint32 vdisp_e; /*end of vertical display*/ 85 uint32 vsync_s; /*begin of vertical sync pulse*/ 86 uint32 vsync_e; /*end of vertical sync pulse*/ 87 uint32 vblnk_s; /*begin vertical blanking*/ 88 uint32 vblnk_e; /*end vertical blanking*/ 89 90 uint32 linecomp; /*split screen and vdisp_e interrupt*/ 91 92 LOG(4,("CRTC2: setting timing\n")); 93 94 /* setup tuned internal modeline for flatpanel if connected and active */ 95 if (si->ps.tmds2_active) 96 { 97 LOG(2,("CRTC2: DFP active: tuning modeline\n")); 98 99 /* horizontal timing */ 100 //testing (640x480): total = 135% is too much, 120% to small... 101 //total = display + 160 equals panel modeline: but must be smaller...? 102 // target.timing.h_total = target.timing.h_display + 152;//160;//128 103 // target.timing.h_sync_start = target.timing.h_total - 136;//144;//112 104 // target.timing.h_sync_end = target.timing.h_total - 40;//48;//16 105 //adaptive to panel: fixme: test on 4:3 and 16:10 panels! 106 target.timing.h_sync_start = 107 ((uint16)((si->ps.p2_timing.h_sync_start / ((float)si->ps.p2_timing.h_display)) * 108 target.timing.h_display)) & 0xfff8; 109 110 target.timing.h_sync_end = 111 ((uint16)((si->ps.p2_timing.h_sync_end / ((float)si->ps.p2_timing.h_display)) * 112 target.timing.h_display)) & 0xfff8; 113 114 target.timing.h_total = 115 (((uint16)((si->ps.p2_timing.h_total / ((float)si->ps.p2_timing.h_display)) * 116 target.timing.h_display)) & 0xfff8) - 8; 117 118 if (target.timing.h_sync_start == target.timing.h_display) 119 target.timing.h_sync_start += 8; 120 if (target.timing.h_sync_end == target.timing.h_total) 121 target.timing.h_sync_end -= 8; 122 123 /* vertical timing */ 124 // target.timing.v_total = target.timing.v_display + 6; 125 // target.timing.v_sync_start = target.timing.v_total - 3; 126 // target.timing.v_sync_end = target.timing.v_total - 2; 127 target.timing.v_sync_start = 128 ((uint16)((si->ps.p2_timing.v_sync_start / ((float)si->ps.p2_timing.v_display)) * 129 target.timing.v_display)); 130 131 target.timing.v_sync_end = 132 ((uint16)((si->ps.p2_timing.v_sync_end / ((float)si->ps.p2_timing.v_display)) * 133 target.timing.v_display)); 134 135 target.timing.v_total = 136 ((uint16)((si->ps.p2_timing.v_total / ((float)si->ps.p2_timing.v_display)) * 137 target.timing.v_display)) - 1; 138 139 if (target.timing.v_sync_start == target.timing.v_display) 140 target.timing.v_sync_start += 1; 141 if (target.timing.v_sync_end == target.timing.v_total) 142 target.timing.v_sync_end -= 1; 143 144 /* disable GPU scaling testmode so automatic scaling will be done */ 145 DAC2W(FP_DEBUG1, 0); 146 } 147 148 /* Modify parameters as required by standard VGA */ 149 htotal = ((target.timing.h_total >> 3) - 5); 150 hdisp_e = ((target.timing.h_display >> 3) - 1); 151 hblnk_s = hdisp_e; 152 hblnk_e = (htotal + 4);//0; 153 hsync_s = (target.timing.h_sync_start >> 3); 154 hsync_e = (target.timing.h_sync_end >> 3); 155 156 vtotal = target.timing.v_total - 2; 157 vdisp_e = target.timing.v_display - 1; 158 vblnk_s = vdisp_e; 159 vblnk_e = (vtotal + 1); 160 vsync_s = target.timing.v_sync_start;//-1; 161 vsync_e = target.timing.v_sync_end;//-1; 162 163 /* prevent memory adress counter from being reset (linecomp may not occur) */ 164 linecomp = target.timing.v_display; 165 166 /* enable access to secondary head */ 167 set_crtc_owner(1); 168 169 /* Note for laptop and DVI flatpanels: 170 * CRTC timing has a seperate set of registers from flatpanel timing. 171 * The flatpanel timing registers have scaling registers that are used to match 172 * these two modelines. */ 173 { 174 LOG(4,("CRTC2: Setting full timing...\n")); 175 176 /* log the mode that will be set */ 177 LOG(2,("CRTC2:\n\tHTOT:%x\n\tHDISPEND:%x\n\tHBLNKS:%x\n\tHBLNKE:%x\n\tHSYNCS:%x\n\tHSYNCE:%x\n\t",htotal,hdisp_e,hblnk_s,hblnk_e,hsync_s,hsync_e)); 178 LOG(2,("VTOT:%x\n\tVDISPEND:%x\n\tVBLNKS:%x\n\tVBLNKE:%x\n\tVSYNCS:%x\n\tVSYNCE:%x\n",vtotal,vdisp_e,vblnk_s,vblnk_e,vsync_s,vsync_e)); 179 180 /* actually program the card! */ 181 /* unlock CRTC registers at index 0-7 */ 182 CRTC2W(VSYNCE, (CRTC2R(VSYNCE) & 0x7f)); 183 /* horizontal standard VGA regs */ 184 CRTC2W(HTOTAL, (htotal & 0xff)); 185 CRTC2W(HDISPE, (hdisp_e & 0xff)); 186 CRTC2W(HBLANKS, (hblnk_s & 0xff)); 187 /* also unlock vertical retrace registers in advance */ 188 CRTC2W(HBLANKE, ((hblnk_e & 0x1f) | 0x80)); 189 CRTC2W(HSYNCS, (hsync_s & 0xff)); 190 CRTC2W(HSYNCE, ((hsync_e & 0x1f) | ((hblnk_e & 0x20) << 2))); 191 192 /* vertical standard VGA regs */ 193 CRTC2W(VTOTAL, (vtotal & 0xff)); 194 CRTC2W(OVERFLOW, 195 ( 196 ((vtotal & 0x100) >> (8 - 0)) | ((vtotal & 0x200) >> (9 - 5)) | 197 ((vdisp_e & 0x100) >> (8 - 1)) | ((vdisp_e & 0x200) >> (9 - 6)) | 198 ((vsync_s & 0x100) >> (8 - 2)) | ((vsync_s & 0x200) >> (9 - 7)) | 199 ((vblnk_s & 0x100) >> (8 - 3)) | ((linecomp & 0x100) >> (8 - 4)) 200 )); 201 CRTC2W(PRROWSCN, 0x00); /* not used */ 202 CRTC2W(MAXSCLIN, (((vblnk_s & 0x200) >> (9 - 5)) | ((linecomp & 0x200) >> (9 - 6)))); 203 CRTC2W(VSYNCS, (vsync_s & 0xff)); 204 CRTC2W(VSYNCE, ((CRTC2R(VSYNCE) & 0xf0) | (vsync_e & 0x0f))); 205 CRTC2W(VDISPE, (vdisp_e & 0xff)); 206 CRTC2W(VBLANKS, (vblnk_s & 0xff)); 207 CRTC2W(VBLANKE, (vblnk_e & 0xff)); 208 CRTC2W(LINECOMP, (linecomp & 0xff)); 209 210 /* horizontal extended regs */ 211 //fixme: we reset bit4. is this correct?? 212 CRTC2W(HEB, (CRTC2R(HEB) & 0xe0) | 213 ( 214 ((htotal & 0x100) >> (8 - 0)) | 215 ((hdisp_e & 0x100) >> (8 - 1)) | 216 ((hblnk_s & 0x100) >> (8 - 2)) | 217 ((hsync_s & 0x100) >> (8 - 3)) 218 )); 219 220 /* (mostly) vertical extended regs */ 221 CRTC2W(LSR, 222 ( 223 ((vtotal & 0x400) >> (10 - 0)) | 224 ((vdisp_e & 0x400) >> (10 - 1)) | 225 ((vsync_s & 0x400) >> (10 - 2)) | 226 ((vblnk_s & 0x400) >> (10 - 3)) | 227 ((hblnk_e & 0x040) >> (6 - 4)) 228 //fixme: we still miss one linecomp bit!?! is this it?? 229 //| ((linecomp & 0x400) >> 3) 230 )); 231 232 /* more vertical extended regs */ 233 CRTC2W(EXTRA, 234 ( 235 ((vtotal & 0x800) >> (11 - 0)) | 236 ((vdisp_e & 0x800) >> (11 - 2)) | 237 ((vsync_s & 0x800) >> (11 - 4)) | 238 ((vblnk_s & 0x800) >> (11 - 6)) 239 //fixme: do we miss another linecomp bit!?! 240 )); 241 242 /* setup 'large screen' mode */ 243 if (target.timing.h_display >= 1280) 244 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xfb)); 245 else 246 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x04)); 247 248 /* setup HSYNC & VSYNC polarity */ 249 LOG(2,("CRTC2: sync polarity: ")); 250 temp = NV_REG8(NV8_MISCR); 251 if (target.timing.flags & B_POSITIVE_HSYNC) 252 { 253 LOG(2,("H:pos ")); 254 temp &= ~0x40; 255 } 256 else 257 { 258 LOG(2,("H:neg ")); 259 temp |= 0x40; 260 } 261 if (target.timing.flags & B_POSITIVE_VSYNC) 262 { 263 LOG(2,("V:pos ")); 264 temp &= ~0x80; 265 } 266 else 267 { 268 LOG(2,("V:neg ")); 269 temp |= 0x80; 270 } 271 NV_REG8(NV8_MISCW) = temp; 272 273 LOG(2,(", MISC reg readback: $%02x\n", NV_REG8(NV8_MISCR))); 274 } 275 276 /* always disable interlaced operation */ 277 /* (interlace is supported on upto and including NV10, NV15, and NV30 and up) */ 278 CRTC2W(INTERLACE, 0xff); 279 280 /* setup flatpanel if connected and active */ 281 if (si->ps.tmds2_active) 282 { 283 uint32 iscale_x, iscale_y; 284 285 /* calculate inverse scaling factors used by hardware in 20.12 format */ 286 iscale_x = (((1 << 12) * target.timing.h_display) / si->ps.p2_timing.h_display); 287 iscale_y = (((1 << 12) * target.timing.v_display) / si->ps.p2_timing.v_display); 288 289 /* unblock flatpanel timing programming (or something like that..) */ 290 CRTC2W(FP_HTIMING, 0); 291 CRTC2W(FP_VTIMING, 0); 292 LOG(2,("CRTC2: FP_HTIMING reg readback: $%02x\n", CRTC2R(FP_HTIMING))); 293 LOG(2,("CRTC2: FP_VTIMING reg readback: $%02x\n", CRTC2R(FP_VTIMING))); 294 295 /* enable full width visibility on flatpanel */ 296 DAC2W(FP_HVALID_S, 0); 297 DAC2W(FP_HVALID_E, (si->ps.p2_timing.h_display - 1)); 298 /* enable full height visibility on flatpanel */ 299 DAC2W(FP_VVALID_S, 0); 300 DAC2W(FP_VVALID_E, (si->ps.p2_timing.v_display - 1)); 301 302 /* nVidia cards support upscaling except on ??? */ 303 /* NV11 cards can upscale after all! */ 304 if (0)//si->ps.card_type == NV11) 305 { 306 /* disable last fetched line limiting */ 307 DAC2W(FP_DEBUG2, 0x00000000); 308 /* inform panel to scale if needed */ 309 if ((iscale_x != (1 << 12)) || (iscale_y != (1 << 12))) 310 { 311 LOG(2,("CRTC2: DFP needs to do scaling\n")); 312 DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) | 0x00000100)); 313 } 314 else 315 { 316 LOG(2,("CRTC2: no scaling for DFP needed\n")); 317 DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) & 0xfffffeff)); 318 } 319 } 320 else 321 { 322 float dm_aspect; 323 324 LOG(2,("CRTC2: GPU scales for DFP if needed\n")); 325 326 /* calculate display mode aspect */ 327 dm_aspect = (target.timing.h_display / ((float)target.timing.v_display)); 328 329 /* limit last fetched line if vertical scaling is done */ 330 if (iscale_y != (1 << 12)) 331 DAC2W(FP_DEBUG2, ((1 << 28) | ((target.timing.v_display - 1) << 16))); 332 else 333 DAC2W(FP_DEBUG2, 0x00000000); 334 335 /* inform panel not to scale */ 336 DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) & 0xfffffeff)); 337 338 /* GPU scaling is automatically setup by hardware, so only modify this 339 * scalingfactor for non 4:3 (1.33) aspect panels; 340 * let's consider 1280x1024 1:33 aspect (it's 1.25 aspect actually!) */ 341 342 /* correct for widescreen panels relative to mode... 343 * (so if panel is more widescreen than mode being set) */ 344 /* BTW: known widescreen panels: 345 * 1280 x 800 (1.60), 346 * 1440 x 900 (1.60), 347 * 1680 x 1050 (1.60), 348 * 1920 x 1200 (1.60). */ 349 /* known 4:3 aspect non-standard resolution panels: 350 * 1400 x 1050 (1.33). */ 351 /* NOTE: 352 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */ 353 if ((iscale_x != (1 << 12)) && (si->ps.panel2_aspect > (dm_aspect + 0.10))) 354 { 355 uint16 diff; 356 357 LOG(2,("CRTC2: (relative) widescreen panel: tuning horizontal scaling\n")); 358 359 /* X-scaling should be the same as Y-scaling */ 360 iscale_x = iscale_y; 361 /* enable testmode (b12) and program new X-scaling factor */ 362 DAC2W(FP_DEBUG1, (((iscale_x >> 1) & 0x00000fff) | (1 << 12))); 363 /* center/cut-off left and right side of screen */ 364 diff = ((si->ps.p2_timing.h_display - 365 (target.timing.h_display * ((1 << 12) / ((float)iscale_x)))) 366 / 2); 367 DAC2W(FP_HVALID_S, diff); 368 DAC2W(FP_HVALID_E, ((si->ps.p2_timing.h_display - diff) - 1)); 369 } 370 /* correct for portrait panels... */ 371 /* NOTE: 372 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */ 373 if ((iscale_y != (1 << 12)) && (si->ps.panel2_aspect < (dm_aspect - 0.10))) 374 { 375 LOG(2,("CRTC2: (relative) portrait panel: should tune vertical scaling\n")); 376 /* fixme: implement if this kind of portrait panels exist on nVidia... */ 377 } 378 } 379 380 /* do some logging.. */ 381 LOG(2,("CRTC2: FP_HVALID_S reg readback: $%08x\n", DAC2R(FP_HVALID_S))); 382 LOG(2,("CRTC2: FP_HVALID_E reg readback: $%08x\n", DAC2R(FP_HVALID_E))); 383 LOG(2,("CRTC2: FP_VVALID_S reg readback: $%08x\n", DAC2R(FP_VVALID_S))); 384 LOG(2,("CRTC2: FP_VVALID_E reg readback: $%08x\n", DAC2R(FP_VVALID_E))); 385 LOG(2,("CRTC2: FP_DEBUG0 reg readback: $%08x\n", DAC2R(FP_DEBUG0))); 386 LOG(2,("CRTC2: FP_DEBUG1 reg readback: $%08x\n", DAC2R(FP_DEBUG1))); 387 LOG(2,("CRTC2: FP_DEBUG2 reg readback: $%08x\n", DAC2R(FP_DEBUG2))); 388 LOG(2,("CRTC2: FP_DEBUG3 reg readback: $%08x\n", DAC2R(FP_DEBUG3))); 389 LOG(2,("CRTC2: FP_TG_CTRL reg readback: $%08x\n", DAC2R(FP_TG_CTRL))); 390 } 391 392 return B_OK; 393 } 394 395 status_t nv_crtc2_depth(int mode) 396 { 397 uint8 viddelay = 0; 398 uint32 genctrl = 0; 399 400 /* set VCLK scaling */ 401 switch(mode) 402 { 403 case BPP8: 404 viddelay = 0x01; 405 /* genctrl b4 & b5 reset: 'direct mode' */ 406 genctrl = 0x00101100; 407 break; 408 case BPP15: 409 viddelay = 0x02; 410 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 411 genctrl = 0x00100130; 412 break; 413 case BPP16: 414 viddelay = 0x02; 415 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 416 genctrl = 0x00101130; 417 break; 418 case BPP24: 419 viddelay = 0x03; 420 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 421 genctrl = 0x00100130; 422 break; 423 case BPP32: 424 viddelay = 0x03; 425 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 426 genctrl = 0x00101130; 427 break; 428 } 429 /* enable access to secondary head */ 430 set_crtc_owner(1); 431 432 CRTC2W(PIXEL, ((CRTC2R(PIXEL) & 0xfc) | viddelay)); 433 DAC2W(GENCTRL, genctrl); 434 435 return B_OK; 436 } 437 438 status_t nv_crtc2_dpms(bool display, bool h, bool v) 439 { 440 uint8 temp; 441 442 LOG(4,("CRTC2: setting DPMS: ")); 443 444 /* enable access to secondary head */ 445 set_crtc_owner(1); 446 447 /* start synchronous reset: required before turning screen off! */ 448 SEQW(RESET, 0x01); 449 450 /* turn screen off */ 451 temp = SEQR(CLKMODE); 452 if (display) 453 { 454 SEQW(CLKMODE, (temp & ~0x20)); 455 456 /* end synchronous reset if display should be enabled */ 457 SEQW(RESET, 0x03); 458 459 //'safe mode' test! feedback needed with this 'setting'! 460 if (0)//si->ps.tmds2_active) 461 { 462 /* powerup both LVDS (laptop panellink) and TMDS (DVI panellink) 463 * internal transmitters... */ 464 /* note: 465 * the powerbits in this register are hardwired to the DVI connectors, 466 * instead of to the DACs! (confirmed NV34) */ 467 //fixme... 468 DAC2W(FP_DEBUG0, (DAC2R(FP_DEBUG0) & 0xcfffffff)); 469 /* ... and powerup external TMDS transmitter if it exists */ 470 /* (confirmed OK on NV28 and NV34) */ 471 CRTC2W(0x59, (CRTC2R(0x59) | 0x01)); 472 } 473 474 LOG(4,("display on, ")); 475 } 476 else 477 { 478 SEQW(CLKMODE, (temp | 0x20)); 479 480 //'safe mode' test! feedback needed with this 'setting'! 481 if (0)//si->ps.tmds2_active) 482 { 483 /* powerdown both LVDS (laptop panellink) and TMDS (DVI panellink) 484 * internal transmitters... */ 485 /* note: 486 * the powerbits in this register are hardwired to the DVI connectors, 487 * instead of to the DACs! (confirmed NV34) */ 488 //fixme... 489 DAC2W(FP_DEBUG0, (DAC2R(FP_DEBUG0) | 0x30000000)); 490 /* ... and powerdown external TMDS transmitter if it exists */ 491 /* (confirmed OK on NV28 and NV34) */ 492 CRTC2W(0x59, (CRTC2R(0x59) & 0xfe)); 493 } 494 495 LOG(4,("display off, ")); 496 } 497 498 if (h) 499 { 500 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0x7f)); 501 LOG(4,("hsync enabled, ")); 502 } 503 else 504 { 505 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x80)); 506 LOG(4,("hsync disabled, ")); 507 } 508 if (v) 509 { 510 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xbf)); 511 LOG(4,("vsync enabled\n")); 512 } 513 else 514 { 515 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x40)); 516 LOG(4,("vsync disabled\n")); 517 } 518 519 return B_OK; 520 } 521 522 status_t nv_crtc2_dpms_fetch(bool *display, bool *h, bool *v) 523 { 524 /* enable access to secondary head */ 525 set_crtc_owner(1); 526 527 *display = !(SEQR(CLKMODE) & 0x20); 528 *h = !(CRTC2R(REPAINT1) & 0x80); 529 *v = !(CRTC2R(REPAINT1) & 0x40); 530 531 LOG(4,("CTRC2: fetched DPMS state:")); 532 if (display) LOG(4,("display on, ")); 533 else LOG(4,("display off, ")); 534 if (h) LOG(4,("hsync enabled, ")); 535 else LOG(4,("hsync disabled, ")); 536 if (v) LOG(4,("vsync enabled\n")); 537 else LOG(4,("vsync disabled\n")); 538 539 return B_OK; 540 } 541 542 status_t nv_crtc2_set_display_pitch() 543 { 544 uint32 offset; 545 546 LOG(4,("CRTC2: setting card pitch (offset between lines)\n")); 547 548 /* figure out offset value hardware needs */ 549 offset = si->fbc.bytes_per_row / 8; 550 551 LOG(2,("CRTC2: offset register set to: $%04x\n", offset)); 552 553 /* enable access to secondary head */ 554 set_crtc_owner(1); 555 556 /* program the card */ 557 CRTC2W(PITCHL, (offset & 0x00ff)); 558 CRTC2W(REPAINT0, ((CRTC2R(REPAINT0) & 0x1f) | ((offset & 0x0700) >> 3))); 559 560 return B_OK; 561 } 562 563 status_t nv_crtc2_set_display_start(uint32 startadd,uint8 bpp) 564 { 565 uint32 timeout = 0; 566 567 LOG(4,("CRTC2: setting card RAM to be displayed bpp %d\n", bpp)); 568 569 LOG(2,("CRTC2: startadd: $%08x\n", startadd)); 570 LOG(2,("CRTC2: frameRAM: $%08x\n", si->framebuffer)); 571 LOG(2,("CRTC2: framebuffer: $%08x\n", si->fbc.frame_buffer)); 572 573 /* we might have no retraces during setmode! */ 574 /* wait 25mS max. for retrace to occur (refresh > 40Hz) */ 575 while (((NV_REG32(NV32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) && 576 (timeout < (25000/10))) 577 { 578 /* don't snooze much longer or retrace might get missed! */ 579 snooze(10); 580 timeout++; 581 } 582 583 /* enable access to secondary head */ 584 set_crtc_owner(1); 585 586 /* upto 4Gb RAM adressing: must be used on NV10 and later! */ 587 /* NOTE: 588 * While this register also exists on pre-NV10 cards, it will 589 * wrap-around at 16Mb boundaries!! */ 590 591 /* 30bit adress in 32bit words */ 592 NV_REG32(NV32_NV10FB2STADD32) = (startadd & 0xfffffffc); 593 594 /* set byte adress: (b0 - 1) */ 595 ATB2W(HORPIXPAN, ((startadd & 0x00000003) << 1)); 596 597 return B_OK; 598 } 599 600 status_t nv_crtc2_cursor_init() 601 { 602 int i; 603 uint32 * fb; 604 /* cursor bitmap will be stored at the start of the framebuffer */ 605 const uint32 curadd = 0; 606 607 /* enable access to secondary head */ 608 set_crtc_owner(1); 609 610 /* set cursor bitmap adress ... */ 611 if (si->ps.laptop) 612 { 613 /* must be used this way on pre-NV10 and on all 'Go' cards! */ 614 615 /* cursorbitmap must start on 2Kbyte boundary: */ 616 /* set adress bit11-16, and set 'no doublescan' (registerbit 1 = 0) */ 617 CRTC2W(CURCTL0, ((curadd & 0x0001f800) >> 9)); 618 /* set adress bit17-23, and set graphics mode cursor(?) (registerbit 7 = 1) */ 619 CRTC2W(CURCTL1, (((curadd & 0x00fe0000) >> 17) | 0x80)); 620 /* set adress bit24-31 */ 621 CRTC2W(CURCTL2, ((curadd & 0xff000000) >> 24)); 622 } 623 else 624 { 625 /* upto 4Gb RAM adressing: 626 * can be used on NV10 and later (except for 'Go' cards)! */ 627 /* NOTE: 628 * This register does not exist on pre-NV10 and 'Go' cards. */ 629 630 /* cursorbitmap must still start on 2Kbyte boundary: */ 631 NV_REG32(NV32_NV10CUR2ADD32) = (curadd & 0xfffff800); 632 } 633 634 /* set cursor colour: not needed because of direct nature of cursor bitmap. */ 635 636 /*clear cursor*/ 637 fb = (uint32 *) si->framebuffer + curadd; 638 for (i=0;i<(2048/4);i++) 639 { 640 fb[i]=0; 641 } 642 643 /* select 32x32 pixel, 16bit color cursorbitmap, no doublescan */ 644 NV_REG32(NV32_2CURCONF) = 0x02000100; 645 646 /* activate hardware cursor */ 647 nv_crtc2_cursor_show(); 648 649 return B_OK; 650 } 651 652 status_t nv_crtc2_cursor_show() 653 { 654 LOG(4,("CRTC2: enabling cursor\n")); 655 656 /* enable access to secondary head */ 657 set_crtc_owner(1); 658 659 /* b0 = 1 enables cursor */ 660 CRTC2W(CURCTL0, (CRTC2R(CURCTL0) | 0x01)); 661 662 return B_OK; 663 } 664 665 status_t nv_crtc2_cursor_hide() 666 { 667 LOG(4,("CRTC2: disabling cursor\n")); 668 669 /* enable access to secondary head */ 670 set_crtc_owner(1); 671 672 /* b0 = 0 disables cursor */ 673 CRTC2W(CURCTL0, (CRTC2R(CURCTL0) & 0xfe)); 674 675 return B_OK; 676 } 677 678 /*set up cursor shape*/ 679 status_t nv_crtc2_cursor_define(uint8* andMask,uint8* xorMask) 680 { 681 int x, y; 682 uint8 b; 683 uint16 *cursor; 684 uint16 pixel; 685 686 /* get a pointer to the cursor */ 687 cursor = (uint16*) si->framebuffer; 688 689 /* draw the cursor */ 690 /* (Nvidia cards have a RGB15 direct color cursor bitmap, bit #16 is transparancy) */ 691 for (y = 0; y < 16; y++) 692 { 693 b = 0x80; 694 for (x = 0; x < 8; x++) 695 { 696 /* preset transparant */ 697 pixel = 0x0000; 698 /* set white if requested */ 699 if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; 700 /* set black if requested */ 701 if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; 702 /* set invert if requested */ 703 if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; 704 /* place the pixel in the bitmap */ 705 cursor[x + (y * 32)] = pixel; 706 b >>= 1; 707 } 708 xorMask++; 709 andMask++; 710 b = 0x80; 711 for (; x < 16; x++) 712 { 713 /* preset transparant */ 714 pixel = 0x0000; 715 /* set white if requested */ 716 if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; 717 /* set black if requested */ 718 if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; 719 /* set invert if requested */ 720 if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; 721 /* place the pixel in the bitmap */ 722 cursor[x + (y * 32)] = pixel; 723 b >>= 1; 724 } 725 xorMask++; 726 andMask++; 727 } 728 729 return B_OK; 730 } 731 732 /* position the cursor */ 733 status_t nv_crtc2_cursor_position(uint16 x, uint16 y) 734 { 735 uint16 yhigh; 736 737 /* make sure we are beyond the first line of the cursorbitmap being drawn during 738 * updating the position to prevent distortions: no double buffering feature */ 739 /* Note: 740 * we need to return as quick as possible or some apps will exhibit lagging.. */ 741 742 /* read the old cursor Y position */ 743 yhigh = ((DAC2R(CURPOS) & 0x0fff0000) >> 16); 744 /* make sure we will wait until we are below both the old and new Y position: 745 * visible cursorbitmap drawing needs to be done at least... */ 746 if (y > yhigh) yhigh = y; 747 748 if (yhigh < (si->dm.timing.v_display - 16)) 749 { 750 /* we have vertical lines below old and new cursorposition to spare. So we 751 * update the cursor postion 'mid-screen', but below that area. */ 752 while (((uint16)(NV_REG32(NV32_RASTER2) & 0x000007ff)) < (yhigh + 16)) 753 { 754 snooze(10); 755 } 756 } 757 else 758 { 759 /* no room to spare, just wait for retrace (is relatively slow) */ 760 while ((NV_REG32(NV32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) 761 { 762 /* don't snooze much longer or retrace might get missed! */ 763 snooze(10); 764 } 765 } 766 767 /* update cursorposition */ 768 DAC2W(CURPOS, ((x & 0x0fff) | ((y & 0x0fff) << 16))); 769 770 return B_OK; 771 } 772