1 /* second CTRC functionality for GeForce cards */ 2 /* Author: 3 Rudolf Cornelissen 11/2002-6/2004 4 */ 5 6 #define MODULE_BIT 0x00020000 7 8 #include "nv_std.h" 9 10 /*Adjust passed parameters to a valid mode line*/ 11 status_t nv_crtc2_validate_timing( 12 uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht, 13 uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt 14 ) 15 { 16 /* horizontal */ 17 /* make all parameters multiples of 8 */ 18 *hd_e &= 0xfff8; 19 *hs_s &= 0xfff8; 20 *hs_e &= 0xfff8; 21 *ht &= 0xfff8; 22 23 /* confine to required number of bits, taking logic into account */ 24 if (*hd_e > ((0x01ff - 2) << 3)) *hd_e = ((0x01ff - 2) << 3); 25 if (*hs_s > ((0x01ff - 1) << 3)) *hs_s = ((0x01ff - 1) << 3); 26 if (*hs_e > ( 0x01ff << 3)) *hs_e = ( 0x01ff << 3); 27 if (*ht > ((0x01ff + 5) << 3)) *ht = ((0x01ff + 5) << 3); 28 29 /* NOTE: keep horizontal timing at multiples of 8! */ 30 /* confine to a reasonable width */ 31 if (*hd_e < 640) *hd_e = 640; 32 if (*hd_e > 2048) *hd_e = 2048; 33 34 /* if hor. total does not leave room for a sensible sync pulse, increase it! */ 35 if (*ht < (*hd_e + 80)) *ht = (*hd_e + 80); 36 37 /* make sure sync pulse is not during display */ 38 if (*hs_e > (*ht - 8)) *hs_e = (*ht - 8); 39 if (*hs_s < (*hd_e + 8)) *hs_s = (*hd_e + 8); 40 41 /* correct sync pulse if it is too long: 42 * there are only 5 bits available to save this in the card registers! */ 43 if (*hs_e > (*hs_s + 0xf8)) *hs_e = (*hs_s + 0xf8); 44 45 /*vertical*/ 46 /* confine to required number of bits, taking logic into account */ 47 //fixme if needed: on GeForce cards there are 12 instead of 11 bits... 48 if (*vd_e > (0x7ff - 2)) *vd_e = (0x7ff - 2); 49 if (*vs_s > (0x7ff - 1)) *vs_s = (0x7ff - 1); 50 if (*vs_e > 0x7ff ) *vs_e = 0x7ff ; 51 if (*vt > (0x7ff + 2)) *vt = (0x7ff + 2); 52 53 /* confine to a reasonable height */ 54 if (*vd_e < 480) *vd_e = 480; 55 if (*vd_e > 1536) *vd_e = 1536; 56 57 /*if vertical total does not leave room for a sync pulse, increase it!*/ 58 if (*vt < (*vd_e + 3)) *vt = (*vd_e + 3); 59 60 /* make sure sync pulse is not during display */ 61 if (*vs_e > (*vt - 1)) *vs_e = (*vt - 1); 62 if (*vs_s < (*vd_e + 1)) *vs_s = (*vd_e + 1); 63 64 /* correct sync pulse if it is too long: 65 * there are only 4 bits available to save this in the card registers! */ 66 if (*vs_e > (*vs_s + 0x0f)) *vs_e = (*vs_s + 0x0f); 67 68 return B_OK; 69 } 70 71 /*set a mode line - inputs are in pixels*/ 72 status_t nv_crtc2_set_timing(display_mode target) 73 { 74 uint8 temp; 75 76 uint32 htotal; /*total horizontal total VCLKs*/ 77 uint32 hdisp_e; /*end of horizontal display (begins at 0)*/ 78 uint32 hsync_s; /*begin of horizontal sync pulse*/ 79 uint32 hsync_e; /*end of horizontal sync pulse*/ 80 uint32 hblnk_s; /*begin horizontal blanking*/ 81 uint32 hblnk_e; /*end horizontal blanking*/ 82 83 uint32 vtotal; /*total vertical total scanlines*/ 84 uint32 vdisp_e; /*end of vertical display*/ 85 uint32 vsync_s; /*begin of vertical sync pulse*/ 86 uint32 vsync_e; /*end of vertical sync pulse*/ 87 uint32 vblnk_s; /*begin vertical blanking*/ 88 uint32 vblnk_e; /*end vertical blanking*/ 89 90 uint32 linecomp; /*split screen and vdisp_e interrupt*/ 91 92 LOG(4,("CRTC2: setting timing\n")); 93 94 /* setup tuned internal modeline for flatpanel if connected and active */ 95 /* notes: 96 * - the CRTC modeline must end earlier than the panel modeline to keep correct 97 * sync going; 98 * - if the CRTC modeline ends too soon, pixelnoise will occur in 8 (or so) pixel 99 * wide horizontal stripes. This can be observed earliest on fullscreen overlay, 100 * and if it gets worse, also normal desktop output will suffer. The stripes 101 * are mainly visible at the left of the screen, over the entire screen height. */ 102 if (si->ps.tmds2_active) 103 { 104 LOG(2,("CRTC2: DFP active: tuning modeline\n")); 105 106 /* horizontal timing */ 107 target.timing.h_sync_start = 108 ((uint16)((si->ps.p2_timing.h_sync_start / ((float)si->ps.p2_timing.h_display)) * 109 target.timing.h_display)) & 0xfff8; 110 111 target.timing.h_sync_end = 112 ((uint16)((si->ps.p2_timing.h_sync_end / ((float)si->ps.p2_timing.h_display)) * 113 target.timing.h_display)) & 0xfff8; 114 115 target.timing.h_total = 116 (((uint16)((si->ps.p2_timing.h_total / ((float)si->ps.p2_timing.h_display)) * 117 target.timing.h_display)) & 0xfff8) - 8; 118 119 //fixme: can be removed if community confirms no problems with modified setup! 120 //(confirmed this 'problem' on NV34 and NV11 now.) 121 /* NV11 timing has tighter constraints than later cards */ 122 // if ((si->ps.card_type == NV11) && 123 // (target.timing.h_display == si->ps.p2_timing.h_display)) 124 125 /* in native mode the CRTC needs some extra time to keep synced correctly */ 126 if (target.timing.h_display == si->ps.p2_timing.h_display) 127 { 128 target.timing.h_total -= 56; 129 } 130 131 if (target.timing.h_sync_start == target.timing.h_display) 132 target.timing.h_sync_start += 8; 133 if (target.timing.h_sync_end == target.timing.h_total) 134 target.timing.h_sync_end -= 8; 135 136 /* vertical timing */ 137 target.timing.v_sync_start = 138 ((uint16)((si->ps.p2_timing.v_sync_start / ((float)si->ps.p2_timing.v_display)) * 139 target.timing.v_display)); 140 141 target.timing.v_sync_end = 142 ((uint16)((si->ps.p2_timing.v_sync_end / ((float)si->ps.p2_timing.v_display)) * 143 target.timing.v_display)); 144 145 target.timing.v_total = 146 ((uint16)((si->ps.p2_timing.v_total / ((float)si->ps.p2_timing.v_display)) * 147 target.timing.v_display)) - 1; 148 149 if (target.timing.v_sync_start == target.timing.v_display) 150 target.timing.v_sync_start += 1; 151 if (target.timing.v_sync_end == target.timing.v_total) 152 target.timing.v_sync_end -= 1; 153 154 /* disable GPU scaling testmode so automatic scaling will be done */ 155 DAC2W(FP_DEBUG1, 0); 156 } 157 158 /* Modify parameters as required by standard VGA */ 159 htotal = ((target.timing.h_total >> 3) - 5); 160 hdisp_e = ((target.timing.h_display >> 3) - 1); 161 hblnk_s = hdisp_e; 162 hblnk_e = (htotal + 4);//0; 163 hsync_s = (target.timing.h_sync_start >> 3); 164 hsync_e = (target.timing.h_sync_end >> 3); 165 166 vtotal = target.timing.v_total - 2; 167 vdisp_e = target.timing.v_display - 1; 168 vblnk_s = vdisp_e; 169 vblnk_e = (vtotal + 1); 170 vsync_s = target.timing.v_sync_start;//-1; 171 vsync_e = target.timing.v_sync_end;//-1; 172 173 /* prevent memory adress counter from being reset (linecomp may not occur) */ 174 linecomp = target.timing.v_display; 175 176 /* enable access to secondary head */ 177 set_crtc_owner(1); 178 179 /* Note for laptop and DVI flatpanels: 180 * CRTC timing has a seperate set of registers from flatpanel timing. 181 * The flatpanel timing registers have scaling registers that are used to match 182 * these two modelines. */ 183 { 184 LOG(4,("CRTC2: Setting full timing...\n")); 185 186 /* log the mode that will be set */ 187 LOG(2,("CRTC2:\n\tHTOT:%x\n\tHDISPEND:%x\n\tHBLNKS:%x\n\tHBLNKE:%x\n\tHSYNCS:%x\n\tHSYNCE:%x\n\t",htotal,hdisp_e,hblnk_s,hblnk_e,hsync_s,hsync_e)); 188 LOG(2,("VTOT:%x\n\tVDISPEND:%x\n\tVBLNKS:%x\n\tVBLNKE:%x\n\tVSYNCS:%x\n\tVSYNCE:%x\n",vtotal,vdisp_e,vblnk_s,vblnk_e,vsync_s,vsync_e)); 189 190 /* actually program the card! */ 191 /* unlock CRTC registers at index 0-7 */ 192 CRTC2W(VSYNCE, (CRTC2R(VSYNCE) & 0x7f)); 193 /* horizontal standard VGA regs */ 194 CRTC2W(HTOTAL, (htotal & 0xff)); 195 CRTC2W(HDISPE, (hdisp_e & 0xff)); 196 CRTC2W(HBLANKS, (hblnk_s & 0xff)); 197 /* also unlock vertical retrace registers in advance */ 198 CRTC2W(HBLANKE, ((hblnk_e & 0x1f) | 0x80)); 199 CRTC2W(HSYNCS, (hsync_s & 0xff)); 200 CRTC2W(HSYNCE, ((hsync_e & 0x1f) | ((hblnk_e & 0x20) << 2))); 201 202 /* vertical standard VGA regs */ 203 CRTC2W(VTOTAL, (vtotal & 0xff)); 204 CRTC2W(OVERFLOW, 205 ( 206 ((vtotal & 0x100) >> (8 - 0)) | ((vtotal & 0x200) >> (9 - 5)) | 207 ((vdisp_e & 0x100) >> (8 - 1)) | ((vdisp_e & 0x200) >> (9 - 6)) | 208 ((vsync_s & 0x100) >> (8 - 2)) | ((vsync_s & 0x200) >> (9 - 7)) | 209 ((vblnk_s & 0x100) >> (8 - 3)) | ((linecomp & 0x100) >> (8 - 4)) 210 )); 211 CRTC2W(PRROWSCN, 0x00); /* not used */ 212 CRTC2W(MAXSCLIN, (((vblnk_s & 0x200) >> (9 - 5)) | ((linecomp & 0x200) >> (9 - 6)))); 213 CRTC2W(VSYNCS, (vsync_s & 0xff)); 214 CRTC2W(VSYNCE, ((CRTC2R(VSYNCE) & 0xf0) | (vsync_e & 0x0f))); 215 CRTC2W(VDISPE, (vdisp_e & 0xff)); 216 CRTC2W(VBLANKS, (vblnk_s & 0xff)); 217 CRTC2W(VBLANKE, (vblnk_e & 0xff)); 218 CRTC2W(LINECOMP, (linecomp & 0xff)); 219 220 /* horizontal extended regs */ 221 //fixme: we reset bit4. is this correct?? 222 CRTC2W(HEB, (CRTC2R(HEB) & 0xe0) | 223 ( 224 ((htotal & 0x100) >> (8 - 0)) | 225 ((hdisp_e & 0x100) >> (8 - 1)) | 226 ((hblnk_s & 0x100) >> (8 - 2)) | 227 ((hsync_s & 0x100) >> (8 - 3)) 228 )); 229 230 /* (mostly) vertical extended regs */ 231 CRTC2W(LSR, 232 ( 233 ((vtotal & 0x400) >> (10 - 0)) | 234 ((vdisp_e & 0x400) >> (10 - 1)) | 235 ((vsync_s & 0x400) >> (10 - 2)) | 236 ((vblnk_s & 0x400) >> (10 - 3)) | 237 ((hblnk_e & 0x040) >> (6 - 4)) 238 //fixme: we still miss one linecomp bit!?! is this it?? 239 //| ((linecomp & 0x400) >> 3) 240 )); 241 242 /* more vertical extended regs */ 243 CRTC2W(EXTRA, 244 ( 245 ((vtotal & 0x800) >> (11 - 0)) | 246 ((vdisp_e & 0x800) >> (11 - 2)) | 247 ((vsync_s & 0x800) >> (11 - 4)) | 248 ((vblnk_s & 0x800) >> (11 - 6)) 249 //fixme: do we miss another linecomp bit!?! 250 )); 251 252 /* setup 'large screen' mode */ 253 if (target.timing.h_display >= 1280) 254 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xfb)); 255 else 256 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x04)); 257 258 /* setup HSYNC & VSYNC polarity */ 259 LOG(2,("CRTC2: sync polarity: ")); 260 temp = NV_REG8(NV8_MISCR); 261 if (target.timing.flags & B_POSITIVE_HSYNC) 262 { 263 LOG(2,("H:pos ")); 264 temp &= ~0x40; 265 } 266 else 267 { 268 LOG(2,("H:neg ")); 269 temp |= 0x40; 270 } 271 if (target.timing.flags & B_POSITIVE_VSYNC) 272 { 273 LOG(2,("V:pos ")); 274 temp &= ~0x80; 275 } 276 else 277 { 278 LOG(2,("V:neg ")); 279 temp |= 0x80; 280 } 281 NV_REG8(NV8_MISCW) = temp; 282 283 LOG(2,(", MISC reg readback: $%02x\n", NV_REG8(NV8_MISCR))); 284 } 285 286 /* always disable interlaced operation */ 287 /* (interlace is supported on upto and including NV10, NV15, and NV30 and up) */ 288 CRTC2W(INTERLACE, 0xff); 289 290 /* disable CRTC slaved mode unless a panel is in use */ 291 // fixme: this kills TVout when it was in use... 292 if (!si->ps.tmds2_active) CRTC2W(PIXEL, (CRTC2R(PIXEL) & 0x7f)); 293 294 /* setup flatpanel if connected and active */ 295 if (si->ps.tmds2_active) 296 { 297 uint32 iscale_x, iscale_y; 298 299 /* calculate inverse scaling factors used by hardware in 20.12 format */ 300 iscale_x = (((1 << 12) * target.timing.h_display) / si->ps.p2_timing.h_display); 301 iscale_y = (((1 << 12) * target.timing.v_display) / si->ps.p2_timing.v_display); 302 303 /* unblock flatpanel timing programming (or something like that..) */ 304 CRTC2W(FP_HTIMING, 0); 305 CRTC2W(FP_VTIMING, 0); 306 LOG(2,("CRTC2: FP_HTIMING reg readback: $%02x\n", CRTC2R(FP_HTIMING))); 307 LOG(2,("CRTC2: FP_VTIMING reg readback: $%02x\n", CRTC2R(FP_VTIMING))); 308 309 /* enable full width visibility on flatpanel */ 310 DAC2W(FP_HVALID_S, 0); 311 DAC2W(FP_HVALID_E, (si->ps.p2_timing.h_display - 1)); 312 /* enable full height visibility on flatpanel */ 313 DAC2W(FP_VVALID_S, 0); 314 DAC2W(FP_VVALID_E, (si->ps.p2_timing.v_display - 1)); 315 316 /* nVidia cards support upscaling except on ??? */ 317 /* NV11 cards can upscale after all! */ 318 if (0)//si->ps.card_type == NV11) 319 { 320 /* disable last fetched line limiting */ 321 DAC2W(FP_DEBUG2, 0x00000000); 322 /* inform panel to scale if needed */ 323 if ((iscale_x != (1 << 12)) || (iscale_y != (1 << 12))) 324 { 325 LOG(2,("CRTC2: DFP needs to do scaling\n")); 326 DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) | 0x00000100)); 327 } 328 else 329 { 330 LOG(2,("CRTC2: no scaling for DFP needed\n")); 331 DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) & 0xfffffeff)); 332 } 333 } 334 else 335 { 336 float dm_aspect; 337 338 LOG(2,("CRTC2: GPU scales for DFP if needed\n")); 339 340 /* calculate display mode aspect */ 341 dm_aspect = (target.timing.h_display / ((float)target.timing.v_display)); 342 343 /* limit last fetched line if vertical scaling is done */ 344 if (iscale_y != (1 << 12)) 345 DAC2W(FP_DEBUG2, ((1 << 28) | ((target.timing.v_display - 1) << 16))); 346 else 347 DAC2W(FP_DEBUG2, 0x00000000); 348 349 /* inform panel not to scale */ 350 DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) & 0xfffffeff)); 351 352 /* GPU scaling is automatically setup by hardware, so only modify this 353 * scalingfactor for non 4:3 (1.33) aspect panels; 354 * let's consider 1280x1024 1:33 aspect (it's 1.25 aspect actually!) */ 355 356 /* correct for widescreen panels relative to mode... 357 * (so if panel is more widescreen than mode being set) */ 358 /* BTW: known widescreen panels: 359 * 1280 x 800 (1.60), 360 * 1440 x 900 (1.60), 361 * 1680 x 1050 (1.60), 362 * 1920 x 1200 (1.60). */ 363 /* known 4:3 aspect non-standard resolution panels: 364 * 1400 x 1050 (1.33). */ 365 /* NOTE: 366 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */ 367 if ((iscale_x != (1 << 12)) && (si->ps.panel2_aspect > (dm_aspect + 0.10))) 368 { 369 uint16 diff; 370 371 LOG(2,("CRTC2: (relative) widescreen panel: tuning horizontal scaling\n")); 372 373 /* X-scaling should be the same as Y-scaling */ 374 iscale_x = iscale_y; 375 /* enable testmode (b12) and program new X-scaling factor */ 376 DAC2W(FP_DEBUG1, (((iscale_x >> 1) & 0x00000fff) | (1 << 12))); 377 /* center/cut-off left and right side of screen */ 378 diff = ((si->ps.p2_timing.h_display - 379 (target.timing.h_display * ((1 << 12) / ((float)iscale_x)))) 380 / 2); 381 DAC2W(FP_HVALID_S, diff); 382 DAC2W(FP_HVALID_E, ((si->ps.p2_timing.h_display - diff) - 1)); 383 } 384 /* correct for portrait panels... */ 385 /* NOTE: 386 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */ 387 if ((iscale_y != (1 << 12)) && (si->ps.panel2_aspect < (dm_aspect - 0.10))) 388 { 389 LOG(2,("CRTC2: (relative) portrait panel: should tune vertical scaling\n")); 390 /* fixme: implement if this kind of portrait panels exist on nVidia... */ 391 } 392 } 393 394 /* do some logging.. */ 395 LOG(2,("CRTC2: FP_HVALID_S reg readback: $%08x\n", DAC2R(FP_HVALID_S))); 396 LOG(2,("CRTC2: FP_HVALID_E reg readback: $%08x\n", DAC2R(FP_HVALID_E))); 397 LOG(2,("CRTC2: FP_VVALID_S reg readback: $%08x\n", DAC2R(FP_VVALID_S))); 398 LOG(2,("CRTC2: FP_VVALID_E reg readback: $%08x\n", DAC2R(FP_VVALID_E))); 399 LOG(2,("CRTC2: FP_DEBUG0 reg readback: $%08x\n", DAC2R(FP_DEBUG0))); 400 LOG(2,("CRTC2: FP_DEBUG1 reg readback: $%08x\n", DAC2R(FP_DEBUG1))); 401 LOG(2,("CRTC2: FP_DEBUG2 reg readback: $%08x\n", DAC2R(FP_DEBUG2))); 402 LOG(2,("CRTC2: FP_DEBUG3 reg readback: $%08x\n", DAC2R(FP_DEBUG3))); 403 LOG(2,("CRTC2: FP_TG_CTRL reg readback: $%08x\n", DAC2R(FP_TG_CTRL))); 404 } 405 406 return B_OK; 407 } 408 409 status_t nv_crtc2_depth(int mode) 410 { 411 uint8 viddelay = 0; 412 uint32 genctrl = 0; 413 414 /* set VCLK scaling */ 415 switch(mode) 416 { 417 case BPP8: 418 viddelay = 0x01; 419 /* genctrl b4 & b5 reset: 'direct mode' */ 420 genctrl = 0x00101100; 421 break; 422 case BPP15: 423 viddelay = 0x02; 424 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 425 genctrl = 0x00100130; 426 break; 427 case BPP16: 428 viddelay = 0x02; 429 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 430 genctrl = 0x00101130; 431 break; 432 case BPP24: 433 viddelay = 0x03; 434 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 435 genctrl = 0x00100130; 436 break; 437 case BPP32: 438 viddelay = 0x03; 439 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 440 genctrl = 0x00101130; 441 break; 442 } 443 /* enable access to secondary head */ 444 set_crtc_owner(1); 445 446 CRTC2W(PIXEL, ((CRTC2R(PIXEL) & 0xfc) | viddelay)); 447 DAC2W(GENCTRL, genctrl); 448 449 return B_OK; 450 } 451 452 status_t nv_crtc2_dpms(bool display, bool h, bool v) 453 { 454 uint8 temp; 455 456 LOG(4,("CRTC2: setting DPMS: ")); 457 458 /* enable access to secondary head */ 459 set_crtc_owner(1); 460 461 /* start synchronous reset: required before turning screen off! */ 462 SEQW(RESET, 0x01); 463 464 /* turn screen off */ 465 temp = SEQR(CLKMODE); 466 if (display) 467 { 468 SEQW(CLKMODE, (temp & ~0x20)); 469 470 /* end synchronous reset if display should be enabled */ 471 SEQW(RESET, 0x03); 472 473 //'safe mode' test! feedback needed with this 'setting'! 474 if (0)//si->ps.tmds2_active) 475 { 476 /* powerup both LVDS (laptop panellink) and TMDS (DVI panellink) 477 * internal transmitters... */ 478 /* note: 479 * the powerbits in this register are hardwired to the DVI connectors, 480 * instead of to the DACs! (confirmed NV34) */ 481 //fixme... 482 DAC2W(FP_DEBUG0, (DAC2R(FP_DEBUG0) & 0xcfffffff)); 483 /* ... and powerup external TMDS transmitter if it exists */ 484 /* (confirmed OK on NV28 and NV34) */ 485 CRTC2W(0x59, (CRTC2R(0x59) | 0x01)); 486 } 487 488 LOG(4,("display on, ")); 489 } 490 else 491 { 492 SEQW(CLKMODE, (temp | 0x20)); 493 494 //'safe mode' test! feedback needed with this 'setting'! 495 if (0)//si->ps.tmds2_active) 496 { 497 /* powerdown both LVDS (laptop panellink) and TMDS (DVI panellink) 498 * internal transmitters... */ 499 /* note: 500 * the powerbits in this register are hardwired to the DVI connectors, 501 * instead of to the DACs! (confirmed NV34) */ 502 //fixme... 503 DAC2W(FP_DEBUG0, (DAC2R(FP_DEBUG0) | 0x30000000)); 504 /* ... and powerdown external TMDS transmitter if it exists */ 505 /* (confirmed OK on NV28 and NV34) */ 506 CRTC2W(0x59, (CRTC2R(0x59) & 0xfe)); 507 } 508 509 LOG(4,("display off, ")); 510 } 511 512 if (h) 513 { 514 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0x7f)); 515 LOG(4,("hsync enabled, ")); 516 } 517 else 518 { 519 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x80)); 520 LOG(4,("hsync disabled, ")); 521 } 522 if (v) 523 { 524 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xbf)); 525 LOG(4,("vsync enabled\n")); 526 } 527 else 528 { 529 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x40)); 530 LOG(4,("vsync disabled\n")); 531 } 532 533 return B_OK; 534 } 535 536 status_t nv_crtc2_dpms_fetch(bool *display, bool *h, bool *v) 537 { 538 /* enable access to secondary head */ 539 set_crtc_owner(1); 540 541 *display = !(SEQR(CLKMODE) & 0x20); 542 *h = !(CRTC2R(REPAINT1) & 0x80); 543 *v = !(CRTC2R(REPAINT1) & 0x40); 544 545 LOG(4,("CTRC2: fetched DPMS state: ")); 546 if (*display) LOG(4,("display on, ")); 547 else LOG(4,("display off, ")); 548 if (*h) LOG(4,("hsync enabled, ")); 549 else LOG(4,("hsync disabled, ")); 550 if (*v) LOG(4,("vsync enabled\n")); 551 else LOG(4,("vsync disabled\n")); 552 553 return B_OK; 554 } 555 556 status_t nv_crtc2_set_display_pitch() 557 { 558 uint32 offset; 559 560 LOG(4,("CRTC2: setting card pitch (offset between lines)\n")); 561 562 /* figure out offset value hardware needs */ 563 offset = si->fbc.bytes_per_row / 8; 564 565 LOG(2,("CRTC2: offset register set to: $%04x\n", offset)); 566 567 /* enable access to secondary head */ 568 set_crtc_owner(1); 569 570 /* program the card */ 571 CRTC2W(PITCHL, (offset & 0x00ff)); 572 CRTC2W(REPAINT0, ((CRTC2R(REPAINT0) & 0x1f) | ((offset & 0x0700) >> 3))); 573 574 return B_OK; 575 } 576 577 status_t nv_crtc2_set_display_start(uint32 startadd,uint8 bpp) 578 { 579 uint32 timeout = 0; 580 581 LOG(4,("CRTC2: setting card RAM to be displayed bpp %d\n", bpp)); 582 583 LOG(2,("CRTC2: startadd: $%08x\n", startadd)); 584 LOG(2,("CRTC2: frameRAM: $%08x\n", si->framebuffer)); 585 LOG(2,("CRTC2: framebuffer: $%08x\n", si->fbc.frame_buffer)); 586 587 /* we might have no retraces during setmode! */ 588 /* wait 25mS max. for retrace to occur (refresh > 40Hz) */ 589 while (((NV_REG32(NV32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) && 590 (timeout < (25000/10))) 591 { 592 /* don't snooze much longer or retrace might get missed! */ 593 snooze(10); 594 timeout++; 595 } 596 597 /* enable access to secondary head */ 598 set_crtc_owner(1); 599 600 /* upto 4Gb RAM adressing: must be used on NV10 and later! */ 601 /* NOTE: 602 * While this register also exists on pre-NV10 cards, it will 603 * wrap-around at 16Mb boundaries!! */ 604 605 /* 30bit adress in 32bit words */ 606 NV_REG32(NV32_NV10FB2STADD32) = (startadd & 0xfffffffc); 607 608 /* set byte adress: (b0 - 1) */ 609 ATB2W(HORPIXPAN, ((startadd & 0x00000003) << 1)); 610 611 return B_OK; 612 } 613 614 status_t nv_crtc2_cursor_init() 615 { 616 int i; 617 uint32 * fb; 618 /* cursor bitmap will be stored at the start of the framebuffer */ 619 const uint32 curadd = 0; 620 621 /* enable access to secondary head */ 622 set_crtc_owner(1); 623 624 /* set cursor bitmap adress ... */ 625 if (si->ps.laptop) 626 { 627 /* must be used this way on pre-NV10 and on all 'Go' cards! */ 628 629 /* cursorbitmap must start on 2Kbyte boundary: */ 630 /* set adress bit11-16, and set 'no doublescan' (registerbit 1 = 0) */ 631 CRTC2W(CURCTL0, ((curadd & 0x0001f800) >> 9)); 632 /* set adress bit17-23, and set graphics mode cursor(?) (registerbit 7 = 1) */ 633 CRTC2W(CURCTL1, (((curadd & 0x00fe0000) >> 17) | 0x80)); 634 /* set adress bit24-31 */ 635 CRTC2W(CURCTL2, ((curadd & 0xff000000) >> 24)); 636 } 637 else 638 { 639 /* upto 4Gb RAM adressing: 640 * can be used on NV10 and later (except for 'Go' cards)! */ 641 /* NOTE: 642 * This register does not exist on pre-NV10 and 'Go' cards. */ 643 644 /* cursorbitmap must still start on 2Kbyte boundary: */ 645 NV_REG32(NV32_NV10CUR2ADD32) = (curadd & 0xfffff800); 646 } 647 648 /* set cursor colour: not needed because of direct nature of cursor bitmap. */ 649 650 /*clear cursor*/ 651 fb = (uint32 *) si->framebuffer + curadd; 652 for (i=0;i<(2048/4);i++) 653 { 654 fb[i]=0; 655 } 656 657 /* select 32x32 pixel, 16bit color cursorbitmap, no doublescan */ 658 NV_REG32(NV32_2CURCONF) = 0x02000100; 659 660 /* activate hardware cursor */ 661 nv_crtc2_cursor_show(); 662 663 return B_OK; 664 } 665 666 status_t nv_crtc2_cursor_show() 667 { 668 LOG(4,("CRTC2: enabling cursor\n")); 669 670 /* enable access to secondary head */ 671 set_crtc_owner(1); 672 673 /* b0 = 1 enables cursor */ 674 CRTC2W(CURCTL0, (CRTC2R(CURCTL0) | 0x01)); 675 676 return B_OK; 677 } 678 679 status_t nv_crtc2_cursor_hide() 680 { 681 LOG(4,("CRTC2: disabling cursor\n")); 682 683 /* enable access to secondary head */ 684 set_crtc_owner(1); 685 686 /* b0 = 0 disables cursor */ 687 CRTC2W(CURCTL0, (CRTC2R(CURCTL0) & 0xfe)); 688 689 return B_OK; 690 } 691 692 /*set up cursor shape*/ 693 status_t nv_crtc2_cursor_define(uint8* andMask,uint8* xorMask) 694 { 695 int x, y; 696 uint8 b; 697 uint16 *cursor; 698 uint16 pixel; 699 700 /* get a pointer to the cursor */ 701 cursor = (uint16*) si->framebuffer; 702 703 /* draw the cursor */ 704 /* (Nvidia cards have a RGB15 direct color cursor bitmap, bit #16 is transparancy) */ 705 for (y = 0; y < 16; y++) 706 { 707 b = 0x80; 708 for (x = 0; x < 8; x++) 709 { 710 /* preset transparant */ 711 pixel = 0x0000; 712 /* set white if requested */ 713 if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; 714 /* set black if requested */ 715 if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; 716 /* set invert if requested */ 717 if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; 718 /* place the pixel in the bitmap */ 719 cursor[x + (y * 32)] = pixel; 720 b >>= 1; 721 } 722 xorMask++; 723 andMask++; 724 b = 0x80; 725 for (; x < 16; x++) 726 { 727 /* preset transparant */ 728 pixel = 0x0000; 729 /* set white if requested */ 730 if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; 731 /* set black if requested */ 732 if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; 733 /* set invert if requested */ 734 if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; 735 /* place the pixel in the bitmap */ 736 cursor[x + (y * 32)] = pixel; 737 b >>= 1; 738 } 739 xorMask++; 740 andMask++; 741 } 742 743 return B_OK; 744 } 745 746 /* position the cursor */ 747 status_t nv_crtc2_cursor_position(uint16 x, uint16 y) 748 { 749 uint16 yhigh; 750 751 /* make sure we are beyond the first line of the cursorbitmap being drawn during 752 * updating the position to prevent distortions: no double buffering feature */ 753 /* Note: 754 * we need to return as quick as possible or some apps will exhibit lagging.. */ 755 756 /* read the old cursor Y position */ 757 yhigh = ((DAC2R(CURPOS) & 0x0fff0000) >> 16); 758 /* make sure we will wait until we are below both the old and new Y position: 759 * visible cursorbitmap drawing needs to be done at least... */ 760 if (y > yhigh) yhigh = y; 761 762 if (yhigh < (si->dm.timing.v_display - 16)) 763 { 764 /* we have vertical lines below old and new cursorposition to spare. So we 765 * update the cursor postion 'mid-screen', but below that area. */ 766 while (((uint16)(NV_REG32(NV32_RASTER2) & 0x000007ff)) < (yhigh + 16)) 767 { 768 snooze(10); 769 } 770 } 771 else 772 { 773 /* no room to spare, just wait for retrace (is relatively slow) */ 774 while ((NV_REG32(NV32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) 775 { 776 /* don't snooze much longer or retrace might get missed! */ 777 snooze(10); 778 } 779 } 780 781 /* update cursorposition */ 782 DAC2W(CURPOS, ((x & 0x0fff) | ((y & 0x0fff) << 16))); 783 784 return B_OK; 785 } 786