1 /* second CTRC functionality for GeForce cards */ 2 /* Author: 3 Rudolf Cornelissen 11/2002-4/2004 4 */ 5 6 #define MODULE_BIT 0x00020000 7 8 #include "nv_std.h" 9 10 /*Adjust passed parameters to a valid mode line*/ 11 status_t nv_crtc2_validate_timing( 12 uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht, 13 uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt 14 ) 15 { 16 /* horizontal */ 17 /* make all parameters multiples of 8 */ 18 *hd_e &= 0xfff8; 19 *hs_s &= 0xfff8; 20 *hs_e &= 0xfff8; 21 *ht &= 0xfff8; 22 23 /* confine to required number of bits, taking logic into account */ 24 if (*hd_e > ((0x01ff - 2) << 3)) *hd_e = ((0x01ff - 2) << 3); 25 if (*hs_s > ((0x01ff - 1) << 3)) *hs_s = ((0x01ff - 1) << 3); 26 if (*hs_e > ( 0x01ff << 3)) *hs_e = ( 0x01ff << 3); 27 if (*ht > ((0x01ff + 5) << 3)) *ht = ((0x01ff + 5) << 3); 28 29 /* NOTE: keep horizontal timing at multiples of 8! */ 30 /* confine to a reasonable width */ 31 if (*hd_e < 640) *hd_e = 640; 32 if (*hd_e > 2048) *hd_e = 2048; 33 34 /* if hor. total does not leave room for a sensible sync pulse, increase it! */ 35 if (*ht < (*hd_e + 80)) *ht = (*hd_e + 80); 36 37 /* make sure sync pulse is not during display */ 38 if (*hs_e > (*ht - 8)) *hs_e = (*ht - 8); 39 if (*hs_s < (*hd_e + 8)) *hs_s = (*hd_e + 8); 40 41 /* correct sync pulse if it is too long: 42 * there are only 5 bits available to save this in the card registers! */ 43 if (*hs_e > (*hs_s + 0xf8)) *hs_e = (*hs_s + 0xf8); 44 45 /*vertical*/ 46 /* confine to required number of bits, taking logic into account */ 47 //fixme if needed: on GeForce cards there are 12 instead of 11 bits... 48 if (*vd_e > (0x7ff - 2)) *vd_e = (0x7ff - 2); 49 if (*vs_s > (0x7ff - 1)) *vs_s = (0x7ff - 1); 50 if (*vs_e > 0x7ff ) *vs_e = 0x7ff ; 51 if (*vt > (0x7ff + 2)) *vt = (0x7ff + 2); 52 53 /* confine to a reasonable height */ 54 if (*vd_e < 480) *vd_e = 480; 55 if (*vd_e > 1536) *vd_e = 1536; 56 57 /*if vertical total does not leave room for a sync pulse, increase it!*/ 58 if (*vt < (*vd_e + 3)) *vt = (*vd_e + 3); 59 60 /* make sure sync pulse is not during display */ 61 if (*vs_e > (*vt - 1)) *vs_e = (*vt - 1); 62 if (*vs_s < (*vd_e + 1)) *vs_s = (*vd_e + 1); 63 64 /* correct sync pulse if it is too long: 65 * there are only 4 bits available to save this in the card registers! */ 66 if (*vs_e > (*vs_s + 0x0f)) *vs_e = (*vs_s + 0x0f); 67 68 return B_OK; 69 } 70 71 /*set a mode line - inputs are in pixels*/ 72 status_t nv_crtc2_set_timing(display_mode target) 73 { 74 uint8 temp; 75 76 uint32 htotal; /*total horizontal total VCLKs*/ 77 uint32 hdisp_e; /*end of horizontal display (begins at 0)*/ 78 uint32 hsync_s; /*begin of horizontal sync pulse*/ 79 uint32 hsync_e; /*end of horizontal sync pulse*/ 80 uint32 hblnk_s; /*begin horizontal blanking*/ 81 uint32 hblnk_e; /*end horizontal blanking*/ 82 83 uint32 vtotal; /*total vertical total scanlines*/ 84 uint32 vdisp_e; /*end of vertical display*/ 85 uint32 vsync_s; /*begin of vertical sync pulse*/ 86 uint32 vsync_e; /*end of vertical sync pulse*/ 87 uint32 vblnk_s; /*begin vertical blanking*/ 88 uint32 vblnk_e; /*end vertical blanking*/ 89 90 uint32 linecomp; /*split screen and vdisp_e interrupt*/ 91 92 LOG(4,("CRTC2: setting timing\n")); 93 94 /* setup fixed modeline for flatpanel if connected and active */ 95 if (si->ps.tmds2_active) 96 { 97 LOG(2,("CRTC2: DFP active: tuning modeline\n")); 98 99 /* horizontal timing */ 100 //fixme (?): maybe we need real modeline calculations here... 101 //testing (640x480): total = 135% is too much, 120% to small... 102 target.timing.h_total = target.timing.h_display + 160;//128 103 target.timing.h_sync_start = target.timing.h_total - 144;//112 104 target.timing.h_sync_end = target.timing.h_total - 48;//16 105 106 /* vertical timing */ 107 target.timing.v_total = target.timing.v_display + 6; 108 target.timing.v_sync_start = target.timing.v_total - 3; 109 target.timing.v_sync_end = target.timing.v_total - 2; 110 111 /* disable GPU scaling testmode so automatic scaling will be done */ 112 DAC2W(FP_DEBUG1, 0); 113 } 114 115 /* Modify parameters as required by standard VGA */ 116 htotal = ((target.timing.h_total >> 3) - 5); 117 hdisp_e = ((target.timing.h_display >> 3) - 1); 118 hblnk_s = hdisp_e; 119 hblnk_e = (htotal + 4);//0; 120 hsync_s = (target.timing.h_sync_start >> 3); 121 hsync_e = (target.timing.h_sync_end >> 3); 122 123 vtotal = target.timing.v_total - 2; 124 vdisp_e = target.timing.v_display - 1; 125 vblnk_s = vdisp_e; 126 vblnk_e = (vtotal + 1); 127 vsync_s = target.timing.v_sync_start;//-1; 128 vsync_e = target.timing.v_sync_end;//-1; 129 130 /* prevent memory adress counter from being reset (linecomp may not occur) */ 131 linecomp = target.timing.v_display; 132 133 /* enable access to CRTC2 */ 134 CRTC2W(OWNER, 0x03); 135 136 /* Note for laptop and DVI flatpanels: 137 * CRTC timing has a seperate set of registers from flatpanel timing. 138 * The flatpanel timing registers have scaling registers that are used to match 139 * these two modelines. */ 140 { 141 LOG(4,("CRTC2: Setting full timing...\n")); 142 143 /* log the mode that will be set */ 144 LOG(2,("CRTC2:\n\tHTOT:%x\n\tHDISPEND:%x\n\tHBLNKS:%x\n\tHBLNKE:%x\n\tHSYNCS:%x\n\tHSYNCE:%x\n\t",htotal,hdisp_e,hblnk_s,hblnk_e,hsync_s,hsync_e)); 145 LOG(2,("VTOT:%x\n\tVDISPEND:%x\n\tVBLNKS:%x\n\tVBLNKE:%x\n\tVSYNCS:%x\n\tVSYNCE:%x\n",vtotal,vdisp_e,vblnk_s,vblnk_e,vsync_s,vsync_e)); 146 147 /* actually program the card! */ 148 /* unlock CRTC registers at index 0-7 */ 149 CRTC2W(VSYNCE, (CRTC2R(VSYNCE) & 0x7f)); 150 /* horizontal standard VGA regs */ 151 CRTC2W(HTOTAL, (htotal & 0xff)); 152 CRTC2W(HDISPE, (hdisp_e & 0xff)); 153 CRTC2W(HBLANKS, (hblnk_s & 0xff)); 154 /* also unlock vertical retrace registers in advance */ 155 CRTC2W(HBLANKE, ((hblnk_e & 0x1f) | 0x80)); 156 CRTC2W(HSYNCS, (hsync_s & 0xff)); 157 CRTC2W(HSYNCE, ((hsync_e & 0x1f) | ((hblnk_e & 0x20) << 2))); 158 159 /* vertical standard VGA regs */ 160 CRTC2W(VTOTAL, (vtotal & 0xff)); 161 CRTC2W(OVERFLOW, 162 ( 163 ((vtotal & 0x100) >> (8 - 0)) | ((vtotal & 0x200) >> (9 - 5)) | 164 ((vdisp_e & 0x100) >> (8 - 1)) | ((vdisp_e & 0x200) >> (9 - 6)) | 165 ((vsync_s & 0x100) >> (8 - 2)) | ((vsync_s & 0x200) >> (9 - 7)) | 166 ((vblnk_s & 0x100) >> (8 - 3)) | ((linecomp & 0x100) >> (8 - 4)) 167 )); 168 CRTC2W(PRROWSCN, 0x00); /* not used */ 169 CRTC2W(MAXSCLIN, (((vblnk_s & 0x200) >> (9 - 5)) | ((linecomp & 0x200) >> (9 - 6)))); 170 CRTC2W(VSYNCS, (vsync_s & 0xff)); 171 CRTC2W(VSYNCE, ((CRTC2R(VSYNCE) & 0xf0) | (vsync_e & 0x0f))); 172 CRTC2W(VDISPE, (vdisp_e & 0xff)); 173 CRTC2W(VBLANKS, (vblnk_s & 0xff)); 174 CRTC2W(VBLANKE, (vblnk_e & 0xff)); 175 CRTC2W(LINECOMP, (linecomp & 0xff)); 176 177 /* horizontal extended regs */ 178 //fixme: we reset bit4. is this correct?? 179 CRTC2W(HEB, (CRTC2R(HEB) & 0xe0) | 180 ( 181 ((htotal & 0x100) >> (8 - 0)) | 182 ((hdisp_e & 0x100) >> (8 - 1)) | 183 ((hblnk_s & 0x100) >> (8 - 2)) | 184 ((hsync_s & 0x100) >> (8 - 3)) 185 )); 186 187 /* (mostly) vertical extended regs */ 188 CRTC2W(LSR, 189 ( 190 ((vtotal & 0x400) >> (10 - 0)) | 191 ((vdisp_e & 0x400) >> (10 - 1)) | 192 ((vsync_s & 0x400) >> (10 - 2)) | 193 ((vblnk_s & 0x400) >> (10 - 3)) | 194 ((hblnk_e & 0x040) >> (6 - 4)) 195 //fixme: we still miss one linecomp bit!?! is this it?? 196 //| ((linecomp & 0x400) >> 3) 197 )); 198 199 /* more vertical extended regs */ 200 CRTC2W(EXTRA, 201 ( 202 ((vtotal & 0x800) >> (11 - 0)) | 203 ((vdisp_e & 0x800) >> (11 - 2)) | 204 ((vsync_s & 0x800) >> (11 - 4)) | 205 ((vblnk_s & 0x800) >> (11 - 6)) 206 //fixme: do we miss another linecomp bit!?! 207 )); 208 209 /* setup 'large screen' mode */ 210 if (target.timing.h_display >= 1280) 211 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xfb)); 212 else 213 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x04)); 214 215 /* setup HSYNC & VSYNC polarity */ 216 LOG(2,("CRTC2: sync polarity: ")); 217 temp = NV_REG8(NV8_MISCR); 218 if (target.timing.flags & B_POSITIVE_HSYNC) 219 { 220 LOG(2,("H:pos ")); 221 temp &= ~0x40; 222 } 223 else 224 { 225 LOG(2,("H:neg ")); 226 temp |= 0x40; 227 } 228 if (target.timing.flags & B_POSITIVE_VSYNC) 229 { 230 LOG(2,("V:pos ")); 231 temp &= ~0x80; 232 } 233 else 234 { 235 LOG(2,("V:neg ")); 236 temp |= 0x80; 237 } 238 NV_REG8(NV8_MISCW) = temp; 239 240 LOG(2,(", MISC reg readback: $%02x\n", NV_REG8(NV8_MISCR))); 241 } 242 243 /* always disable interlaced operation */ 244 /* (interlace is supported on upto and including NV10, NV15, and NV30 and up) */ 245 CRTC2W(INTERLACE, 0xff); 246 247 /* setup flatpanel if connected and active */ 248 if (si->ps.tmds2_active) 249 { 250 uint32 iscale_x, iscale_y; 251 252 /* powerup both LVDS (laptop panellink) and TMDS (DVI panellink) transmitters */ 253 //fixme: remove once DPMS confirmed OK! 254 // DAC2W(FP_DEBUG0, (DAC2R(FP_DEBUG0) & 0xcfffffff)); 255 256 /* calculate inverse scaling factors used by hardware in 20.12 format */ 257 iscale_x = (((1 << 12) * target.timing.h_display) / si->ps.panel2_width); 258 iscale_y = (((1 << 12) * target.timing.v_display) / si->ps.panel2_height); 259 260 /* unblock flatpanel timing programming (or something like that..) */ 261 CRTC2W(FP_HTIMING, 0); 262 CRTC2W(FP_VTIMING, 0); 263 LOG(2,("CRTC2: FP_HTIMING reg readback: $%02x\n", CRTC2R(FP_HTIMING))); 264 LOG(2,("CRTC2: FP_VTIMING reg readback: $%02x\n", CRTC2R(FP_VTIMING))); 265 266 /* enable full width visibility on flatpanel */ 267 DAC2W(FP_HVALID_S, 0); 268 DAC2W(FP_HVALID_E, (si->ps.panel2_width - 1)); 269 /* enable full height visibility on flatpanel */ 270 DAC2W(FP_VVALID_S, 0); 271 DAC2W(FP_VVALID_E, (si->ps.panel2_height - 1)); 272 273 /* nVidia cards support upscaling except on ??? */ 274 /* NV11 cards can upscale after all! */ 275 if (0)//si->ps.card_type == NV11) 276 { 277 /* disable last fetched line limiting */ 278 DAC2W(FP_DEBUG2, 0x00000000); 279 /* inform panel to scale if needed */ 280 if ((iscale_x != (1 << 12)) || (iscale_y != (1 << 12))) 281 { 282 LOG(2,("CRTC2: DFP needs to do scaling\n")); 283 DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) | 0x00000100)); 284 } 285 else 286 { 287 LOG(2,("CRTC2: no scaling for DFP needed\n")); 288 DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) & 0xfffffeff)); 289 } 290 } 291 else 292 { 293 float dm_aspect; 294 295 LOG(2,("CRTC2: GPU scales for DFP if needed\n")); 296 297 /* calculate display mode aspect */ 298 dm_aspect = (target.timing.h_display / ((float)target.timing.v_display)); 299 300 /* limit last fetched line if vertical scaling is done */ 301 if (iscale_y != (1 << 12)) 302 DAC2W(FP_DEBUG2, ((1 << 28) | ((target.timing.v_display - 1) << 16))); 303 else 304 DAC2W(FP_DEBUG2, 0x00000000); 305 306 /* inform panel not to scale */ 307 DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) & 0xfffffeff)); 308 309 /* GPU scaling is automatically setup by hardware, so only modify this 310 * scalingfactor for non 4:3 (1.33) aspect panels; 311 * let's consider 1280x1024 1:33 aspect (it's 1.25 aspect actually!) */ 312 313 /* correct for widescreen panels relative to mode... 314 * (so if panel is more widescreen than mode being set) */ 315 /* BTW: known widescreen panels: 316 * 1280 x 800 (1.60), 317 * 1440 x 900 (1.60), 318 * 1680 x 1050 (1.60). */ 319 /* known 4:3 aspect non-standard resolution panels: 320 * 1400 x 1050 (1.33). */ 321 /* NOTE: 322 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */ 323 if ((iscale_x != (1 << 12)) && (si->ps.panel2_aspect > (dm_aspect + 0.10))) 324 { 325 uint16 diff; 326 327 LOG(2,("CRTC2: (relative) widescreen panel: tuning horizontal scaling\n")); 328 329 /* X-scaling should be the same as Y-scaling */ 330 iscale_x = iscale_y; 331 /* enable testmode (b12) and program new X-scaling factor */ 332 DAC2W(FP_DEBUG1, (((iscale_x >> 1) & 0x00000fff) | (1 << 12))); 333 /* center/cut-off left and right side of screen */ 334 diff = ((si->ps.panel2_width - 335 (target.timing.h_display * ((1 << 12) / ((float)iscale_x)))) 336 / 2); 337 DAC2W(FP_HVALID_S, diff); 338 DAC2W(FP_HVALID_E, ((si->ps.panel2_width - diff) - 1)); 339 } 340 /* correct for portrait panels... */ 341 /* NOTE: 342 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */ 343 if ((iscale_y != (1 << 12)) && (si->ps.panel2_aspect < (dm_aspect - 0.10))) 344 { 345 LOG(2,("CRTC2: (relative) portrait panel: should tune vertical scaling\n")); 346 /* fixme: implement if this kind of portrait panels exist on nVidia... */ 347 } 348 } 349 350 /* do some logging.. */ 351 LOG(2,("CRTC2: FP_HVALID_S reg readback: $%08x\n", DAC2R(FP_HVALID_S))); 352 LOG(2,("CRTC2: FP_HVALID_E reg readback: $%08x\n", DAC2R(FP_HVALID_E))); 353 LOG(2,("CRTC2: FP_VVALID_S reg readback: $%08x\n", DAC2R(FP_VVALID_S))); 354 LOG(2,("CRTC2: FP_VVALID_E reg readback: $%08x\n", DAC2R(FP_VVALID_E))); 355 LOG(2,("CRTC2: FP_DEBUG0 reg readback: $%08x\n", DAC2R(FP_DEBUG0))); 356 LOG(2,("CRTC2: FP_DEBUG1 reg readback: $%08x\n", DAC2R(FP_DEBUG1))); 357 LOG(2,("CRTC2: FP_DEBUG2 reg readback: $%08x\n", DAC2R(FP_DEBUG2))); 358 LOG(2,("CRTC2: FP_DEBUG3 reg readback: $%08x\n", DAC2R(FP_DEBUG3))); 359 LOG(2,("CRTC2: FP_TG_CTRL reg readback: $%08x\n", DAC2R(FP_TG_CTRL))); 360 } 361 362 return B_OK; 363 } 364 365 status_t nv_crtc2_depth(int mode) 366 { 367 uint8 viddelay = 0; 368 uint32 genctrl = 0; 369 370 /* set VCLK scaling */ 371 switch(mode) 372 { 373 case BPP8: 374 viddelay = 0x01; 375 /* genctrl b4 & b5 reset: 'direct mode' */ 376 genctrl = 0x00101100; 377 break; 378 case BPP15: 379 viddelay = 0x02; 380 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 381 genctrl = 0x00100130; 382 break; 383 case BPP16: 384 viddelay = 0x02; 385 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 386 genctrl = 0x00101130; 387 break; 388 case BPP24: 389 viddelay = 0x03; 390 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 391 genctrl = 0x00100130; 392 break; 393 case BPP32: 394 viddelay = 0x03; 395 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 396 genctrl = 0x00101130; 397 break; 398 } 399 /* enable access to CRTC2 */ 400 CRTC2W(OWNER, 0x03); 401 402 CRTC2W(PIXEL, ((CRTC2R(PIXEL) & 0xfc) | viddelay)); 403 DAC2W(GENCTRL, genctrl); 404 405 return B_OK; 406 } 407 408 status_t nv_crtc2_dpms(bool display, bool h, bool v) 409 { 410 uint8 temp; 411 412 LOG(4,("CRTC2: setting DPMS: ")); 413 414 /* enable access to CRTC2 (and SEQUENCER2) */ 415 CRTC2W(OWNER, 0x03); 416 417 /* start synchronous reset: required before turning screen off! */ 418 SEQW(RESET, 0x01); 419 420 /* turn screen off */ 421 temp = SEQR(CLKMODE); 422 if (display) 423 { 424 SEQW(CLKMODE, (temp & ~0x20)); 425 426 /* end synchronous reset if display should be enabled */ 427 SEQW(RESET, 0x03); 428 429 /* powerup both LVDS (laptop panellink) and TMDS (DVI panellink) transmitters */ 430 if (si->ps.tmds2_active) DAC2W(FP_DEBUG0, (DAC2R(FP_DEBUG0) & 0xcfffffff)); 431 432 LOG(4,("display on, ")); 433 } 434 else 435 { 436 SEQW(CLKMODE, (temp | 0x20)); 437 438 /* powerdown both LVDS (laptop panellink) and TMDS (DVI panellink) transmitters */ 439 if (si->ps.tmds2_active) DAC2W(FP_DEBUG0, (DAC2R(FP_DEBUG0) | 0x30000000)); 440 441 LOG(4,("display off, ")); 442 } 443 444 if (h) 445 { 446 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0x7f)); 447 LOG(4,("hsync enabled, ")); 448 } 449 else 450 { 451 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x80)); 452 LOG(4,("hsync disabled, ")); 453 } 454 if (v) 455 { 456 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xbf)); 457 LOG(4,("vsync enabled\n")); 458 } 459 else 460 { 461 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x40)); 462 LOG(4,("vsync disabled\n")); 463 } 464 465 return B_OK; 466 } 467 468 status_t nv_crtc2_dpms_fetch(bool *display, bool *h, bool *v) 469 { 470 /* enable access to CRTC2 (and SEQUENCER2) */ 471 CRTC2W(OWNER, 0x03); 472 473 *display = !(SEQR(CLKMODE) & 0x20); 474 *h = !(CRTC2R(REPAINT1) & 0x80); 475 *v = !(CRTC2R(REPAINT1) & 0x40); 476 477 LOG(4,("CTRC2: fetched DPMS state:")); 478 if (display) LOG(4,("display on, ")); 479 else LOG(4,("display off, ")); 480 if (h) LOG(4,("hsync enabled, ")); 481 else LOG(4,("hsync disabled, ")); 482 if (v) LOG(4,("vsync enabled\n")); 483 else LOG(4,("vsync disabled\n")); 484 485 return B_OK; 486 } 487 488 status_t nv_crtc2_set_display_pitch() 489 { 490 uint32 offset; 491 492 LOG(4,("CRTC2: setting card pitch (offset between lines)\n")); 493 494 /* figure out offset value hardware needs */ 495 offset = si->fbc.bytes_per_row / 8; 496 497 LOG(2,("CRTC2: offset register set to: $%04x\n", offset)); 498 499 /* enable access to CRTC2 */ 500 CRTC2W(OWNER, 0x03); 501 502 /* program the card */ 503 CRTC2W(PITCHL, (offset & 0x00ff)); 504 CRTC2W(REPAINT0, ((CRTC2R(REPAINT0) & 0x1f) | ((offset & 0x0700) >> 3))); 505 506 return B_OK; 507 } 508 509 status_t nv_crtc2_set_display_start(uint32 startadd,uint8 bpp) 510 { 511 uint32 timeout = 0; 512 513 LOG(4,("CRTC2: setting card RAM to be displayed bpp %d\n", bpp)); 514 515 LOG(2,("CRTC2: startadd: $%08x\n", startadd)); 516 LOG(2,("CRTC2: frameRAM: $%08x\n", si->framebuffer)); 517 LOG(2,("CRTC2: framebuffer: $%08x\n", si->fbc.frame_buffer)); 518 519 /* we might have no retraces during setmode! */ 520 /* wait 25mS max. for retrace to occur (refresh > 40Hz) */ 521 while (((NV_REG32(NV32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) && 522 (timeout < (25000/10))) 523 { 524 /* don't snooze much longer or retrace might get missed! */ 525 snooze(10); 526 timeout++; 527 } 528 529 /* enable access to CRTC2 */ 530 CRTC2W(OWNER, 0x03); 531 532 /* upto 4Gb RAM adressing: must be used on NV10 and later! */ 533 /* NOTE: 534 * While this register also exists on pre-NV10 cards, it will 535 * wrap-around at 16Mb boundaries!! */ 536 537 /* 30bit adress in 32bit words */ 538 NV_REG32(NV32_NV10FB2STADD32) = (startadd & 0xfffffffc); 539 540 /* set byte adress: (b0 - 1) */ 541 ATB2W(HORPIXPAN, ((startadd & 0x00000003) << 1)); 542 543 return B_OK; 544 } 545 546 status_t nv_crtc2_cursor_init() 547 { 548 int i; 549 uint32 * fb; 550 /* cursor bitmap will be stored at the start of the framebuffer */ 551 const uint32 curadd = 0; 552 553 /* enable access to CRTC2 */ 554 CRTC2W(OWNER, 0x03); 555 556 /* set cursor bitmap adress ... */ 557 if (si->ps.laptop) 558 { 559 /* must be used this way on pre-NV10 and on all 'Go' cards! */ 560 561 /* cursorbitmap must start on 2Kbyte boundary: */ 562 /* set adress bit11-16, and set 'no doublescan' (registerbit 1 = 0) */ 563 CRTC2W(CURCTL0, ((curadd & 0x0001f800) >> 9)); 564 /* set adress bit17-23, and set graphics mode cursor(?) (registerbit 7 = 1) */ 565 CRTC2W(CURCTL1, (((curadd & 0x00fe0000) >> 17) | 0x80)); 566 /* set adress bit24-31 */ 567 CRTC2W(CURCTL2, ((curadd & 0xff000000) >> 24)); 568 } 569 else 570 { 571 /* upto 4Gb RAM adressing: 572 * can be used on NV10 and later (except for 'Go' cards)! */ 573 /* NOTE: 574 * This register does not exist on pre-NV10 and 'Go' cards. */ 575 576 /* cursorbitmap must still start on 2Kbyte boundary: */ 577 NV_REG32(NV32_NV10CUR2ADD32) = (curadd & 0xfffff800); 578 } 579 580 /* set cursor colour: not needed because of direct nature of cursor bitmap. */ 581 582 /*clear cursor*/ 583 fb = (uint32 *) si->framebuffer + curadd; 584 for (i=0;i<(2048/4);i++) 585 { 586 fb[i]=0; 587 } 588 589 /* select 32x32 pixel, 16bit color cursorbitmap, no doublescan */ 590 NV_REG32(NV32_2CURCONF) = 0x02000100; 591 592 /* activate hardware cursor */ 593 nv_crtc2_cursor_show(); 594 595 return B_OK; 596 } 597 598 status_t nv_crtc2_cursor_show() 599 { 600 LOG(4,("CRTC2: enabling cursor\n")); 601 602 /* enable access to CRTC2 */ 603 CRTC2W(OWNER, 0x03); 604 605 /* b0 = 1 enables cursor */ 606 CRTC2W(CURCTL0, (CRTC2R(CURCTL0) | 0x01)); 607 608 return B_OK; 609 } 610 611 status_t nv_crtc2_cursor_hide() 612 { 613 LOG(4,("CRTC2: disabling cursor\n")); 614 615 /* enable access to CRTC2 */ 616 CRTC2W(OWNER, 0x03); 617 618 /* b0 = 0 disables cursor */ 619 CRTC2W(CURCTL0, (CRTC2R(CURCTL0) & 0xfe)); 620 621 return B_OK; 622 } 623 624 /*set up cursor shape*/ 625 status_t nv_crtc2_cursor_define(uint8* andMask,uint8* xorMask) 626 { 627 int x, y; 628 uint8 b; 629 uint16 *cursor; 630 uint16 pixel; 631 632 /* get a pointer to the cursor */ 633 cursor = (uint16*) si->framebuffer; 634 635 /* draw the cursor */ 636 /* (Nvidia cards have a RGB15 direct color cursor bitmap, bit #16 is transparancy) */ 637 for (y = 0; y < 16; y++) 638 { 639 b = 0x80; 640 for (x = 0; x < 8; x++) 641 { 642 /* preset transparant */ 643 pixel = 0x0000; 644 /* set white if requested */ 645 if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; 646 /* set black if requested */ 647 if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; 648 /* set invert if requested */ 649 if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; 650 /* place the pixel in the bitmap */ 651 cursor[x + (y * 32)] = pixel; 652 b >>= 1; 653 } 654 xorMask++; 655 andMask++; 656 b = 0x80; 657 for (; x < 16; x++) 658 { 659 /* preset transparant */ 660 pixel = 0x0000; 661 /* set white if requested */ 662 if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; 663 /* set black if requested */ 664 if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; 665 /* set invert if requested */ 666 if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; 667 /* place the pixel in the bitmap */ 668 cursor[x + (y * 32)] = pixel; 669 b >>= 1; 670 } 671 xorMask++; 672 andMask++; 673 } 674 675 return B_OK; 676 } 677 678 /* position the cursor */ 679 status_t nv_crtc2_cursor_position(uint16 x, uint16 y) 680 { 681 uint16 yhigh; 682 683 /* make sure we are beyond the first line of the cursorbitmap being drawn during 684 * updating the position to prevent distortions: no double buffering feature */ 685 /* Note: 686 * we need to return as quick as possible or some apps will exhibit lagging.. */ 687 688 /* read the old cursor Y position */ 689 yhigh = ((DAC2R(CURPOS) & 0x0fff0000) >> 16); 690 /* make sure we will wait until we are below both the old and new Y position: 691 * visible cursorbitmap drawing needs to be done at least... */ 692 if (y > yhigh) yhigh = y; 693 694 if (yhigh < (si->dm.timing.v_display - 16)) 695 { 696 /* we have vertical lines below old and new cursorposition to spare. So we 697 * update the cursor postion 'mid-screen', but below that area. */ 698 while (((uint16)(NV_REG32(NV32_RASTER2) & 0x000007ff)) < (yhigh + 16)) 699 { 700 snooze(10); 701 } 702 } 703 else 704 { 705 /* no room to spare, just wait for retrace (is relatively slow) */ 706 while ((NV_REG32(NV32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) 707 { 708 /* don't snooze much longer or retrace might get missed! */ 709 snooze(10); 710 } 711 } 712 713 /* update cursorposition */ 714 DAC2W(CURPOS, ((x & 0x0fff) | ((y & 0x0fff) << 16))); 715 716 return B_OK; 717 } 718