1 /* second CTRC functionality for GeForce cards */ 2 /* Author: 3 Rudolf Cornelissen 11/2002-4/2004 4 */ 5 6 #define MODULE_BIT 0x00020000 7 8 #include "nv_std.h" 9 10 /*Adjust passed parameters to a valid mode line*/ 11 status_t nv_crtc2_validate_timing( 12 uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht, 13 uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt 14 ) 15 { 16 /* horizontal */ 17 /* make all parameters multiples of 8 */ 18 *hd_e &= 0xfff8; 19 *hs_s &= 0xfff8; 20 *hs_e &= 0xfff8; 21 *ht &= 0xfff8; 22 23 /* confine to required number of bits, taking logic into account */ 24 if (*hd_e > ((0x01ff - 2) << 3)) *hd_e = ((0x01ff - 2) << 3); 25 if (*hs_s > ((0x01ff - 1) << 3)) *hs_s = ((0x01ff - 1) << 3); 26 if (*hs_e > ( 0x01ff << 3)) *hs_e = ( 0x01ff << 3); 27 if (*ht > ((0x01ff + 5) << 3)) *ht = ((0x01ff + 5) << 3); 28 29 /* NOTE: keep horizontal timing at multiples of 8! */ 30 /* confine to a reasonable width */ 31 if (*hd_e < 640) *hd_e = 640; 32 if (*hd_e > 2048) *hd_e = 2048; 33 34 /* if hor. total does not leave room for a sensible sync pulse, increase it! */ 35 if (*ht < (*hd_e + 80)) *ht = (*hd_e + 80); 36 37 /* make sure sync pulse is not during display */ 38 if (*hs_e > (*ht - 8)) *hs_e = (*ht - 8); 39 if (*hs_s < (*hd_e + 8)) *hs_s = (*hd_e + 8); 40 41 /* correct sync pulse if it is too long: 42 * there are only 5 bits available to save this in the card registers! */ 43 if (*hs_e > (*hs_s + 0xf8)) *hs_e = (*hs_s + 0xf8); 44 45 /*vertical*/ 46 /* confine to required number of bits, taking logic into account */ 47 //fixme if needed: on GeForce cards there are 12 instead of 11 bits... 48 if (*vd_e > (0x7ff - 2)) *vd_e = (0x7ff - 2); 49 if (*vs_s > (0x7ff - 1)) *vs_s = (0x7ff - 1); 50 if (*vs_e > 0x7ff ) *vs_e = 0x7ff ; 51 if (*vt > (0x7ff + 2)) *vt = (0x7ff + 2); 52 53 /* confine to a reasonable height */ 54 if (*vd_e < 480) *vd_e = 480; 55 if (*vd_e > 1536) *vd_e = 1536; 56 57 /*if vertical total does not leave room for a sync pulse, increase it!*/ 58 if (*vt < (*vd_e + 3)) *vt = (*vd_e + 3); 59 60 /* make sure sync pulse is not during display */ 61 if (*vs_e > (*vt - 1)) *vs_e = (*vt - 1); 62 if (*vs_s < (*vd_e + 1)) *vs_s = (*vd_e + 1); 63 64 /* correct sync pulse if it is too long: 65 * there are only 4 bits available to save this in the card registers! */ 66 if (*vs_e > (*vs_s + 0x0f)) *vs_e = (*vs_s + 0x0f); 67 68 return B_OK; 69 } 70 71 /*set a mode line - inputs are in pixels*/ 72 status_t nv_crtc2_set_timing(display_mode target) 73 { 74 uint8 temp; 75 76 uint32 htotal; /*total horizontal total VCLKs*/ 77 uint32 hdisp_e; /*end of horizontal display (begins at 0)*/ 78 uint32 hsync_s; /*begin of horizontal sync pulse*/ 79 uint32 hsync_e; /*end of horizontal sync pulse*/ 80 uint32 hblnk_s; /*begin horizontal blanking*/ 81 uint32 hblnk_e; /*end horizontal blanking*/ 82 83 uint32 vtotal; /*total vertical total scanlines*/ 84 uint32 vdisp_e; /*end of vertical display*/ 85 uint32 vsync_s; /*begin of vertical sync pulse*/ 86 uint32 vsync_e; /*end of vertical sync pulse*/ 87 uint32 vblnk_s; /*begin vertical blanking*/ 88 uint32 vblnk_e; /*end vertical blanking*/ 89 90 uint32 linecomp; /*split screen and vdisp_e interrupt*/ 91 92 LOG(4,("CRTC2: setting timing\n")); 93 94 /* setup fixed modeline for flatpanel if connected and active */ 95 if (si->ps.tmds2_active) 96 { 97 LOG(2,("CRTC2: DFP active: tuning modeline\n")); 98 99 /* horizontal timing */ 100 //fixme (?): maybe we need real modeline calculations here... 101 //testing (640x480): total = 135% is too much, 120% to small... 102 target.timing.h_total = target.timing.h_display + 160;//128 103 target.timing.h_sync_start = target.timing.h_total - 144;//112 104 target.timing.h_sync_end = target.timing.h_total - 48;//16 105 106 /* vertical timing */ 107 target.timing.v_total = target.timing.v_display + 6; 108 target.timing.v_sync_start = target.timing.v_total - 3; 109 target.timing.v_sync_end = target.timing.v_total - 2; 110 111 /* disable GPU scaling testmode so automatic scaling will be done */ 112 DAC2W(FP_DEBUG1, 0); 113 } 114 115 /* Modify parameters as required by standard VGA */ 116 htotal = ((target.timing.h_total >> 3) - 5); 117 hdisp_e = ((target.timing.h_display >> 3) - 1); 118 hblnk_s = hdisp_e; 119 hblnk_e = (htotal + 4);//0; 120 hsync_s = (target.timing.h_sync_start >> 3); 121 hsync_e = (target.timing.h_sync_end >> 3); 122 123 vtotal = target.timing.v_total - 2; 124 vdisp_e = target.timing.v_display - 1; 125 vblnk_s = vdisp_e; 126 vblnk_e = (vtotal + 1); 127 vsync_s = target.timing.v_sync_start;//-1; 128 vsync_e = target.timing.v_sync_end;//-1; 129 130 /* prevent memory adress counter from being reset (linecomp may not occur) */ 131 linecomp = target.timing.v_display; 132 133 /* enable access to secondary head */ 134 set_crtc_owner(1); 135 136 /* Note for laptop and DVI flatpanels: 137 * CRTC timing has a seperate set of registers from flatpanel timing. 138 * The flatpanel timing registers have scaling registers that are used to match 139 * these two modelines. */ 140 { 141 LOG(4,("CRTC2: Setting full timing...\n")); 142 143 /* log the mode that will be set */ 144 LOG(2,("CRTC2:\n\tHTOT:%x\n\tHDISPEND:%x\n\tHBLNKS:%x\n\tHBLNKE:%x\n\tHSYNCS:%x\n\tHSYNCE:%x\n\t",htotal,hdisp_e,hblnk_s,hblnk_e,hsync_s,hsync_e)); 145 LOG(2,("VTOT:%x\n\tVDISPEND:%x\n\tVBLNKS:%x\n\tVBLNKE:%x\n\tVSYNCS:%x\n\tVSYNCE:%x\n",vtotal,vdisp_e,vblnk_s,vblnk_e,vsync_s,vsync_e)); 146 147 /* actually program the card! */ 148 /* unlock CRTC registers at index 0-7 */ 149 CRTC2W(VSYNCE, (CRTC2R(VSYNCE) & 0x7f)); 150 /* horizontal standard VGA regs */ 151 CRTC2W(HTOTAL, (htotal & 0xff)); 152 CRTC2W(HDISPE, (hdisp_e & 0xff)); 153 CRTC2W(HBLANKS, (hblnk_s & 0xff)); 154 /* also unlock vertical retrace registers in advance */ 155 CRTC2W(HBLANKE, ((hblnk_e & 0x1f) | 0x80)); 156 CRTC2W(HSYNCS, (hsync_s & 0xff)); 157 CRTC2W(HSYNCE, ((hsync_e & 0x1f) | ((hblnk_e & 0x20) << 2))); 158 159 /* vertical standard VGA regs */ 160 CRTC2W(VTOTAL, (vtotal & 0xff)); 161 CRTC2W(OVERFLOW, 162 ( 163 ((vtotal & 0x100) >> (8 - 0)) | ((vtotal & 0x200) >> (9 - 5)) | 164 ((vdisp_e & 0x100) >> (8 - 1)) | ((vdisp_e & 0x200) >> (9 - 6)) | 165 ((vsync_s & 0x100) >> (8 - 2)) | ((vsync_s & 0x200) >> (9 - 7)) | 166 ((vblnk_s & 0x100) >> (8 - 3)) | ((linecomp & 0x100) >> (8 - 4)) 167 )); 168 CRTC2W(PRROWSCN, 0x00); /* not used */ 169 CRTC2W(MAXSCLIN, (((vblnk_s & 0x200) >> (9 - 5)) | ((linecomp & 0x200) >> (9 - 6)))); 170 CRTC2W(VSYNCS, (vsync_s & 0xff)); 171 CRTC2W(VSYNCE, ((CRTC2R(VSYNCE) & 0xf0) | (vsync_e & 0x0f))); 172 CRTC2W(VDISPE, (vdisp_e & 0xff)); 173 CRTC2W(VBLANKS, (vblnk_s & 0xff)); 174 CRTC2W(VBLANKE, (vblnk_e & 0xff)); 175 CRTC2W(LINECOMP, (linecomp & 0xff)); 176 177 /* horizontal extended regs */ 178 //fixme: we reset bit4. is this correct?? 179 CRTC2W(HEB, (CRTC2R(HEB) & 0xe0) | 180 ( 181 ((htotal & 0x100) >> (8 - 0)) | 182 ((hdisp_e & 0x100) >> (8 - 1)) | 183 ((hblnk_s & 0x100) >> (8 - 2)) | 184 ((hsync_s & 0x100) >> (8 - 3)) 185 )); 186 187 /* (mostly) vertical extended regs */ 188 CRTC2W(LSR, 189 ( 190 ((vtotal & 0x400) >> (10 - 0)) | 191 ((vdisp_e & 0x400) >> (10 - 1)) | 192 ((vsync_s & 0x400) >> (10 - 2)) | 193 ((vblnk_s & 0x400) >> (10 - 3)) | 194 ((hblnk_e & 0x040) >> (6 - 4)) 195 //fixme: we still miss one linecomp bit!?! is this it?? 196 //| ((linecomp & 0x400) >> 3) 197 )); 198 199 /* more vertical extended regs */ 200 CRTC2W(EXTRA, 201 ( 202 ((vtotal & 0x800) >> (11 - 0)) | 203 ((vdisp_e & 0x800) >> (11 - 2)) | 204 ((vsync_s & 0x800) >> (11 - 4)) | 205 ((vblnk_s & 0x800) >> (11 - 6)) 206 //fixme: do we miss another linecomp bit!?! 207 )); 208 209 /* setup 'large screen' mode */ 210 if (target.timing.h_display >= 1280) 211 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xfb)); 212 else 213 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x04)); 214 215 /* setup HSYNC & VSYNC polarity */ 216 LOG(2,("CRTC2: sync polarity: ")); 217 temp = NV_REG8(NV8_MISCR); 218 if (target.timing.flags & B_POSITIVE_HSYNC) 219 { 220 LOG(2,("H:pos ")); 221 temp &= ~0x40; 222 } 223 else 224 { 225 LOG(2,("H:neg ")); 226 temp |= 0x40; 227 } 228 if (target.timing.flags & B_POSITIVE_VSYNC) 229 { 230 LOG(2,("V:pos ")); 231 temp &= ~0x80; 232 } 233 else 234 { 235 LOG(2,("V:neg ")); 236 temp |= 0x80; 237 } 238 NV_REG8(NV8_MISCW) = temp; 239 240 LOG(2,(", MISC reg readback: $%02x\n", NV_REG8(NV8_MISCR))); 241 } 242 243 /* always disable interlaced operation */ 244 /* (interlace is supported on upto and including NV10, NV15, and NV30 and up) */ 245 CRTC2W(INTERLACE, 0xff); 246 247 /* setup flatpanel if connected and active */ 248 if (si->ps.tmds2_active) 249 { 250 uint32 iscale_x, iscale_y; 251 252 /* calculate inverse scaling factors used by hardware in 20.12 format */ 253 iscale_x = (((1 << 12) * target.timing.h_display) / si->ps.panel2_width); 254 iscale_y = (((1 << 12) * target.timing.v_display) / si->ps.panel2_height); 255 256 /* unblock flatpanel timing programming (or something like that..) */ 257 CRTC2W(FP_HTIMING, 0); 258 CRTC2W(FP_VTIMING, 0); 259 LOG(2,("CRTC2: FP_HTIMING reg readback: $%02x\n", CRTC2R(FP_HTIMING))); 260 LOG(2,("CRTC2: FP_VTIMING reg readback: $%02x\n", CRTC2R(FP_VTIMING))); 261 262 /* enable full width visibility on flatpanel */ 263 DAC2W(FP_HVALID_S, 0); 264 DAC2W(FP_HVALID_E, (si->ps.panel2_width - 1)); 265 /* enable full height visibility on flatpanel */ 266 DAC2W(FP_VVALID_S, 0); 267 DAC2W(FP_VVALID_E, (si->ps.panel2_height - 1)); 268 269 /* nVidia cards support upscaling except on ??? */ 270 /* NV11 cards can upscale after all! */ 271 if (0)//si->ps.card_type == NV11) 272 { 273 /* disable last fetched line limiting */ 274 DAC2W(FP_DEBUG2, 0x00000000); 275 /* inform panel to scale if needed */ 276 if ((iscale_x != (1 << 12)) || (iscale_y != (1 << 12))) 277 { 278 LOG(2,("CRTC2: DFP needs to do scaling\n")); 279 DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) | 0x00000100)); 280 } 281 else 282 { 283 LOG(2,("CRTC2: no scaling for DFP needed\n")); 284 DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) & 0xfffffeff)); 285 } 286 } 287 else 288 { 289 float dm_aspect; 290 291 LOG(2,("CRTC2: GPU scales for DFP if needed\n")); 292 293 /* calculate display mode aspect */ 294 dm_aspect = (target.timing.h_display / ((float)target.timing.v_display)); 295 296 /* limit last fetched line if vertical scaling is done */ 297 if (iscale_y != (1 << 12)) 298 DAC2W(FP_DEBUG2, ((1 << 28) | ((target.timing.v_display - 1) << 16))); 299 else 300 DAC2W(FP_DEBUG2, 0x00000000); 301 302 /* inform panel not to scale */ 303 DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) & 0xfffffeff)); 304 305 /* GPU scaling is automatically setup by hardware, so only modify this 306 * scalingfactor for non 4:3 (1.33) aspect panels; 307 * let's consider 1280x1024 1:33 aspect (it's 1.25 aspect actually!) */ 308 309 /* correct for widescreen panels relative to mode... 310 * (so if panel is more widescreen than mode being set) */ 311 /* BTW: known widescreen panels: 312 * 1280 x 800 (1.60), 313 * 1440 x 900 (1.60), 314 * 1680 x 1050 (1.60). */ 315 /* known 4:3 aspect non-standard resolution panels: 316 * 1400 x 1050 (1.33). */ 317 /* NOTE: 318 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */ 319 if ((iscale_x != (1 << 12)) && (si->ps.panel2_aspect > (dm_aspect + 0.10))) 320 { 321 uint16 diff; 322 323 LOG(2,("CRTC2: (relative) widescreen panel: tuning horizontal scaling\n")); 324 325 /* X-scaling should be the same as Y-scaling */ 326 iscale_x = iscale_y; 327 /* enable testmode (b12) and program new X-scaling factor */ 328 DAC2W(FP_DEBUG1, (((iscale_x >> 1) & 0x00000fff) | (1 << 12))); 329 /* center/cut-off left and right side of screen */ 330 diff = ((si->ps.panel2_width - 331 (target.timing.h_display * ((1 << 12) / ((float)iscale_x)))) 332 / 2); 333 DAC2W(FP_HVALID_S, diff); 334 DAC2W(FP_HVALID_E, ((si->ps.panel2_width - diff) - 1)); 335 } 336 /* correct for portrait panels... */ 337 /* NOTE: 338 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */ 339 if ((iscale_y != (1 << 12)) && (si->ps.panel2_aspect < (dm_aspect - 0.10))) 340 { 341 LOG(2,("CRTC2: (relative) portrait panel: should tune vertical scaling\n")); 342 /* fixme: implement if this kind of portrait panels exist on nVidia... */ 343 } 344 } 345 346 /* do some logging.. */ 347 LOG(2,("CRTC2: FP_HVALID_S reg readback: $%08x\n", DAC2R(FP_HVALID_S))); 348 LOG(2,("CRTC2: FP_HVALID_E reg readback: $%08x\n", DAC2R(FP_HVALID_E))); 349 LOG(2,("CRTC2: FP_VVALID_S reg readback: $%08x\n", DAC2R(FP_VVALID_S))); 350 LOG(2,("CRTC2: FP_VVALID_E reg readback: $%08x\n", DAC2R(FP_VVALID_E))); 351 LOG(2,("CRTC2: FP_DEBUG0 reg readback: $%08x\n", DAC2R(FP_DEBUG0))); 352 LOG(2,("CRTC2: FP_DEBUG1 reg readback: $%08x\n", DAC2R(FP_DEBUG1))); 353 LOG(2,("CRTC2: FP_DEBUG2 reg readback: $%08x\n", DAC2R(FP_DEBUG2))); 354 LOG(2,("CRTC2: FP_DEBUG3 reg readback: $%08x\n", DAC2R(FP_DEBUG3))); 355 LOG(2,("CRTC2: FP_TG_CTRL reg readback: $%08x\n", DAC2R(FP_TG_CTRL))); 356 } 357 358 return B_OK; 359 } 360 361 status_t nv_crtc2_depth(int mode) 362 { 363 uint8 viddelay = 0; 364 uint32 genctrl = 0; 365 366 /* set VCLK scaling */ 367 switch(mode) 368 { 369 case BPP8: 370 viddelay = 0x01; 371 /* genctrl b4 & b5 reset: 'direct mode' */ 372 genctrl = 0x00101100; 373 break; 374 case BPP15: 375 viddelay = 0x02; 376 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 377 genctrl = 0x00100130; 378 break; 379 case BPP16: 380 viddelay = 0x02; 381 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 382 genctrl = 0x00101130; 383 break; 384 case BPP24: 385 viddelay = 0x03; 386 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 387 genctrl = 0x00100130; 388 break; 389 case BPP32: 390 viddelay = 0x03; 391 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 392 genctrl = 0x00101130; 393 break; 394 } 395 /* enable access to secondary head */ 396 set_crtc_owner(1); 397 398 CRTC2W(PIXEL, ((CRTC2R(PIXEL) & 0xfc) | viddelay)); 399 DAC2W(GENCTRL, genctrl); 400 401 return B_OK; 402 } 403 404 status_t nv_crtc2_dpms(bool display, bool h, bool v) 405 { 406 uint8 temp; 407 408 LOG(4,("CRTC2: setting DPMS: ")); 409 410 /* enable access to secondary head */ 411 set_crtc_owner(1); 412 413 /* start synchronous reset: required before turning screen off! */ 414 SEQW(RESET, 0x01); 415 416 /* turn screen off */ 417 temp = SEQR(CLKMODE); 418 if (display) 419 { 420 SEQW(CLKMODE, (temp & ~0x20)); 421 422 /* end synchronous reset if display should be enabled */ 423 SEQW(RESET, 0x03); 424 425 //'safe mode' test! feedback needed with this 'setting'! 426 if (0)//si->ps.tmds2_active) 427 { 428 /* powerup both LVDS (laptop panellink) and TMDS (DVI panellink) 429 * internal transmitters... */ 430 /* note: 431 * the powerbits in this register are hardwired to the DVI connectors, 432 * instead of to the DACs! (confirmed NV34) */ 433 //fixme... 434 DAC2W(FP_DEBUG0, (DAC2R(FP_DEBUG0) & 0xcfffffff)); 435 /* ... and powerup external TMDS transmitter if it exists */ 436 /* (confirmed OK on NV28 and NV34) */ 437 CRTC2W(0x59, (CRTC2R(0x59) | 0x01)); 438 } 439 440 LOG(4,("display on, ")); 441 } 442 else 443 { 444 SEQW(CLKMODE, (temp | 0x20)); 445 446 //'safe mode' test! feedback needed with this 'setting'! 447 if (0)//si->ps.tmds2_active) 448 { 449 /* powerdown both LVDS (laptop panellink) and TMDS (DVI panellink) 450 * internal transmitters... */ 451 /* note: 452 * the powerbits in this register are hardwired to the DVI connectors, 453 * instead of to the DACs! (confirmed NV34) */ 454 //fixme... 455 DAC2W(FP_DEBUG0, (DAC2R(FP_DEBUG0) | 0x30000000)); 456 /* ... and powerdown external TMDS transmitter if it exists */ 457 /* (confirmed OK on NV28 and NV34) */ 458 CRTC2W(0x59, (CRTC2R(0x59) & 0xfe)); 459 } 460 461 LOG(4,("display off, ")); 462 } 463 464 if (h) 465 { 466 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0x7f)); 467 LOG(4,("hsync enabled, ")); 468 } 469 else 470 { 471 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x80)); 472 LOG(4,("hsync disabled, ")); 473 } 474 if (v) 475 { 476 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xbf)); 477 LOG(4,("vsync enabled\n")); 478 } 479 else 480 { 481 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x40)); 482 LOG(4,("vsync disabled\n")); 483 } 484 485 return B_OK; 486 } 487 488 status_t nv_crtc2_dpms_fetch(bool *display, bool *h, bool *v) 489 { 490 /* enable access to secondary head */ 491 set_crtc_owner(1); 492 493 *display = !(SEQR(CLKMODE) & 0x20); 494 *h = !(CRTC2R(REPAINT1) & 0x80); 495 *v = !(CRTC2R(REPAINT1) & 0x40); 496 497 LOG(4,("CTRC2: fetched DPMS state:")); 498 if (display) LOG(4,("display on, ")); 499 else LOG(4,("display off, ")); 500 if (h) LOG(4,("hsync enabled, ")); 501 else LOG(4,("hsync disabled, ")); 502 if (v) LOG(4,("vsync enabled\n")); 503 else LOG(4,("vsync disabled\n")); 504 505 return B_OK; 506 } 507 508 status_t nv_crtc2_set_display_pitch() 509 { 510 uint32 offset; 511 512 LOG(4,("CRTC2: setting card pitch (offset between lines)\n")); 513 514 /* figure out offset value hardware needs */ 515 offset = si->fbc.bytes_per_row / 8; 516 517 LOG(2,("CRTC2: offset register set to: $%04x\n", offset)); 518 519 /* enable access to secondary head */ 520 set_crtc_owner(1); 521 522 /* program the card */ 523 CRTC2W(PITCHL, (offset & 0x00ff)); 524 CRTC2W(REPAINT0, ((CRTC2R(REPAINT0) & 0x1f) | ((offset & 0x0700) >> 3))); 525 526 return B_OK; 527 } 528 529 status_t nv_crtc2_set_display_start(uint32 startadd,uint8 bpp) 530 { 531 uint32 timeout = 0; 532 533 LOG(4,("CRTC2: setting card RAM to be displayed bpp %d\n", bpp)); 534 535 LOG(2,("CRTC2: startadd: $%08x\n", startadd)); 536 LOG(2,("CRTC2: frameRAM: $%08x\n", si->framebuffer)); 537 LOG(2,("CRTC2: framebuffer: $%08x\n", si->fbc.frame_buffer)); 538 539 /* we might have no retraces during setmode! */ 540 /* wait 25mS max. for retrace to occur (refresh > 40Hz) */ 541 while (((NV_REG32(NV32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) && 542 (timeout < (25000/10))) 543 { 544 /* don't snooze much longer or retrace might get missed! */ 545 snooze(10); 546 timeout++; 547 } 548 549 /* enable access to secondary head */ 550 set_crtc_owner(1); 551 552 /* upto 4Gb RAM adressing: must be used on NV10 and later! */ 553 /* NOTE: 554 * While this register also exists on pre-NV10 cards, it will 555 * wrap-around at 16Mb boundaries!! */ 556 557 /* 30bit adress in 32bit words */ 558 NV_REG32(NV32_NV10FB2STADD32) = (startadd & 0xfffffffc); 559 560 /* set byte adress: (b0 - 1) */ 561 ATB2W(HORPIXPAN, ((startadd & 0x00000003) << 1)); 562 563 return B_OK; 564 } 565 566 status_t nv_crtc2_cursor_init() 567 { 568 int i; 569 uint32 * fb; 570 /* cursor bitmap will be stored at the start of the framebuffer */ 571 const uint32 curadd = 0; 572 573 /* enable access to secondary head */ 574 set_crtc_owner(1); 575 576 /* set cursor bitmap adress ... */ 577 if (si->ps.laptop) 578 { 579 /* must be used this way on pre-NV10 and on all 'Go' cards! */ 580 581 /* cursorbitmap must start on 2Kbyte boundary: */ 582 /* set adress bit11-16, and set 'no doublescan' (registerbit 1 = 0) */ 583 CRTC2W(CURCTL0, ((curadd & 0x0001f800) >> 9)); 584 /* set adress bit17-23, and set graphics mode cursor(?) (registerbit 7 = 1) */ 585 CRTC2W(CURCTL1, (((curadd & 0x00fe0000) >> 17) | 0x80)); 586 /* set adress bit24-31 */ 587 CRTC2W(CURCTL2, ((curadd & 0xff000000) >> 24)); 588 } 589 else 590 { 591 /* upto 4Gb RAM adressing: 592 * can be used on NV10 and later (except for 'Go' cards)! */ 593 /* NOTE: 594 * This register does not exist on pre-NV10 and 'Go' cards. */ 595 596 /* cursorbitmap must still start on 2Kbyte boundary: */ 597 NV_REG32(NV32_NV10CUR2ADD32) = (curadd & 0xfffff800); 598 } 599 600 /* set cursor colour: not needed because of direct nature of cursor bitmap. */ 601 602 /*clear cursor*/ 603 fb = (uint32 *) si->framebuffer + curadd; 604 for (i=0;i<(2048/4);i++) 605 { 606 fb[i]=0; 607 } 608 609 /* select 32x32 pixel, 16bit color cursorbitmap, no doublescan */ 610 NV_REG32(NV32_2CURCONF) = 0x02000100; 611 612 /* activate hardware cursor */ 613 nv_crtc2_cursor_show(); 614 615 return B_OK; 616 } 617 618 status_t nv_crtc2_cursor_show() 619 { 620 LOG(4,("CRTC2: enabling cursor\n")); 621 622 /* enable access to secondary head */ 623 set_crtc_owner(1); 624 625 /* b0 = 1 enables cursor */ 626 CRTC2W(CURCTL0, (CRTC2R(CURCTL0) | 0x01)); 627 628 return B_OK; 629 } 630 631 status_t nv_crtc2_cursor_hide() 632 { 633 LOG(4,("CRTC2: disabling cursor\n")); 634 635 /* enable access to secondary head */ 636 set_crtc_owner(1); 637 638 /* b0 = 0 disables cursor */ 639 CRTC2W(CURCTL0, (CRTC2R(CURCTL0) & 0xfe)); 640 641 return B_OK; 642 } 643 644 /*set up cursor shape*/ 645 status_t nv_crtc2_cursor_define(uint8* andMask,uint8* xorMask) 646 { 647 int x, y; 648 uint8 b; 649 uint16 *cursor; 650 uint16 pixel; 651 652 /* get a pointer to the cursor */ 653 cursor = (uint16*) si->framebuffer; 654 655 /* draw the cursor */ 656 /* (Nvidia cards have a RGB15 direct color cursor bitmap, bit #16 is transparancy) */ 657 for (y = 0; y < 16; y++) 658 { 659 b = 0x80; 660 for (x = 0; x < 8; x++) 661 { 662 /* preset transparant */ 663 pixel = 0x0000; 664 /* set white if requested */ 665 if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; 666 /* set black if requested */ 667 if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; 668 /* set invert if requested */ 669 if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; 670 /* place the pixel in the bitmap */ 671 cursor[x + (y * 32)] = pixel; 672 b >>= 1; 673 } 674 xorMask++; 675 andMask++; 676 b = 0x80; 677 for (; x < 16; x++) 678 { 679 /* preset transparant */ 680 pixel = 0x0000; 681 /* set white if requested */ 682 if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; 683 /* set black if requested */ 684 if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; 685 /* set invert if requested */ 686 if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; 687 /* place the pixel in the bitmap */ 688 cursor[x + (y * 32)] = pixel; 689 b >>= 1; 690 } 691 xorMask++; 692 andMask++; 693 } 694 695 return B_OK; 696 } 697 698 /* position the cursor */ 699 status_t nv_crtc2_cursor_position(uint16 x, uint16 y) 700 { 701 uint16 yhigh; 702 703 /* make sure we are beyond the first line of the cursorbitmap being drawn during 704 * updating the position to prevent distortions: no double buffering feature */ 705 /* Note: 706 * we need to return as quick as possible or some apps will exhibit lagging.. */ 707 708 /* read the old cursor Y position */ 709 yhigh = ((DAC2R(CURPOS) & 0x0fff0000) >> 16); 710 /* make sure we will wait until we are below both the old and new Y position: 711 * visible cursorbitmap drawing needs to be done at least... */ 712 if (y > yhigh) yhigh = y; 713 714 if (yhigh < (si->dm.timing.v_display - 16)) 715 { 716 /* we have vertical lines below old and new cursorposition to spare. So we 717 * update the cursor postion 'mid-screen', but below that area. */ 718 while (((uint16)(NV_REG32(NV32_RASTER2) & 0x000007ff)) < (yhigh + 16)) 719 { 720 snooze(10); 721 } 722 } 723 else 724 { 725 /* no room to spare, just wait for retrace (is relatively slow) */ 726 while ((NV_REG32(NV32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) 727 { 728 /* don't snooze much longer or retrace might get missed! */ 729 snooze(10); 730 } 731 } 732 733 /* update cursorposition */ 734 DAC2W(CURPOS, ((x & 0x0fff) | ((y & 0x0fff) << 16))); 735 736 return B_OK; 737 } 738