1 /* second CTRC functionality for GeForce cards */ 2 /* Author: 3 Rudolf Cornelissen 11/2002-5/2004 4 */ 5 6 #define MODULE_BIT 0x00020000 7 8 #include "nv_std.h" 9 10 /*Adjust passed parameters to a valid mode line*/ 11 status_t nv_crtc2_validate_timing( 12 uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht, 13 uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt 14 ) 15 { 16 /* horizontal */ 17 /* make all parameters multiples of 8 */ 18 *hd_e &= 0xfff8; 19 *hs_s &= 0xfff8; 20 *hs_e &= 0xfff8; 21 *ht &= 0xfff8; 22 23 /* confine to required number of bits, taking logic into account */ 24 if (*hd_e > ((0x01ff - 2) << 3)) *hd_e = ((0x01ff - 2) << 3); 25 if (*hs_s > ((0x01ff - 1) << 3)) *hs_s = ((0x01ff - 1) << 3); 26 if (*hs_e > ( 0x01ff << 3)) *hs_e = ( 0x01ff << 3); 27 if (*ht > ((0x01ff + 5) << 3)) *ht = ((0x01ff + 5) << 3); 28 29 /* NOTE: keep horizontal timing at multiples of 8! */ 30 /* confine to a reasonable width */ 31 if (*hd_e < 640) *hd_e = 640; 32 if (*hd_e > 2048) *hd_e = 2048; 33 34 /* if hor. total does not leave room for a sensible sync pulse, increase it! */ 35 if (*ht < (*hd_e + 80)) *ht = (*hd_e + 80); 36 37 /* make sure sync pulse is not during display */ 38 if (*hs_e > (*ht - 8)) *hs_e = (*ht - 8); 39 if (*hs_s < (*hd_e + 8)) *hs_s = (*hd_e + 8); 40 41 /* correct sync pulse if it is too long: 42 * there are only 5 bits available to save this in the card registers! */ 43 if (*hs_e > (*hs_s + 0xf8)) *hs_e = (*hs_s + 0xf8); 44 45 /*vertical*/ 46 /* confine to required number of bits, taking logic into account */ 47 //fixme if needed: on GeForce cards there are 12 instead of 11 bits... 48 if (*vd_e > (0x7ff - 2)) *vd_e = (0x7ff - 2); 49 if (*vs_s > (0x7ff - 1)) *vs_s = (0x7ff - 1); 50 if (*vs_e > 0x7ff ) *vs_e = 0x7ff ; 51 if (*vt > (0x7ff + 2)) *vt = (0x7ff + 2); 52 53 /* confine to a reasonable height */ 54 if (*vd_e < 480) *vd_e = 480; 55 if (*vd_e > 1536) *vd_e = 1536; 56 57 /*if vertical total does not leave room for a sync pulse, increase it!*/ 58 if (*vt < (*vd_e + 3)) *vt = (*vd_e + 3); 59 60 /* make sure sync pulse is not during display */ 61 if (*vs_e > (*vt - 1)) *vs_e = (*vt - 1); 62 if (*vs_s < (*vd_e + 1)) *vs_s = (*vd_e + 1); 63 64 /* correct sync pulse if it is too long: 65 * there are only 4 bits available to save this in the card registers! */ 66 if (*vs_e > (*vs_s + 0x0f)) *vs_e = (*vs_s + 0x0f); 67 68 return B_OK; 69 } 70 71 /*set a mode line - inputs are in pixels*/ 72 status_t nv_crtc2_set_timing(display_mode target) 73 { 74 uint8 temp; 75 76 uint32 htotal; /*total horizontal total VCLKs*/ 77 uint32 hdisp_e; /*end of horizontal display (begins at 0)*/ 78 uint32 hsync_s; /*begin of horizontal sync pulse*/ 79 uint32 hsync_e; /*end of horizontal sync pulse*/ 80 uint32 hblnk_s; /*begin horizontal blanking*/ 81 uint32 hblnk_e; /*end horizontal blanking*/ 82 83 uint32 vtotal; /*total vertical total scanlines*/ 84 uint32 vdisp_e; /*end of vertical display*/ 85 uint32 vsync_s; /*begin of vertical sync pulse*/ 86 uint32 vsync_e; /*end of vertical sync pulse*/ 87 uint32 vblnk_s; /*begin vertical blanking*/ 88 uint32 vblnk_e; /*end vertical blanking*/ 89 90 uint32 linecomp; /*split screen and vdisp_e interrupt*/ 91 92 LOG(4,("CRTC2: setting timing\n")); 93 94 /* setup fixed modeline for flatpanel if connected and active */ 95 if (si->ps.tmds2_active) 96 { 97 display_mode p1, p2; 98 bool pan1, pan2; 99 100 LOG(2,("CRTC2: DFP active: tuning modeline\n")); 101 102 get_panel_modelines(&p1, &p2, &pan1, &pan2); 103 104 /* horizontal timing */ 105 //testing (640x480): total = 135% is too much, 120% to small... 106 //total = display + 160 equals panel modeline: but must be smaller...? 107 // target.timing.h_total = target.timing.h_display + 152;//160;//128 108 // target.timing.h_sync_start = target.timing.h_total - 136;//144;//112 109 // target.timing.h_sync_end = target.timing.h_total - 40;//48;//16 110 //adaptive to panel: fixme: test on 4:3 and 16:10 panels! 111 target.timing.h_sync_start = 112 ((uint16)((p2.timing.h_sync_start / ((float)p2.timing.h_display)) * 113 target.timing.h_display)) & 0xfff8; 114 115 target.timing.h_sync_end = 116 ((uint16)((p2.timing.h_sync_end / ((float)p2.timing.h_display)) * 117 target.timing.h_display)) & 0xfff8; 118 119 target.timing.h_total = 120 (((uint16)((p2.timing.h_total / ((float)p2.timing.h_display)) * 121 target.timing.h_display)) & 0xfff8) - 8; 122 123 if (target.timing.h_sync_start == target.timing.h_display) 124 target.timing.h_sync_start += 8; 125 if (target.timing.h_sync_end == target.timing.h_total) 126 target.timing.h_sync_end -= 8; 127 128 /* vertical timing */ 129 // target.timing.v_total = target.timing.v_display + 6; 130 // target.timing.v_sync_start = target.timing.v_total - 3; 131 // target.timing.v_sync_end = target.timing.v_total - 2; 132 target.timing.v_sync_start = 133 ((uint16)((p2.timing.v_sync_start / ((float)p2.timing.v_display)) * 134 target.timing.v_display)); 135 136 target.timing.v_sync_end = 137 ((uint16)((p2.timing.v_sync_end / ((float)p2.timing.v_display)) * 138 target.timing.v_display)); 139 140 target.timing.v_total = 141 ((uint16)((p2.timing.v_total / ((float)p2.timing.v_display)) * 142 target.timing.v_display)); 143 144 if (target.timing.v_sync_start == target.timing.v_display) 145 target.timing.v_sync_start += 1; 146 if (target.timing.v_sync_end == target.timing.v_total) 147 target.timing.v_sync_end -= 1; 148 149 /* disable GPU scaling testmode so automatic scaling will be done */ 150 DAC2W(FP_DEBUG1, 0); 151 } 152 153 /* Modify parameters as required by standard VGA */ 154 htotal = ((target.timing.h_total >> 3) - 5); 155 hdisp_e = ((target.timing.h_display >> 3) - 1); 156 hblnk_s = hdisp_e; 157 hblnk_e = (htotal + 4);//0; 158 hsync_s = (target.timing.h_sync_start >> 3); 159 hsync_e = (target.timing.h_sync_end >> 3); 160 161 vtotal = target.timing.v_total - 2; 162 vdisp_e = target.timing.v_display - 1; 163 vblnk_s = vdisp_e; 164 vblnk_e = (vtotal + 1); 165 vsync_s = target.timing.v_sync_start;//-1; 166 vsync_e = target.timing.v_sync_end;//-1; 167 168 /* prevent memory adress counter from being reset (linecomp may not occur) */ 169 linecomp = target.timing.v_display; 170 171 /* enable access to secondary head */ 172 set_crtc_owner(1); 173 174 /* Note for laptop and DVI flatpanels: 175 * CRTC timing has a seperate set of registers from flatpanel timing. 176 * The flatpanel timing registers have scaling registers that are used to match 177 * these two modelines. */ 178 { 179 LOG(4,("CRTC2: Setting full timing...\n")); 180 181 /* log the mode that will be set */ 182 LOG(2,("CRTC2:\n\tHTOT:%x\n\tHDISPEND:%x\n\tHBLNKS:%x\n\tHBLNKE:%x\n\tHSYNCS:%x\n\tHSYNCE:%x\n\t",htotal,hdisp_e,hblnk_s,hblnk_e,hsync_s,hsync_e)); 183 LOG(2,("VTOT:%x\n\tVDISPEND:%x\n\tVBLNKS:%x\n\tVBLNKE:%x\n\tVSYNCS:%x\n\tVSYNCE:%x\n",vtotal,vdisp_e,vblnk_s,vblnk_e,vsync_s,vsync_e)); 184 185 /* actually program the card! */ 186 /* unlock CRTC registers at index 0-7 */ 187 CRTC2W(VSYNCE, (CRTC2R(VSYNCE) & 0x7f)); 188 /* horizontal standard VGA regs */ 189 CRTC2W(HTOTAL, (htotal & 0xff)); 190 CRTC2W(HDISPE, (hdisp_e & 0xff)); 191 CRTC2W(HBLANKS, (hblnk_s & 0xff)); 192 /* also unlock vertical retrace registers in advance */ 193 CRTC2W(HBLANKE, ((hblnk_e & 0x1f) | 0x80)); 194 CRTC2W(HSYNCS, (hsync_s & 0xff)); 195 CRTC2W(HSYNCE, ((hsync_e & 0x1f) | ((hblnk_e & 0x20) << 2))); 196 197 /* vertical standard VGA regs */ 198 CRTC2W(VTOTAL, (vtotal & 0xff)); 199 CRTC2W(OVERFLOW, 200 ( 201 ((vtotal & 0x100) >> (8 - 0)) | ((vtotal & 0x200) >> (9 - 5)) | 202 ((vdisp_e & 0x100) >> (8 - 1)) | ((vdisp_e & 0x200) >> (9 - 6)) | 203 ((vsync_s & 0x100) >> (8 - 2)) | ((vsync_s & 0x200) >> (9 - 7)) | 204 ((vblnk_s & 0x100) >> (8 - 3)) | ((linecomp & 0x100) >> (8 - 4)) 205 )); 206 CRTC2W(PRROWSCN, 0x00); /* not used */ 207 CRTC2W(MAXSCLIN, (((vblnk_s & 0x200) >> (9 - 5)) | ((linecomp & 0x200) >> (9 - 6)))); 208 CRTC2W(VSYNCS, (vsync_s & 0xff)); 209 CRTC2W(VSYNCE, ((CRTC2R(VSYNCE) & 0xf0) | (vsync_e & 0x0f))); 210 CRTC2W(VDISPE, (vdisp_e & 0xff)); 211 CRTC2W(VBLANKS, (vblnk_s & 0xff)); 212 CRTC2W(VBLANKE, (vblnk_e & 0xff)); 213 CRTC2W(LINECOMP, (linecomp & 0xff)); 214 215 /* horizontal extended regs */ 216 //fixme: we reset bit4. is this correct?? 217 CRTC2W(HEB, (CRTC2R(HEB) & 0xe0) | 218 ( 219 ((htotal & 0x100) >> (8 - 0)) | 220 ((hdisp_e & 0x100) >> (8 - 1)) | 221 ((hblnk_s & 0x100) >> (8 - 2)) | 222 ((hsync_s & 0x100) >> (8 - 3)) 223 )); 224 225 /* (mostly) vertical extended regs */ 226 CRTC2W(LSR, 227 ( 228 ((vtotal & 0x400) >> (10 - 0)) | 229 ((vdisp_e & 0x400) >> (10 - 1)) | 230 ((vsync_s & 0x400) >> (10 - 2)) | 231 ((vblnk_s & 0x400) >> (10 - 3)) | 232 ((hblnk_e & 0x040) >> (6 - 4)) 233 //fixme: we still miss one linecomp bit!?! is this it?? 234 //| ((linecomp & 0x400) >> 3) 235 )); 236 237 /* more vertical extended regs */ 238 CRTC2W(EXTRA, 239 ( 240 ((vtotal & 0x800) >> (11 - 0)) | 241 ((vdisp_e & 0x800) >> (11 - 2)) | 242 ((vsync_s & 0x800) >> (11 - 4)) | 243 ((vblnk_s & 0x800) >> (11 - 6)) 244 //fixme: do we miss another linecomp bit!?! 245 )); 246 247 /* setup 'large screen' mode */ 248 if (target.timing.h_display >= 1280) 249 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xfb)); 250 else 251 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x04)); 252 253 /* setup HSYNC & VSYNC polarity */ 254 LOG(2,("CRTC2: sync polarity: ")); 255 temp = NV_REG8(NV8_MISCR); 256 if (target.timing.flags & B_POSITIVE_HSYNC) 257 { 258 LOG(2,("H:pos ")); 259 temp &= ~0x40; 260 } 261 else 262 { 263 LOG(2,("H:neg ")); 264 temp |= 0x40; 265 } 266 if (target.timing.flags & B_POSITIVE_VSYNC) 267 { 268 LOG(2,("V:pos ")); 269 temp &= ~0x80; 270 } 271 else 272 { 273 LOG(2,("V:neg ")); 274 temp |= 0x80; 275 } 276 NV_REG8(NV8_MISCW) = temp; 277 278 LOG(2,(", MISC reg readback: $%02x\n", NV_REG8(NV8_MISCR))); 279 } 280 281 /* always disable interlaced operation */ 282 /* (interlace is supported on upto and including NV10, NV15, and NV30 and up) */ 283 CRTC2W(INTERLACE, 0xff); 284 285 /* setup flatpanel if connected and active */ 286 if (si->ps.tmds2_active) 287 { 288 uint32 iscale_x, iscale_y; 289 290 /* calculate inverse scaling factors used by hardware in 20.12 format */ 291 iscale_x = (((1 << 12) * target.timing.h_display) / si->ps.p2_timing.h_display); 292 iscale_y = (((1 << 12) * target.timing.v_display) / si->ps.p2_timing.v_display); 293 294 /* unblock flatpanel timing programming (or something like that..) */ 295 CRTC2W(FP_HTIMING, 0); 296 CRTC2W(FP_VTIMING, 0); 297 LOG(2,("CRTC2: FP_HTIMING reg readback: $%02x\n", CRTC2R(FP_HTIMING))); 298 LOG(2,("CRTC2: FP_VTIMING reg readback: $%02x\n", CRTC2R(FP_VTIMING))); 299 300 /* enable full width visibility on flatpanel */ 301 DAC2W(FP_HVALID_S, 0); 302 DAC2W(FP_HVALID_E, (si->ps.p2_timing.h_display - 1)); 303 /* enable full height visibility on flatpanel */ 304 DAC2W(FP_VVALID_S, 0); 305 DAC2W(FP_VVALID_E, (si->ps.p2_timing.v_display - 1)); 306 307 /* nVidia cards support upscaling except on ??? */ 308 /* NV11 cards can upscale after all! */ 309 if (0)//si->ps.card_type == NV11) 310 { 311 /* disable last fetched line limiting */ 312 DAC2W(FP_DEBUG2, 0x00000000); 313 /* inform panel to scale if needed */ 314 if ((iscale_x != (1 << 12)) || (iscale_y != (1 << 12))) 315 { 316 LOG(2,("CRTC2: DFP needs to do scaling\n")); 317 DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) | 0x00000100)); 318 } 319 else 320 { 321 LOG(2,("CRTC2: no scaling for DFP needed\n")); 322 DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) & 0xfffffeff)); 323 } 324 } 325 else 326 { 327 float dm_aspect; 328 329 LOG(2,("CRTC2: GPU scales for DFP if needed\n")); 330 331 /* calculate display mode aspect */ 332 dm_aspect = (target.timing.h_display / ((float)target.timing.v_display)); 333 334 /* limit last fetched line if vertical scaling is done */ 335 if (iscale_y != (1 << 12)) 336 DAC2W(FP_DEBUG2, ((1 << 28) | ((target.timing.v_display - 1) << 16))); 337 else 338 DAC2W(FP_DEBUG2, 0x00000000); 339 340 /* inform panel not to scale */ 341 DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) & 0xfffffeff)); 342 343 /* GPU scaling is automatically setup by hardware, so only modify this 344 * scalingfactor for non 4:3 (1.33) aspect panels; 345 * let's consider 1280x1024 1:33 aspect (it's 1.25 aspect actually!) */ 346 347 /* correct for widescreen panels relative to mode... 348 * (so if panel is more widescreen than mode being set) */ 349 /* BTW: known widescreen panels: 350 * 1280 x 800 (1.60), 351 * 1440 x 900 (1.60), 352 * 1680 x 1050 (1.60). */ 353 /* known 4:3 aspect non-standard resolution panels: 354 * 1400 x 1050 (1.33). */ 355 /* NOTE: 356 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */ 357 if ((iscale_x != (1 << 12)) && (si->ps.panel2_aspect > (dm_aspect + 0.10))) 358 { 359 uint16 diff; 360 361 LOG(2,("CRTC2: (relative) widescreen panel: tuning horizontal scaling\n")); 362 363 /* X-scaling should be the same as Y-scaling */ 364 iscale_x = iscale_y; 365 /* enable testmode (b12) and program new X-scaling factor */ 366 DAC2W(FP_DEBUG1, (((iscale_x >> 1) & 0x00000fff) | (1 << 12))); 367 /* center/cut-off left and right side of screen */ 368 diff = ((si->ps.p2_timing.h_display - 369 (target.timing.h_display * ((1 << 12) / ((float)iscale_x)))) 370 / 2); 371 DAC2W(FP_HVALID_S, diff); 372 DAC2W(FP_HVALID_E, ((si->ps.p2_timing.h_display - diff) - 1)); 373 } 374 /* correct for portrait panels... */ 375 /* NOTE: 376 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */ 377 if ((iscale_y != (1 << 12)) && (si->ps.panel2_aspect < (dm_aspect - 0.10))) 378 { 379 LOG(2,("CRTC2: (relative) portrait panel: should tune vertical scaling\n")); 380 /* fixme: implement if this kind of portrait panels exist on nVidia... */ 381 } 382 } 383 384 /* do some logging.. */ 385 LOG(2,("CRTC2: FP_HVALID_S reg readback: $%08x\n", DAC2R(FP_HVALID_S))); 386 LOG(2,("CRTC2: FP_HVALID_E reg readback: $%08x\n", DAC2R(FP_HVALID_E))); 387 LOG(2,("CRTC2: FP_VVALID_S reg readback: $%08x\n", DAC2R(FP_VVALID_S))); 388 LOG(2,("CRTC2: FP_VVALID_E reg readback: $%08x\n", DAC2R(FP_VVALID_E))); 389 LOG(2,("CRTC2: FP_DEBUG0 reg readback: $%08x\n", DAC2R(FP_DEBUG0))); 390 LOG(2,("CRTC2: FP_DEBUG1 reg readback: $%08x\n", DAC2R(FP_DEBUG1))); 391 LOG(2,("CRTC2: FP_DEBUG2 reg readback: $%08x\n", DAC2R(FP_DEBUG2))); 392 LOG(2,("CRTC2: FP_DEBUG3 reg readback: $%08x\n", DAC2R(FP_DEBUG3))); 393 LOG(2,("CRTC2: FP_TG_CTRL reg readback: $%08x\n", DAC2R(FP_TG_CTRL))); 394 } 395 396 return B_OK; 397 } 398 399 status_t nv_crtc2_depth(int mode) 400 { 401 uint8 viddelay = 0; 402 uint32 genctrl = 0; 403 404 /* set VCLK scaling */ 405 switch(mode) 406 { 407 case BPP8: 408 viddelay = 0x01; 409 /* genctrl b4 & b5 reset: 'direct mode' */ 410 genctrl = 0x00101100; 411 break; 412 case BPP15: 413 viddelay = 0x02; 414 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 415 genctrl = 0x00100130; 416 break; 417 case BPP16: 418 viddelay = 0x02; 419 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 420 genctrl = 0x00101130; 421 break; 422 case BPP24: 423 viddelay = 0x03; 424 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 425 genctrl = 0x00100130; 426 break; 427 case BPP32: 428 viddelay = 0x03; 429 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 430 genctrl = 0x00101130; 431 break; 432 } 433 /* enable access to secondary head */ 434 set_crtc_owner(1); 435 436 CRTC2W(PIXEL, ((CRTC2R(PIXEL) & 0xfc) | viddelay)); 437 DAC2W(GENCTRL, genctrl); 438 439 return B_OK; 440 } 441 442 status_t nv_crtc2_dpms(bool display, bool h, bool v) 443 { 444 uint8 temp; 445 446 LOG(4,("CRTC2: setting DPMS: ")); 447 448 /* enable access to secondary head */ 449 set_crtc_owner(1); 450 451 /* start synchronous reset: required before turning screen off! */ 452 SEQW(RESET, 0x01); 453 454 /* turn screen off */ 455 temp = SEQR(CLKMODE); 456 if (display) 457 { 458 SEQW(CLKMODE, (temp & ~0x20)); 459 460 /* end synchronous reset if display should be enabled */ 461 SEQW(RESET, 0x03); 462 463 //'safe mode' test! feedback needed with this 'setting'! 464 if (0)//si->ps.tmds2_active) 465 { 466 /* powerup both LVDS (laptop panellink) and TMDS (DVI panellink) 467 * internal transmitters... */ 468 /* note: 469 * the powerbits in this register are hardwired to the DVI connectors, 470 * instead of to the DACs! (confirmed NV34) */ 471 //fixme... 472 DAC2W(FP_DEBUG0, (DAC2R(FP_DEBUG0) & 0xcfffffff)); 473 /* ... and powerup external TMDS transmitter if it exists */ 474 /* (confirmed OK on NV28 and NV34) */ 475 CRTC2W(0x59, (CRTC2R(0x59) | 0x01)); 476 } 477 478 LOG(4,("display on, ")); 479 } 480 else 481 { 482 SEQW(CLKMODE, (temp | 0x20)); 483 484 //'safe mode' test! feedback needed with this 'setting'! 485 if (0)//si->ps.tmds2_active) 486 { 487 /* powerdown both LVDS (laptop panellink) and TMDS (DVI panellink) 488 * internal transmitters... */ 489 /* note: 490 * the powerbits in this register are hardwired to the DVI connectors, 491 * instead of to the DACs! (confirmed NV34) */ 492 //fixme... 493 DAC2W(FP_DEBUG0, (DAC2R(FP_DEBUG0) | 0x30000000)); 494 /* ... and powerdown external TMDS transmitter if it exists */ 495 /* (confirmed OK on NV28 and NV34) */ 496 CRTC2W(0x59, (CRTC2R(0x59) & 0xfe)); 497 } 498 499 LOG(4,("display off, ")); 500 } 501 502 if (h) 503 { 504 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0x7f)); 505 LOG(4,("hsync enabled, ")); 506 } 507 else 508 { 509 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x80)); 510 LOG(4,("hsync disabled, ")); 511 } 512 if (v) 513 { 514 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xbf)); 515 LOG(4,("vsync enabled\n")); 516 } 517 else 518 { 519 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x40)); 520 LOG(4,("vsync disabled\n")); 521 } 522 523 return B_OK; 524 } 525 526 status_t nv_crtc2_dpms_fetch(bool *display, bool *h, bool *v) 527 { 528 /* enable access to secondary head */ 529 set_crtc_owner(1); 530 531 *display = !(SEQR(CLKMODE) & 0x20); 532 *h = !(CRTC2R(REPAINT1) & 0x80); 533 *v = !(CRTC2R(REPAINT1) & 0x40); 534 535 LOG(4,("CTRC2: fetched DPMS state:")); 536 if (display) LOG(4,("display on, ")); 537 else LOG(4,("display off, ")); 538 if (h) LOG(4,("hsync enabled, ")); 539 else LOG(4,("hsync disabled, ")); 540 if (v) LOG(4,("vsync enabled\n")); 541 else LOG(4,("vsync disabled\n")); 542 543 return B_OK; 544 } 545 546 status_t nv_crtc2_set_display_pitch() 547 { 548 uint32 offset; 549 550 LOG(4,("CRTC2: setting card pitch (offset between lines)\n")); 551 552 /* figure out offset value hardware needs */ 553 offset = si->fbc.bytes_per_row / 8; 554 555 LOG(2,("CRTC2: offset register set to: $%04x\n", offset)); 556 557 /* enable access to secondary head */ 558 set_crtc_owner(1); 559 560 /* program the card */ 561 CRTC2W(PITCHL, (offset & 0x00ff)); 562 CRTC2W(REPAINT0, ((CRTC2R(REPAINT0) & 0x1f) | ((offset & 0x0700) >> 3))); 563 564 return B_OK; 565 } 566 567 status_t nv_crtc2_set_display_start(uint32 startadd,uint8 bpp) 568 { 569 uint32 timeout = 0; 570 571 LOG(4,("CRTC2: setting card RAM to be displayed bpp %d\n", bpp)); 572 573 LOG(2,("CRTC2: startadd: $%08x\n", startadd)); 574 LOG(2,("CRTC2: frameRAM: $%08x\n", si->framebuffer)); 575 LOG(2,("CRTC2: framebuffer: $%08x\n", si->fbc.frame_buffer)); 576 577 /* we might have no retraces during setmode! */ 578 /* wait 25mS max. for retrace to occur (refresh > 40Hz) */ 579 while (((NV_REG32(NV32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) && 580 (timeout < (25000/10))) 581 { 582 /* don't snooze much longer or retrace might get missed! */ 583 snooze(10); 584 timeout++; 585 } 586 587 /* enable access to secondary head */ 588 set_crtc_owner(1); 589 590 /* upto 4Gb RAM adressing: must be used on NV10 and later! */ 591 /* NOTE: 592 * While this register also exists on pre-NV10 cards, it will 593 * wrap-around at 16Mb boundaries!! */ 594 595 /* 30bit adress in 32bit words */ 596 NV_REG32(NV32_NV10FB2STADD32) = (startadd & 0xfffffffc); 597 598 /* set byte adress: (b0 - 1) */ 599 ATB2W(HORPIXPAN, ((startadd & 0x00000003) << 1)); 600 601 return B_OK; 602 } 603 604 status_t nv_crtc2_cursor_init() 605 { 606 int i; 607 uint32 * fb; 608 /* cursor bitmap will be stored at the start of the framebuffer */ 609 const uint32 curadd = 0; 610 611 /* enable access to secondary head */ 612 set_crtc_owner(1); 613 614 /* set cursor bitmap adress ... */ 615 if (si->ps.laptop) 616 { 617 /* must be used this way on pre-NV10 and on all 'Go' cards! */ 618 619 /* cursorbitmap must start on 2Kbyte boundary: */ 620 /* set adress bit11-16, and set 'no doublescan' (registerbit 1 = 0) */ 621 CRTC2W(CURCTL0, ((curadd & 0x0001f800) >> 9)); 622 /* set adress bit17-23, and set graphics mode cursor(?) (registerbit 7 = 1) */ 623 CRTC2W(CURCTL1, (((curadd & 0x00fe0000) >> 17) | 0x80)); 624 /* set adress bit24-31 */ 625 CRTC2W(CURCTL2, ((curadd & 0xff000000) >> 24)); 626 } 627 else 628 { 629 /* upto 4Gb RAM adressing: 630 * can be used on NV10 and later (except for 'Go' cards)! */ 631 /* NOTE: 632 * This register does not exist on pre-NV10 and 'Go' cards. */ 633 634 /* cursorbitmap must still start on 2Kbyte boundary: */ 635 NV_REG32(NV32_NV10CUR2ADD32) = (curadd & 0xfffff800); 636 } 637 638 /* set cursor colour: not needed because of direct nature of cursor bitmap. */ 639 640 /*clear cursor*/ 641 fb = (uint32 *) si->framebuffer + curadd; 642 for (i=0;i<(2048/4);i++) 643 { 644 fb[i]=0; 645 } 646 647 /* select 32x32 pixel, 16bit color cursorbitmap, no doublescan */ 648 NV_REG32(NV32_2CURCONF) = 0x02000100; 649 650 /* activate hardware cursor */ 651 nv_crtc2_cursor_show(); 652 653 return B_OK; 654 } 655 656 status_t nv_crtc2_cursor_show() 657 { 658 LOG(4,("CRTC2: enabling cursor\n")); 659 660 /* enable access to secondary head */ 661 set_crtc_owner(1); 662 663 /* b0 = 1 enables cursor */ 664 CRTC2W(CURCTL0, (CRTC2R(CURCTL0) | 0x01)); 665 666 return B_OK; 667 } 668 669 status_t nv_crtc2_cursor_hide() 670 { 671 LOG(4,("CRTC2: disabling cursor\n")); 672 673 /* enable access to secondary head */ 674 set_crtc_owner(1); 675 676 /* b0 = 0 disables cursor */ 677 CRTC2W(CURCTL0, (CRTC2R(CURCTL0) & 0xfe)); 678 679 return B_OK; 680 } 681 682 /*set up cursor shape*/ 683 status_t nv_crtc2_cursor_define(uint8* andMask,uint8* xorMask) 684 { 685 int x, y; 686 uint8 b; 687 uint16 *cursor; 688 uint16 pixel; 689 690 /* get a pointer to the cursor */ 691 cursor = (uint16*) si->framebuffer; 692 693 /* draw the cursor */ 694 /* (Nvidia cards have a RGB15 direct color cursor bitmap, bit #16 is transparancy) */ 695 for (y = 0; y < 16; y++) 696 { 697 b = 0x80; 698 for (x = 0; x < 8; x++) 699 { 700 /* preset transparant */ 701 pixel = 0x0000; 702 /* set white if requested */ 703 if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; 704 /* set black if requested */ 705 if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; 706 /* set invert if requested */ 707 if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; 708 /* place the pixel in the bitmap */ 709 cursor[x + (y * 32)] = pixel; 710 b >>= 1; 711 } 712 xorMask++; 713 andMask++; 714 b = 0x80; 715 for (; x < 16; x++) 716 { 717 /* preset transparant */ 718 pixel = 0x0000; 719 /* set white if requested */ 720 if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; 721 /* set black if requested */ 722 if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; 723 /* set invert if requested */ 724 if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; 725 /* place the pixel in the bitmap */ 726 cursor[x + (y * 32)] = pixel; 727 b >>= 1; 728 } 729 xorMask++; 730 andMask++; 731 } 732 733 return B_OK; 734 } 735 736 /* position the cursor */ 737 status_t nv_crtc2_cursor_position(uint16 x, uint16 y) 738 { 739 uint16 yhigh; 740 741 /* make sure we are beyond the first line of the cursorbitmap being drawn during 742 * updating the position to prevent distortions: no double buffering feature */ 743 /* Note: 744 * we need to return as quick as possible or some apps will exhibit lagging.. */ 745 746 /* read the old cursor Y position */ 747 yhigh = ((DAC2R(CURPOS) & 0x0fff0000) >> 16); 748 /* make sure we will wait until we are below both the old and new Y position: 749 * visible cursorbitmap drawing needs to be done at least... */ 750 if (y > yhigh) yhigh = y; 751 752 if (yhigh < (si->dm.timing.v_display - 16)) 753 { 754 /* we have vertical lines below old and new cursorposition to spare. So we 755 * update the cursor postion 'mid-screen', but below that area. */ 756 while (((uint16)(NV_REG32(NV32_RASTER2) & 0x000007ff)) < (yhigh + 16)) 757 { 758 snooze(10); 759 } 760 } 761 else 762 { 763 /* no room to spare, just wait for retrace (is relatively slow) */ 764 while ((NV_REG32(NV32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) 765 { 766 /* don't snooze much longer or retrace might get missed! */ 767 snooze(10); 768 } 769 } 770 771 /* update cursorposition */ 772 DAC2W(CURPOS, ((x & 0x0fff) | ((y & 0x0fff) << 16))); 773 774 return B_OK; 775 } 776