1 /* second CTRC functionality for GeForce cards */ 2 /* Author: 3 Rudolf Cornelissen 11/2002-6/2004 4 */ 5 6 #define MODULE_BIT 0x00020000 7 8 #include "nv_std.h" 9 10 /*Adjust passed parameters to a valid mode line*/ 11 status_t nv_crtc2_validate_timing( 12 uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht, 13 uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt 14 ) 15 { 16 /* horizontal */ 17 /* make all parameters multiples of 8 */ 18 *hd_e &= 0xfff8; 19 *hs_s &= 0xfff8; 20 *hs_e &= 0xfff8; 21 *ht &= 0xfff8; 22 23 /* confine to required number of bits, taking logic into account */ 24 if (*hd_e > ((0x01ff - 2) << 3)) *hd_e = ((0x01ff - 2) << 3); 25 if (*hs_s > ((0x01ff - 1) << 3)) *hs_s = ((0x01ff - 1) << 3); 26 if (*hs_e > ( 0x01ff << 3)) *hs_e = ( 0x01ff << 3); 27 if (*ht > ((0x01ff + 5) << 3)) *ht = ((0x01ff + 5) << 3); 28 29 /* NOTE: keep horizontal timing at multiples of 8! */ 30 /* confine to a reasonable width */ 31 if (*hd_e < 640) *hd_e = 640; 32 if (*hd_e > 2048) *hd_e = 2048; 33 34 /* if hor. total does not leave room for a sensible sync pulse, increase it! */ 35 if (*ht < (*hd_e + 80)) *ht = (*hd_e + 80); 36 37 /* make sure sync pulse is not during display */ 38 if (*hs_e > (*ht - 8)) *hs_e = (*ht - 8); 39 if (*hs_s < (*hd_e + 8)) *hs_s = (*hd_e + 8); 40 41 /* correct sync pulse if it is too long: 42 * there are only 5 bits available to save this in the card registers! */ 43 if (*hs_e > (*hs_s + 0xf8)) *hs_e = (*hs_s + 0xf8); 44 45 /*vertical*/ 46 /* confine to required number of bits, taking logic into account */ 47 //fixme if needed: on GeForce cards there are 12 instead of 11 bits... 48 if (*vd_e > (0x7ff - 2)) *vd_e = (0x7ff - 2); 49 if (*vs_s > (0x7ff - 1)) *vs_s = (0x7ff - 1); 50 if (*vs_e > 0x7ff ) *vs_e = 0x7ff ; 51 if (*vt > (0x7ff + 2)) *vt = (0x7ff + 2); 52 53 /* confine to a reasonable height */ 54 if (*vd_e < 480) *vd_e = 480; 55 if (*vd_e > 1536) *vd_e = 1536; 56 57 /*if vertical total does not leave room for a sync pulse, increase it!*/ 58 if (*vt < (*vd_e + 3)) *vt = (*vd_e + 3); 59 60 /* make sure sync pulse is not during display */ 61 if (*vs_e > (*vt - 1)) *vs_e = (*vt - 1); 62 if (*vs_s < (*vd_e + 1)) *vs_s = (*vd_e + 1); 63 64 /* correct sync pulse if it is too long: 65 * there are only 4 bits available to save this in the card registers! */ 66 if (*vs_e > (*vs_s + 0x0f)) *vs_e = (*vs_s + 0x0f); 67 68 return B_OK; 69 } 70 71 /*set a mode line - inputs are in pixels*/ 72 status_t nv_crtc2_set_timing(display_mode target) 73 { 74 uint8 temp; 75 76 uint32 htotal; /*total horizontal total VCLKs*/ 77 uint32 hdisp_e; /*end of horizontal display (begins at 0)*/ 78 uint32 hsync_s; /*begin of horizontal sync pulse*/ 79 uint32 hsync_e; /*end of horizontal sync pulse*/ 80 uint32 hblnk_s; /*begin horizontal blanking*/ 81 uint32 hblnk_e; /*end horizontal blanking*/ 82 83 uint32 vtotal; /*total vertical total scanlines*/ 84 uint32 vdisp_e; /*end of vertical display*/ 85 uint32 vsync_s; /*begin of vertical sync pulse*/ 86 uint32 vsync_e; /*end of vertical sync pulse*/ 87 uint32 vblnk_s; /*begin vertical blanking*/ 88 uint32 vblnk_e; /*end vertical blanking*/ 89 90 uint32 linecomp; /*split screen and vdisp_e interrupt*/ 91 92 LOG(4,("CRTC2: setting timing\n")); 93 94 /* setup tuned internal modeline for flatpanel if connected and active */ 95 if (si->ps.tmds2_active) 96 { 97 LOG(2,("CRTC2: DFP active: tuning modeline\n")); 98 99 /* horizontal timing */ 100 //testing (640x480): total = 135% is too much, 120% to small... 101 //total = display + 160 equals panel modeline: but must be smaller...? 102 // target.timing.h_total = target.timing.h_display + 152;//160;//128 103 // target.timing.h_sync_start = target.timing.h_total - 136;//144;//112 104 // target.timing.h_sync_end = target.timing.h_total - 40;//48;//16 105 //adaptive to panel: fixme: test on 4:3 and 16:10 panels! 106 target.timing.h_sync_start = 107 ((uint16)((si->ps.p2_timing.h_sync_start / ((float)si->ps.p2_timing.h_display)) * 108 target.timing.h_display)) & 0xfff8; 109 110 target.timing.h_sync_end = 111 ((uint16)((si->ps.p2_timing.h_sync_end / ((float)si->ps.p2_timing.h_display)) * 112 target.timing.h_display)) & 0xfff8; 113 114 target.timing.h_total = 115 (((uint16)((si->ps.p2_timing.h_total / ((float)si->ps.p2_timing.h_display)) * 116 target.timing.h_display)) & 0xfff8) - 8; 117 118 /* apparantly NV11 timing is a bit more critical */ 119 if ((si->ps.card_type == NV11) && 120 (target.timing.h_display == si->ps.p2_timing.h_display)) 121 { 122 target.timing.h_total -= 32; 123 } 124 125 if (target.timing.h_sync_start == target.timing.h_display) 126 target.timing.h_sync_start += 8; 127 if (target.timing.h_sync_end == target.timing.h_total) 128 target.timing.h_sync_end -= 8; 129 130 /* vertical timing */ 131 // target.timing.v_total = target.timing.v_display + 6; 132 // target.timing.v_sync_start = target.timing.v_total - 3; 133 // target.timing.v_sync_end = target.timing.v_total - 2; 134 target.timing.v_sync_start = 135 ((uint16)((si->ps.p2_timing.v_sync_start / ((float)si->ps.p2_timing.v_display)) * 136 target.timing.v_display)); 137 138 target.timing.v_sync_end = 139 ((uint16)((si->ps.p2_timing.v_sync_end / ((float)si->ps.p2_timing.v_display)) * 140 target.timing.v_display)); 141 142 target.timing.v_total = 143 ((uint16)((si->ps.p2_timing.v_total / ((float)si->ps.p2_timing.v_display)) * 144 target.timing.v_display)) - 1; 145 146 if (target.timing.v_sync_start == target.timing.v_display) 147 target.timing.v_sync_start += 1; 148 if (target.timing.v_sync_end == target.timing.v_total) 149 target.timing.v_sync_end -= 1; 150 151 /* disable GPU scaling testmode so automatic scaling will be done */ 152 DAC2W(FP_DEBUG1, 0); 153 } 154 155 /* Modify parameters as required by standard VGA */ 156 htotal = ((target.timing.h_total >> 3) - 5); 157 hdisp_e = ((target.timing.h_display >> 3) - 1); 158 hblnk_s = hdisp_e; 159 hblnk_e = (htotal + 4);//0; 160 hsync_s = (target.timing.h_sync_start >> 3); 161 hsync_e = (target.timing.h_sync_end >> 3); 162 163 vtotal = target.timing.v_total - 2; 164 vdisp_e = target.timing.v_display - 1; 165 vblnk_s = vdisp_e; 166 vblnk_e = (vtotal + 1); 167 vsync_s = target.timing.v_sync_start;//-1; 168 vsync_e = target.timing.v_sync_end;//-1; 169 170 /* prevent memory adress counter from being reset (linecomp may not occur) */ 171 linecomp = target.timing.v_display; 172 173 /* enable access to secondary head */ 174 set_crtc_owner(1); 175 176 /* Note for laptop and DVI flatpanels: 177 * CRTC timing has a seperate set of registers from flatpanel timing. 178 * The flatpanel timing registers have scaling registers that are used to match 179 * these two modelines. */ 180 { 181 LOG(4,("CRTC2: Setting full timing...\n")); 182 183 /* log the mode that will be set */ 184 LOG(2,("CRTC2:\n\tHTOT:%x\n\tHDISPEND:%x\n\tHBLNKS:%x\n\tHBLNKE:%x\n\tHSYNCS:%x\n\tHSYNCE:%x\n\t",htotal,hdisp_e,hblnk_s,hblnk_e,hsync_s,hsync_e)); 185 LOG(2,("VTOT:%x\n\tVDISPEND:%x\n\tVBLNKS:%x\n\tVBLNKE:%x\n\tVSYNCS:%x\n\tVSYNCE:%x\n",vtotal,vdisp_e,vblnk_s,vblnk_e,vsync_s,vsync_e)); 186 187 /* actually program the card! */ 188 /* unlock CRTC registers at index 0-7 */ 189 CRTC2W(VSYNCE, (CRTC2R(VSYNCE) & 0x7f)); 190 /* horizontal standard VGA regs */ 191 CRTC2W(HTOTAL, (htotal & 0xff)); 192 CRTC2W(HDISPE, (hdisp_e & 0xff)); 193 CRTC2W(HBLANKS, (hblnk_s & 0xff)); 194 /* also unlock vertical retrace registers in advance */ 195 CRTC2W(HBLANKE, ((hblnk_e & 0x1f) | 0x80)); 196 CRTC2W(HSYNCS, (hsync_s & 0xff)); 197 CRTC2W(HSYNCE, ((hsync_e & 0x1f) | ((hblnk_e & 0x20) << 2))); 198 199 /* vertical standard VGA regs */ 200 CRTC2W(VTOTAL, (vtotal & 0xff)); 201 CRTC2W(OVERFLOW, 202 ( 203 ((vtotal & 0x100) >> (8 - 0)) | ((vtotal & 0x200) >> (9 - 5)) | 204 ((vdisp_e & 0x100) >> (8 - 1)) | ((vdisp_e & 0x200) >> (9 - 6)) | 205 ((vsync_s & 0x100) >> (8 - 2)) | ((vsync_s & 0x200) >> (9 - 7)) | 206 ((vblnk_s & 0x100) >> (8 - 3)) | ((linecomp & 0x100) >> (8 - 4)) 207 )); 208 CRTC2W(PRROWSCN, 0x00); /* not used */ 209 CRTC2W(MAXSCLIN, (((vblnk_s & 0x200) >> (9 - 5)) | ((linecomp & 0x200) >> (9 - 6)))); 210 CRTC2W(VSYNCS, (vsync_s & 0xff)); 211 CRTC2W(VSYNCE, ((CRTC2R(VSYNCE) & 0xf0) | (vsync_e & 0x0f))); 212 CRTC2W(VDISPE, (vdisp_e & 0xff)); 213 CRTC2W(VBLANKS, (vblnk_s & 0xff)); 214 CRTC2W(VBLANKE, (vblnk_e & 0xff)); 215 CRTC2W(LINECOMP, (linecomp & 0xff)); 216 217 /* horizontal extended regs */ 218 //fixme: we reset bit4. is this correct?? 219 CRTC2W(HEB, (CRTC2R(HEB) & 0xe0) | 220 ( 221 ((htotal & 0x100) >> (8 - 0)) | 222 ((hdisp_e & 0x100) >> (8 - 1)) | 223 ((hblnk_s & 0x100) >> (8 - 2)) | 224 ((hsync_s & 0x100) >> (8 - 3)) 225 )); 226 227 /* (mostly) vertical extended regs */ 228 CRTC2W(LSR, 229 ( 230 ((vtotal & 0x400) >> (10 - 0)) | 231 ((vdisp_e & 0x400) >> (10 - 1)) | 232 ((vsync_s & 0x400) >> (10 - 2)) | 233 ((vblnk_s & 0x400) >> (10 - 3)) | 234 ((hblnk_e & 0x040) >> (6 - 4)) 235 //fixme: we still miss one linecomp bit!?! is this it?? 236 //| ((linecomp & 0x400) >> 3) 237 )); 238 239 /* more vertical extended regs */ 240 CRTC2W(EXTRA, 241 ( 242 ((vtotal & 0x800) >> (11 - 0)) | 243 ((vdisp_e & 0x800) >> (11 - 2)) | 244 ((vsync_s & 0x800) >> (11 - 4)) | 245 ((vblnk_s & 0x800) >> (11 - 6)) 246 //fixme: do we miss another linecomp bit!?! 247 )); 248 249 /* setup 'large screen' mode */ 250 if (target.timing.h_display >= 1280) 251 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xfb)); 252 else 253 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x04)); 254 255 /* setup HSYNC & VSYNC polarity */ 256 LOG(2,("CRTC2: sync polarity: ")); 257 temp = NV_REG8(NV8_MISCR); 258 if (target.timing.flags & B_POSITIVE_HSYNC) 259 { 260 LOG(2,("H:pos ")); 261 temp &= ~0x40; 262 } 263 else 264 { 265 LOG(2,("H:neg ")); 266 temp |= 0x40; 267 } 268 if (target.timing.flags & B_POSITIVE_VSYNC) 269 { 270 LOG(2,("V:pos ")); 271 temp &= ~0x80; 272 } 273 else 274 { 275 LOG(2,("V:neg ")); 276 temp |= 0x80; 277 } 278 NV_REG8(NV8_MISCW) = temp; 279 280 LOG(2,(", MISC reg readback: $%02x\n", NV_REG8(NV8_MISCR))); 281 } 282 283 /* always disable interlaced operation */ 284 /* (interlace is supported on upto and including NV10, NV15, and NV30 and up) */ 285 CRTC2W(INTERLACE, 0xff); 286 287 /* disable CRTC slaved mode unless a panel is in use */ 288 // fixme: this kills TVout when it was in use... 289 if (!si->ps.tmds2_active) CRTC2W(PIXEL, (CRTC2R(PIXEL) & 0x7f)); 290 291 /* setup flatpanel if connected and active */ 292 if (si->ps.tmds2_active) 293 { 294 uint32 iscale_x, iscale_y; 295 296 /* calculate inverse scaling factors used by hardware in 20.12 format */ 297 iscale_x = (((1 << 12) * target.timing.h_display) / si->ps.p2_timing.h_display); 298 iscale_y = (((1 << 12) * target.timing.v_display) / si->ps.p2_timing.v_display); 299 300 /* unblock flatpanel timing programming (or something like that..) */ 301 CRTC2W(FP_HTIMING, 0); 302 CRTC2W(FP_VTIMING, 0); 303 LOG(2,("CRTC2: FP_HTIMING reg readback: $%02x\n", CRTC2R(FP_HTIMING))); 304 LOG(2,("CRTC2: FP_VTIMING reg readback: $%02x\n", CRTC2R(FP_VTIMING))); 305 306 /* enable full width visibility on flatpanel */ 307 DAC2W(FP_HVALID_S, 0); 308 DAC2W(FP_HVALID_E, (si->ps.p2_timing.h_display - 1)); 309 /* enable full height visibility on flatpanel */ 310 DAC2W(FP_VVALID_S, 0); 311 DAC2W(FP_VVALID_E, (si->ps.p2_timing.v_display - 1)); 312 313 /* nVidia cards support upscaling except on ??? */ 314 /* NV11 cards can upscale after all! */ 315 if (0)//si->ps.card_type == NV11) 316 { 317 /* disable last fetched line limiting */ 318 DAC2W(FP_DEBUG2, 0x00000000); 319 /* inform panel to scale if needed */ 320 if ((iscale_x != (1 << 12)) || (iscale_y != (1 << 12))) 321 { 322 LOG(2,("CRTC2: DFP needs to do scaling\n")); 323 DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) | 0x00000100)); 324 } 325 else 326 { 327 LOG(2,("CRTC2: no scaling for DFP needed\n")); 328 DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) & 0xfffffeff)); 329 } 330 } 331 else 332 { 333 float dm_aspect; 334 335 LOG(2,("CRTC2: GPU scales for DFP if needed\n")); 336 337 /* calculate display mode aspect */ 338 dm_aspect = (target.timing.h_display / ((float)target.timing.v_display)); 339 340 /* limit last fetched line if vertical scaling is done */ 341 if (iscale_y != (1 << 12)) 342 DAC2W(FP_DEBUG2, ((1 << 28) | ((target.timing.v_display - 1) << 16))); 343 else 344 DAC2W(FP_DEBUG2, 0x00000000); 345 346 /* inform panel not to scale */ 347 DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) & 0xfffffeff)); 348 349 /* GPU scaling is automatically setup by hardware, so only modify this 350 * scalingfactor for non 4:3 (1.33) aspect panels; 351 * let's consider 1280x1024 1:33 aspect (it's 1.25 aspect actually!) */ 352 353 /* correct for widescreen panels relative to mode... 354 * (so if panel is more widescreen than mode being set) */ 355 /* BTW: known widescreen panels: 356 * 1280 x 800 (1.60), 357 * 1440 x 900 (1.60), 358 * 1680 x 1050 (1.60), 359 * 1920 x 1200 (1.60). */ 360 /* known 4:3 aspect non-standard resolution panels: 361 * 1400 x 1050 (1.33). */ 362 /* NOTE: 363 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */ 364 if ((iscale_x != (1 << 12)) && (si->ps.panel2_aspect > (dm_aspect + 0.10))) 365 { 366 uint16 diff; 367 368 LOG(2,("CRTC2: (relative) widescreen panel: tuning horizontal scaling\n")); 369 370 /* X-scaling should be the same as Y-scaling */ 371 iscale_x = iscale_y; 372 /* enable testmode (b12) and program new X-scaling factor */ 373 DAC2W(FP_DEBUG1, (((iscale_x >> 1) & 0x00000fff) | (1 << 12))); 374 /* center/cut-off left and right side of screen */ 375 diff = ((si->ps.p2_timing.h_display - 376 (target.timing.h_display * ((1 << 12) / ((float)iscale_x)))) 377 / 2); 378 DAC2W(FP_HVALID_S, diff); 379 DAC2W(FP_HVALID_E, ((si->ps.p2_timing.h_display - diff) - 1)); 380 } 381 /* correct for portrait panels... */ 382 /* NOTE: 383 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */ 384 if ((iscale_y != (1 << 12)) && (si->ps.panel2_aspect < (dm_aspect - 0.10))) 385 { 386 LOG(2,("CRTC2: (relative) portrait panel: should tune vertical scaling\n")); 387 /* fixme: implement if this kind of portrait panels exist on nVidia... */ 388 } 389 } 390 391 /* do some logging.. */ 392 LOG(2,("CRTC2: FP_HVALID_S reg readback: $%08x\n", DAC2R(FP_HVALID_S))); 393 LOG(2,("CRTC2: FP_HVALID_E reg readback: $%08x\n", DAC2R(FP_HVALID_E))); 394 LOG(2,("CRTC2: FP_VVALID_S reg readback: $%08x\n", DAC2R(FP_VVALID_S))); 395 LOG(2,("CRTC2: FP_VVALID_E reg readback: $%08x\n", DAC2R(FP_VVALID_E))); 396 LOG(2,("CRTC2: FP_DEBUG0 reg readback: $%08x\n", DAC2R(FP_DEBUG0))); 397 LOG(2,("CRTC2: FP_DEBUG1 reg readback: $%08x\n", DAC2R(FP_DEBUG1))); 398 LOG(2,("CRTC2: FP_DEBUG2 reg readback: $%08x\n", DAC2R(FP_DEBUG2))); 399 LOG(2,("CRTC2: FP_DEBUG3 reg readback: $%08x\n", DAC2R(FP_DEBUG3))); 400 LOG(2,("CRTC2: FP_TG_CTRL reg readback: $%08x\n", DAC2R(FP_TG_CTRL))); 401 } 402 403 return B_OK; 404 } 405 406 status_t nv_crtc2_depth(int mode) 407 { 408 uint8 viddelay = 0; 409 uint32 genctrl = 0; 410 411 /* set VCLK scaling */ 412 switch(mode) 413 { 414 case BPP8: 415 viddelay = 0x01; 416 /* genctrl b4 & b5 reset: 'direct mode' */ 417 genctrl = 0x00101100; 418 break; 419 case BPP15: 420 viddelay = 0x02; 421 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 422 genctrl = 0x00100130; 423 break; 424 case BPP16: 425 viddelay = 0x02; 426 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 427 genctrl = 0x00101130; 428 break; 429 case BPP24: 430 viddelay = 0x03; 431 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 432 genctrl = 0x00100130; 433 break; 434 case BPP32: 435 viddelay = 0x03; 436 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 437 genctrl = 0x00101130; 438 break; 439 } 440 /* enable access to secondary head */ 441 set_crtc_owner(1); 442 443 CRTC2W(PIXEL, ((CRTC2R(PIXEL) & 0xfc) | viddelay)); 444 DAC2W(GENCTRL, genctrl); 445 446 return B_OK; 447 } 448 449 status_t nv_crtc2_dpms(bool display, bool h, bool v) 450 { 451 uint8 temp; 452 453 LOG(4,("CRTC2: setting DPMS: ")); 454 455 /* enable access to secondary head */ 456 set_crtc_owner(1); 457 458 /* start synchronous reset: required before turning screen off! */ 459 SEQW(RESET, 0x01); 460 461 /* turn screen off */ 462 temp = SEQR(CLKMODE); 463 if (display) 464 { 465 SEQW(CLKMODE, (temp & ~0x20)); 466 467 /* end synchronous reset if display should be enabled */ 468 SEQW(RESET, 0x03); 469 470 //'safe mode' test! feedback needed with this 'setting'! 471 if (0)//si->ps.tmds2_active) 472 { 473 /* powerup both LVDS (laptop panellink) and TMDS (DVI panellink) 474 * internal transmitters... */ 475 /* note: 476 * the powerbits in this register are hardwired to the DVI connectors, 477 * instead of to the DACs! (confirmed NV34) */ 478 //fixme... 479 DAC2W(FP_DEBUG0, (DAC2R(FP_DEBUG0) & 0xcfffffff)); 480 /* ... and powerup external TMDS transmitter if it exists */ 481 /* (confirmed OK on NV28 and NV34) */ 482 CRTC2W(0x59, (CRTC2R(0x59) | 0x01)); 483 } 484 485 LOG(4,("display on, ")); 486 } 487 else 488 { 489 SEQW(CLKMODE, (temp | 0x20)); 490 491 //'safe mode' test! feedback needed with this 'setting'! 492 if (0)//si->ps.tmds2_active) 493 { 494 /* powerdown both LVDS (laptop panellink) and TMDS (DVI panellink) 495 * internal transmitters... */ 496 /* note: 497 * the powerbits in this register are hardwired to the DVI connectors, 498 * instead of to the DACs! (confirmed NV34) */ 499 //fixme... 500 DAC2W(FP_DEBUG0, (DAC2R(FP_DEBUG0) | 0x30000000)); 501 /* ... and powerdown external TMDS transmitter if it exists */ 502 /* (confirmed OK on NV28 and NV34) */ 503 CRTC2W(0x59, (CRTC2R(0x59) & 0xfe)); 504 } 505 506 LOG(4,("display off, ")); 507 } 508 509 if (h) 510 { 511 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0x7f)); 512 LOG(4,("hsync enabled, ")); 513 } 514 else 515 { 516 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x80)); 517 LOG(4,("hsync disabled, ")); 518 } 519 if (v) 520 { 521 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xbf)); 522 LOG(4,("vsync enabled\n")); 523 } 524 else 525 { 526 CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x40)); 527 LOG(4,("vsync disabled\n")); 528 } 529 530 return B_OK; 531 } 532 533 status_t nv_crtc2_dpms_fetch(bool *display, bool *h, bool *v) 534 { 535 /* enable access to secondary head */ 536 set_crtc_owner(1); 537 538 *display = !(SEQR(CLKMODE) & 0x20); 539 *h = !(CRTC2R(REPAINT1) & 0x80); 540 *v = !(CRTC2R(REPAINT1) & 0x40); 541 542 LOG(4,("CTRC2: fetched DPMS state: ")); 543 if (*display) LOG(4,("display on, ")); 544 else LOG(4,("display off, ")); 545 if (*h) LOG(4,("hsync enabled, ")); 546 else LOG(4,("hsync disabled, ")); 547 if (*v) LOG(4,("vsync enabled\n")); 548 else LOG(4,("vsync disabled\n")); 549 550 return B_OK; 551 } 552 553 status_t nv_crtc2_set_display_pitch() 554 { 555 uint32 offset; 556 557 LOG(4,("CRTC2: setting card pitch (offset between lines)\n")); 558 559 /* figure out offset value hardware needs */ 560 offset = si->fbc.bytes_per_row / 8; 561 562 LOG(2,("CRTC2: offset register set to: $%04x\n", offset)); 563 564 /* enable access to secondary head */ 565 set_crtc_owner(1); 566 567 /* program the card */ 568 CRTC2W(PITCHL, (offset & 0x00ff)); 569 CRTC2W(REPAINT0, ((CRTC2R(REPAINT0) & 0x1f) | ((offset & 0x0700) >> 3))); 570 571 return B_OK; 572 } 573 574 status_t nv_crtc2_set_display_start(uint32 startadd,uint8 bpp) 575 { 576 uint32 timeout = 0; 577 578 LOG(4,("CRTC2: setting card RAM to be displayed bpp %d\n", bpp)); 579 580 LOG(2,("CRTC2: startadd: $%08x\n", startadd)); 581 LOG(2,("CRTC2: frameRAM: $%08x\n", si->framebuffer)); 582 LOG(2,("CRTC2: framebuffer: $%08x\n", si->fbc.frame_buffer)); 583 584 /* we might have no retraces during setmode! */ 585 /* wait 25mS max. for retrace to occur (refresh > 40Hz) */ 586 while (((NV_REG32(NV32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) && 587 (timeout < (25000/10))) 588 { 589 /* don't snooze much longer or retrace might get missed! */ 590 snooze(10); 591 timeout++; 592 } 593 594 /* enable access to secondary head */ 595 set_crtc_owner(1); 596 597 /* upto 4Gb RAM adressing: must be used on NV10 and later! */ 598 /* NOTE: 599 * While this register also exists on pre-NV10 cards, it will 600 * wrap-around at 16Mb boundaries!! */ 601 602 /* 30bit adress in 32bit words */ 603 NV_REG32(NV32_NV10FB2STADD32) = (startadd & 0xfffffffc); 604 605 /* set byte adress: (b0 - 1) */ 606 ATB2W(HORPIXPAN, ((startadd & 0x00000003) << 1)); 607 608 return B_OK; 609 } 610 611 status_t nv_crtc2_cursor_init() 612 { 613 int i; 614 uint32 * fb; 615 /* cursor bitmap will be stored at the start of the framebuffer */ 616 const uint32 curadd = 0; 617 618 /* enable access to secondary head */ 619 set_crtc_owner(1); 620 621 /* set cursor bitmap adress ... */ 622 if (si->ps.laptop) 623 { 624 /* must be used this way on pre-NV10 and on all 'Go' cards! */ 625 626 /* cursorbitmap must start on 2Kbyte boundary: */ 627 /* set adress bit11-16, and set 'no doublescan' (registerbit 1 = 0) */ 628 CRTC2W(CURCTL0, ((curadd & 0x0001f800) >> 9)); 629 /* set adress bit17-23, and set graphics mode cursor(?) (registerbit 7 = 1) */ 630 CRTC2W(CURCTL1, (((curadd & 0x00fe0000) >> 17) | 0x80)); 631 /* set adress bit24-31 */ 632 CRTC2W(CURCTL2, ((curadd & 0xff000000) >> 24)); 633 } 634 else 635 { 636 /* upto 4Gb RAM adressing: 637 * can be used on NV10 and later (except for 'Go' cards)! */ 638 /* NOTE: 639 * This register does not exist on pre-NV10 and 'Go' cards. */ 640 641 /* cursorbitmap must still start on 2Kbyte boundary: */ 642 NV_REG32(NV32_NV10CUR2ADD32) = (curadd & 0xfffff800); 643 } 644 645 /* set cursor colour: not needed because of direct nature of cursor bitmap. */ 646 647 /*clear cursor*/ 648 fb = (uint32 *) si->framebuffer + curadd; 649 for (i=0;i<(2048/4);i++) 650 { 651 fb[i]=0; 652 } 653 654 /* select 32x32 pixel, 16bit color cursorbitmap, no doublescan */ 655 NV_REG32(NV32_2CURCONF) = 0x02000100; 656 657 /* activate hardware cursor */ 658 nv_crtc2_cursor_show(); 659 660 return B_OK; 661 } 662 663 status_t nv_crtc2_cursor_show() 664 { 665 LOG(4,("CRTC2: enabling cursor\n")); 666 667 /* enable access to secondary head */ 668 set_crtc_owner(1); 669 670 /* b0 = 1 enables cursor */ 671 CRTC2W(CURCTL0, (CRTC2R(CURCTL0) | 0x01)); 672 673 return B_OK; 674 } 675 676 status_t nv_crtc2_cursor_hide() 677 { 678 LOG(4,("CRTC2: disabling cursor\n")); 679 680 /* enable access to secondary head */ 681 set_crtc_owner(1); 682 683 /* b0 = 0 disables cursor */ 684 CRTC2W(CURCTL0, (CRTC2R(CURCTL0) & 0xfe)); 685 686 return B_OK; 687 } 688 689 /*set up cursor shape*/ 690 status_t nv_crtc2_cursor_define(uint8* andMask,uint8* xorMask) 691 { 692 int x, y; 693 uint8 b; 694 uint16 *cursor; 695 uint16 pixel; 696 697 /* get a pointer to the cursor */ 698 cursor = (uint16*) si->framebuffer; 699 700 /* draw the cursor */ 701 /* (Nvidia cards have a RGB15 direct color cursor bitmap, bit #16 is transparancy) */ 702 for (y = 0; y < 16; y++) 703 { 704 b = 0x80; 705 for (x = 0; x < 8; x++) 706 { 707 /* preset transparant */ 708 pixel = 0x0000; 709 /* set white if requested */ 710 if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; 711 /* set black if requested */ 712 if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; 713 /* set invert if requested */ 714 if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; 715 /* place the pixel in the bitmap */ 716 cursor[x + (y * 32)] = pixel; 717 b >>= 1; 718 } 719 xorMask++; 720 andMask++; 721 b = 0x80; 722 for (; x < 16; x++) 723 { 724 /* preset transparant */ 725 pixel = 0x0000; 726 /* set white if requested */ 727 if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; 728 /* set black if requested */ 729 if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; 730 /* set invert if requested */ 731 if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; 732 /* place the pixel in the bitmap */ 733 cursor[x + (y * 32)] = pixel; 734 b >>= 1; 735 } 736 xorMask++; 737 andMask++; 738 } 739 740 return B_OK; 741 } 742 743 /* position the cursor */ 744 status_t nv_crtc2_cursor_position(uint16 x, uint16 y) 745 { 746 uint16 yhigh; 747 748 /* make sure we are beyond the first line of the cursorbitmap being drawn during 749 * updating the position to prevent distortions: no double buffering feature */ 750 /* Note: 751 * we need to return as quick as possible or some apps will exhibit lagging.. */ 752 753 /* read the old cursor Y position */ 754 yhigh = ((DAC2R(CURPOS) & 0x0fff0000) >> 16); 755 /* make sure we will wait until we are below both the old and new Y position: 756 * visible cursorbitmap drawing needs to be done at least... */ 757 if (y > yhigh) yhigh = y; 758 759 if (yhigh < (si->dm.timing.v_display - 16)) 760 { 761 /* we have vertical lines below old and new cursorposition to spare. So we 762 * update the cursor postion 'mid-screen', but below that area. */ 763 while (((uint16)(NV_REG32(NV32_RASTER2) & 0x000007ff)) < (yhigh + 16)) 764 { 765 snooze(10); 766 } 767 } 768 else 769 { 770 /* no room to spare, just wait for retrace (is relatively slow) */ 771 while ((NV_REG32(NV32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) 772 { 773 /* don't snooze much longer or retrace might get missed! */ 774 snooze(10); 775 } 776 } 777 778 /* update cursorposition */ 779 DAC2W(CURPOS, ((x & 0x0fff) | ((y & 0x0fff) << 16))); 780 781 return B_OK; 782 } 783