1 /* CTRC functionality */ 2 /* Author: 3 Rudolf Cornelissen 11/2002-11/2005 4 */ 5 6 #define MODULE_BIT 0x00040000 7 8 #include "nv_std.h" 9 10 /* doing general fail-safe default setup here */ 11 //fixme: this is a _very_ basic setup, and it's preliminary... 12 status_t nv_crtc_update_fifo() 13 { 14 uint8 bytes_per_pixel = 1; 15 uint32 drain; 16 17 /* we are only using this on >>coldstarted<< cards which really need this */ 18 //fixme: re-enable or remove after general user confirmation of behaviour... 19 if (/*(si->settings.usebios) ||*/ (si->ps.card_type != NV05M64)) return B_OK; 20 21 /* enable access to primary head */ 22 set_crtc_owner(0); 23 24 /* set CRTC FIFO low watermark according to memory drain */ 25 switch(si->dm.space) 26 { 27 case B_CMAP8: 28 bytes_per_pixel = 1; 29 break; 30 case B_RGB15_LITTLE: 31 case B_RGB16_LITTLE: 32 bytes_per_pixel = 2; 33 break; 34 case B_RGB24_LITTLE: 35 bytes_per_pixel = 3; 36 break; 37 case B_RGB32_LITTLE: 38 bytes_per_pixel = 4; 39 break; 40 } 41 /* fixme: 42 * - I should probably include the refreshrate as well; 43 * - and the memory clocking speed, core clocking speed, RAM buswidth.. */ 44 drain = si->dm.timing.h_display * si->dm.timing.v_display * bytes_per_pixel; 45 46 /* Doesn't work for other than 32bit space (yet?) */ 47 if (si->dm.space != B_RGB32_LITTLE) 48 { 49 /* BIOS defaults */ 50 CRTCW(FIFO, 0x03); 51 CRTCW(FIFO_LWM, 0x20); 52 LOG(4,("CRTC: FIFO low-watermark set to $20, burst size 256 (BIOS defaults)\n")); 53 return B_OK; 54 } 55 56 if (drain > (((uint32)1280) * 1024 * 4)) 57 { 58 /* set CRTC FIFO burst size for 'smaller' bursts */ 59 CRTCW(FIFO, 0x01); 60 /* Instruct CRTC to fetch new data 'earlier' */ 61 CRTCW(FIFO_LWM, 0x40); 62 LOG(4,("CRTC: FIFO low-watermark set to $40, burst size 64\n")); 63 } 64 else 65 { 66 if (drain > (((uint32)1024) * 768 * 4)) 67 { 68 /* BIOS default */ 69 CRTCW(FIFO, 0x02); 70 /* Instruct CRTC to fetch new data 'earlier' */ 71 CRTCW(FIFO_LWM, 0x40); 72 LOG(4,("CRTC: FIFO low-watermark set to $40, burst size 128\n")); 73 } 74 else 75 { 76 /* BIOS defaults */ 77 CRTCW(FIFO, 0x03); 78 CRTCW(FIFO_LWM, 0x20); 79 LOG(4,("CRTC: FIFO low-watermark set to $20, burst size 256 (BIOS defaults)\n")); 80 } 81 } 82 83 return B_OK; 84 } 85 86 /* Adjust passed parameters to a valid mode line */ 87 status_t nv_crtc_validate_timing( 88 uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht, 89 uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt 90 ) 91 { 92 /* horizontal */ 93 /* make all parameters multiples of 8 */ 94 *hd_e &= 0xfff8; 95 *hs_s &= 0xfff8; 96 *hs_e &= 0xfff8; 97 *ht &= 0xfff8; 98 99 /* confine to required number of bits, taking logic into account */ 100 if (*hd_e > ((0x01ff - 2) << 3)) *hd_e = ((0x01ff - 2) << 3); 101 if (*hs_s > ((0x01ff - 1) << 3)) *hs_s = ((0x01ff - 1) << 3); 102 if (*hs_e > ( 0x01ff << 3)) *hs_e = ( 0x01ff << 3); 103 if (*ht > ((0x01ff + 5) << 3)) *ht = ((0x01ff + 5) << 3); 104 105 /* NOTE: keep horizontal timing at multiples of 8! */ 106 /* confine to a reasonable width */ 107 if (*hd_e < 640) *hd_e = 640; 108 if (si->ps.card_type > NV04) 109 { 110 if (*hd_e > 2048) *hd_e = 2048; 111 } 112 else 113 { 114 if (*hd_e > 1920) *hd_e = 1920; 115 } 116 117 /* if hor. total does not leave room for a sensible sync pulse, increase it! */ 118 if (*ht < (*hd_e + 80)) *ht = (*hd_e + 80); 119 120 /* if hor. total does not adhere to max. blanking pulse width, decrease it! */ 121 if (*ht > (*hd_e + 0x3f8)) *ht = (*hd_e + 0x3f8); 122 123 /* make sure sync pulse is not during display */ 124 if (*hs_e > (*ht - 8)) *hs_e = (*ht - 8); 125 if (*hs_s < (*hd_e + 8)) *hs_s = (*hd_e + 8); 126 127 /* correct sync pulse if it is too long: 128 * there are only 5 bits available to save this in the card registers! */ 129 if (*hs_e > (*hs_s + 0xf8)) *hs_e = (*hs_s + 0xf8); 130 131 /*vertical*/ 132 /* confine to required number of bits, taking logic into account */ 133 //fixme if needed: on GeForce cards there are 12 instead of 11 bits... 134 if (*vd_e > (0x7ff - 2)) *vd_e = (0x7ff - 2); 135 if (*vs_s > (0x7ff - 1)) *vs_s = (0x7ff - 1); 136 if (*vs_e > 0x7ff ) *vs_e = 0x7ff ; 137 if (*vt > (0x7ff + 2)) *vt = (0x7ff + 2); 138 139 /* confine to a reasonable height */ 140 if (*vd_e < 480) *vd_e = 480; 141 if (si->ps.card_type > NV04) 142 { 143 if (*vd_e > 1536) *vd_e = 1536; 144 } 145 else 146 { 147 if (*vd_e > 1440) *vd_e = 1440; 148 } 149 150 /*if vertical total does not leave room for a sync pulse, increase it!*/ 151 if (*vt < (*vd_e + 3)) *vt = (*vd_e + 3); 152 153 /* if vert. total does not adhere to max. blanking pulse width, decrease it! */ 154 if (*vt > (*vd_e + 0xff)) *vt = (*vd_e + 0xff); 155 156 /* make sure sync pulse is not during display */ 157 if (*vs_e > (*vt - 1)) *vs_e = (*vt - 1); 158 if (*vs_s < (*vd_e + 1)) *vs_s = (*vd_e + 1); 159 160 /* correct sync pulse if it is too long: 161 * there are only 4 bits available to save this in the card registers! */ 162 if (*vs_e > (*vs_s + 0x0f)) *vs_e = (*vs_s + 0x0f); 163 164 return B_OK; 165 } 166 167 /*set a mode line - inputs are in pixels*/ 168 status_t nv_crtc_set_timing(display_mode target) 169 { 170 uint8 temp; 171 172 uint32 htotal; /*total horizontal total VCLKs*/ 173 uint32 hdisp_e; /*end of horizontal display (begins at 0)*/ 174 uint32 hsync_s; /*begin of horizontal sync pulse*/ 175 uint32 hsync_e; /*end of horizontal sync pulse*/ 176 uint32 hblnk_s; /*begin horizontal blanking*/ 177 uint32 hblnk_e; /*end horizontal blanking*/ 178 179 uint32 vtotal; /*total vertical total scanlines*/ 180 uint32 vdisp_e; /*end of vertical display*/ 181 uint32 vsync_s; /*begin of vertical sync pulse*/ 182 uint32 vsync_e; /*end of vertical sync pulse*/ 183 uint32 vblnk_s; /*begin vertical blanking*/ 184 uint32 vblnk_e; /*end vertical blanking*/ 185 186 uint32 linecomp; /*split screen and vdisp_e interrupt*/ 187 188 LOG(4,("CRTC: setting timing\n")); 189 190 /* setup tuned internal modeline for flatpanel if connected and active */ 191 /* notes: 192 * - the CRTC modeline must end earlier than the panel modeline to keep correct 193 * sync going; 194 * - if the CRTC modeline ends too soon, pixelnoise will occur in 8 (or so) pixel 195 * wide horizontal stripes. This can be observed earliest on fullscreen overlay, 196 * and if it gets worse, also normal desktop output will suffer. The stripes 197 * are mainly visible at the left of the screen, over the entire screen height. */ 198 if (si->ps.tmds1_active) 199 { 200 LOG(2,("CRTC: DFP active: tuning modeline\n")); 201 202 /* horizontal timing */ 203 target.timing.h_sync_start = 204 ((uint16)((si->ps.p1_timing.h_sync_start / ((float)si->ps.p1_timing.h_display)) * 205 target.timing.h_display)) & 0xfff8; 206 207 target.timing.h_sync_end = 208 ((uint16)((si->ps.p1_timing.h_sync_end / ((float)si->ps.p1_timing.h_display)) * 209 target.timing.h_display)) & 0xfff8; 210 211 target.timing.h_total = 212 (((uint16)((si->ps.p1_timing.h_total / ((float)si->ps.p1_timing.h_display)) * 213 target.timing.h_display)) & 0xfff8) - 8; 214 215 /* in native mode the CRTC needs some extra time to keep synced correctly; 216 * OTOH the overlay unit distorts if we reserve too much time! */ 217 if (target.timing.h_display == si->ps.p1_timing.h_display) 218 { 219 /* NV11 timing has different constraints than later cards */ 220 if (si->ps.card_type == NV11) 221 target.timing.h_total -= 56; 222 else 223 /* confirmed NV34 with 1680x1050 panel */ 224 target.timing.h_total -= 32; 225 } 226 227 if (target.timing.h_sync_start == target.timing.h_display) 228 target.timing.h_sync_start += 8; 229 if (target.timing.h_sync_end == target.timing.h_total) 230 target.timing.h_sync_end -= 8; 231 232 /* vertical timing */ 233 target.timing.v_sync_start = 234 ((uint16)((si->ps.p1_timing.v_sync_start / ((float)si->ps.p1_timing.v_display)) * 235 target.timing.v_display)); 236 237 target.timing.v_sync_end = 238 ((uint16)((si->ps.p1_timing.v_sync_end / ((float)si->ps.p1_timing.v_display)) * 239 target.timing.v_display)); 240 241 target.timing.v_total = 242 ((uint16)((si->ps.p1_timing.v_total / ((float)si->ps.p1_timing.v_display)) * 243 target.timing.v_display)) - 1; 244 245 if (target.timing.v_sync_start == target.timing.v_display) 246 target.timing.v_sync_start += 1; 247 if (target.timing.v_sync_end == target.timing.v_total) 248 target.timing.v_sync_end -= 1; 249 250 /* disable GPU scaling testmode so automatic scaling will be done */ 251 DACW(FP_DEBUG1, 0); 252 } 253 254 /* Modify parameters as required by standard VGA */ 255 htotal = ((target.timing.h_total >> 3) - 5); 256 hdisp_e = ((target.timing.h_display >> 3) - 1); 257 hblnk_s = hdisp_e; 258 hblnk_e = (htotal + 4); 259 hsync_s = (target.timing.h_sync_start >> 3); 260 hsync_e = (target.timing.h_sync_end >> 3); 261 262 vtotal = target.timing.v_total - 2; 263 vdisp_e = target.timing.v_display - 1; 264 vblnk_s = vdisp_e; 265 vblnk_e = (vtotal + 1); 266 vsync_s = target.timing.v_sync_start; 267 vsync_e = target.timing.v_sync_end; 268 269 /* prevent memory adress counter from being reset (linecomp may not occur) */ 270 linecomp = target.timing.v_display; 271 272 /* enable access to primary head */ 273 set_crtc_owner(0); 274 275 /* Note for laptop and DVI flatpanels: 276 * CRTC timing has a seperate set of registers from flatpanel timing. 277 * The flatpanel timing registers have scaling registers that are used to match 278 * these two modelines. */ 279 { 280 LOG(4,("CRTC: Setting full timing...\n")); 281 282 /* log the mode that will be set */ 283 LOG(2,("CRTC:\n\tHTOT:%x\n\tHDISPEND:%x\n\tHBLNKS:%x\n\tHBLNKE:%x\n\tHSYNCS:%x\n\tHSYNCE:%x\n\t",htotal,hdisp_e,hblnk_s,hblnk_e,hsync_s,hsync_e)); 284 LOG(2,("VTOT:%x\n\tVDISPEND:%x\n\tVBLNKS:%x\n\tVBLNKE:%x\n\tVSYNCS:%x\n\tVSYNCE:%x\n",vtotal,vdisp_e,vblnk_s,vblnk_e,vsync_s,vsync_e)); 285 286 /* actually program the card! */ 287 /* unlock CRTC registers at index 0-7 */ 288 CRTCW(VSYNCE, (CRTCR(VSYNCE) & 0x7f)); 289 /* horizontal standard VGA regs */ 290 CRTCW(HTOTAL, (htotal & 0xff)); 291 CRTCW(HDISPE, (hdisp_e & 0xff)); 292 CRTCW(HBLANKS, (hblnk_s & 0xff)); 293 /* also unlock vertical retrace registers in advance */ 294 CRTCW(HBLANKE, ((hblnk_e & 0x1f) | 0x80)); 295 CRTCW(HSYNCS, (hsync_s & 0xff)); 296 CRTCW(HSYNCE, ((hsync_e & 0x1f) | ((hblnk_e & 0x20) << 2))); 297 298 /* vertical standard VGA regs */ 299 CRTCW(VTOTAL, (vtotal & 0xff)); 300 CRTCW(OVERFLOW, 301 ( 302 ((vtotal & 0x100) >> (8 - 0)) | ((vtotal & 0x200) >> (9 - 5)) | 303 ((vdisp_e & 0x100) >> (8 - 1)) | ((vdisp_e & 0x200) >> (9 - 6)) | 304 ((vsync_s & 0x100) >> (8 - 2)) | ((vsync_s & 0x200) >> (9 - 7)) | 305 ((vblnk_s & 0x100) >> (8 - 3)) | ((linecomp & 0x100) >> (8 - 4)) 306 )); 307 CRTCW(PRROWSCN, 0x00); /* not used */ 308 CRTCW(MAXSCLIN, (((vblnk_s & 0x200) >> (9 - 5)) | ((linecomp & 0x200) >> (9 - 6)))); 309 CRTCW(VSYNCS, (vsync_s & 0xff)); 310 CRTCW(VSYNCE, ((CRTCR(VSYNCE) & 0xf0) | (vsync_e & 0x0f))); 311 CRTCW(VDISPE, (vdisp_e & 0xff)); 312 CRTCW(VBLANKS, (vblnk_s & 0xff)); 313 CRTCW(VBLANKE, (vblnk_e & 0xff)); 314 CRTCW(LINECOMP, (linecomp & 0xff)); 315 316 /* horizontal extended regs */ 317 //fixme: we reset bit4. is this correct?? 318 CRTCW(HEB, (CRTCR(HEB) & 0xe0) | 319 ( 320 ((htotal & 0x100) >> (8 - 0)) | 321 ((hdisp_e & 0x100) >> (8 - 1)) | 322 ((hblnk_s & 0x100) >> (8 - 2)) | 323 ((hsync_s & 0x100) >> (8 - 3)) 324 )); 325 326 /* (mostly) vertical extended regs */ 327 CRTCW(LSR, 328 ( 329 ((vtotal & 0x400) >> (10 - 0)) | 330 ((vdisp_e & 0x400) >> (10 - 1)) | 331 ((vsync_s & 0x400) >> (10 - 2)) | 332 ((vblnk_s & 0x400) >> (10 - 3)) | 333 ((hblnk_e & 0x040) >> (6 - 4)) 334 //fixme: we still miss one linecomp bit!?! is this it?? 335 //| ((linecomp & 0x400) >> 3) 336 )); 337 338 /* more vertical extended regs (on GeForce cards only) */ 339 if (si->ps.card_arch >= NV10A) 340 { 341 CRTCW(EXTRA, 342 ( 343 ((vtotal & 0x800) >> (11 - 0)) | 344 ((vdisp_e & 0x800) >> (11 - 2)) | 345 ((vsync_s & 0x800) >> (11 - 4)) | 346 ((vblnk_s & 0x800) >> (11 - 6)) 347 //fixme: do we miss another linecomp bit!?! 348 )); 349 } 350 351 /* setup 'large screen' mode */ 352 if (target.timing.h_display >= 1280) 353 CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0xfb)); 354 else 355 CRTCW(REPAINT1, (CRTCR(REPAINT1) | 0x04)); 356 357 /* setup HSYNC & VSYNC polarity */ 358 LOG(2,("CRTC: sync polarity: ")); 359 temp = NV_REG8(NV8_MISCR); 360 if (target.timing.flags & B_POSITIVE_HSYNC) 361 { 362 LOG(2,("H:pos ")); 363 temp &= ~0x40; 364 } 365 else 366 { 367 LOG(2,("H:neg ")); 368 temp |= 0x40; 369 } 370 if (target.timing.flags & B_POSITIVE_VSYNC) 371 { 372 LOG(2,("V:pos ")); 373 temp &= ~0x80; 374 } 375 else 376 { 377 LOG(2,("V:neg ")); 378 temp |= 0x80; 379 } 380 NV_REG8(NV8_MISCW) = temp; 381 382 LOG(2,(", MISC reg readback: $%02x\n", NV_REG8(NV8_MISCR))); 383 } 384 385 /* always disable interlaced operation */ 386 /* (interlace is supported on upto and including NV10, NV15, and NV30 and up) */ 387 CRTCW(INTERLACE, 0xff); 388 389 /* disable CRTC slaved mode unless a panel is in use */ 390 // fixme: this kills TVout when it was in use... 391 if (!si->ps.tmds1_active) CRTCW(PIXEL, (CRTCR(PIXEL) & 0x7f)); 392 393 /* setup flatpanel if connected and active */ 394 if (si->ps.tmds1_active) 395 { 396 uint32 iscale_x, iscale_y; 397 398 /* calculate inverse scaling factors used by hardware in 20.12 format */ 399 iscale_x = (((1 << 12) * target.timing.h_display) / si->ps.p1_timing.h_display); 400 iscale_y = (((1 << 12) * target.timing.v_display) / si->ps.p1_timing.v_display); 401 402 /* unblock flatpanel timing programming (or something like that..) */ 403 CRTCW(FP_HTIMING, 0); 404 CRTCW(FP_VTIMING, 0); 405 LOG(2,("CRTC: FP_HTIMING reg readback: $%02x\n", CRTCR(FP_HTIMING))); 406 LOG(2,("CRTC: FP_VTIMING reg readback: $%02x\n", CRTCR(FP_VTIMING))); 407 408 /* enable full width visibility on flatpanel */ 409 DACW(FP_HVALID_S, 0); 410 DACW(FP_HVALID_E, (si->ps.p1_timing.h_display - 1)); 411 /* enable full height visibility on flatpanel */ 412 DACW(FP_VVALID_S, 0); 413 DACW(FP_VVALID_E, (si->ps.p1_timing.v_display - 1)); 414 415 /* nVidia cards support upscaling except on ??? */ 416 /* NV11 cards can upscale after all! */ 417 if (0)//si->ps.card_type == NV11) 418 { 419 /* disable last fetched line limiting */ 420 DACW(FP_DEBUG2, 0x00000000); 421 /* inform panel to scale if needed */ 422 if ((iscale_x != (1 << 12)) || (iscale_y != (1 << 12))) 423 { 424 LOG(2,("CRTC: DFP needs to do scaling\n")); 425 DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) | 0x00000100)); 426 } 427 else 428 { 429 LOG(2,("CRTC: no scaling for DFP needed\n")); 430 DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) & 0xfffffeff)); 431 } 432 } 433 else 434 { 435 float dm_aspect; 436 437 LOG(2,("CRTC: GPU scales for DFP if needed\n")); 438 439 /* calculate display mode aspect */ 440 dm_aspect = (target.timing.h_display / ((float)target.timing.v_display)); 441 442 /* limit last fetched line if vertical scaling is done */ 443 if (iscale_y != (1 << 12)) 444 DACW(FP_DEBUG2, ((1 << 28) | ((target.timing.v_display - 1) << 16))); 445 else 446 DACW(FP_DEBUG2, 0x00000000); 447 448 /* inform panel not to scale */ 449 DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) & 0xfffffeff)); 450 451 /* GPU scaling is automatically setup by hardware, so only modify this 452 * scalingfactor for non 4:3 (1.33) aspect panels; 453 * let's consider 1280x1024 1:33 aspect (it's 1.25 aspect actually!) */ 454 455 /* correct for widescreen panels relative to mode... 456 * (so if panel is more widescreen than mode being set) */ 457 /* BTW: known widescreen panels: 458 * 1280 x 800 (1.60), 459 * 1440 x 900 (1.60), 460 * 1680 x 1050 (1.60), 461 * 1920 x 1200 (1.60). */ 462 /* known 4:3 aspect non-standard resolution panels: 463 * 1400 x 1050 (1.33). */ 464 /* NOTE: 465 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */ 466 if ((iscale_x != (1 << 12)) && (si->ps.panel1_aspect > (dm_aspect + 0.10))) 467 { 468 uint16 diff; 469 470 LOG(2,("CRTC: (relative) widescreen panel: tuning horizontal scaling\n")); 471 472 /* X-scaling should be the same as Y-scaling */ 473 iscale_x = iscale_y; 474 /* enable testmode (b12) and program modified X-scaling factor */ 475 DACW(FP_DEBUG1, (((iscale_x >> 1) & 0x00000fff) | (1 << 12))); 476 /* center/cut-off left and right side of screen */ 477 diff = ((si->ps.p1_timing.h_display - 478 ((target.timing.h_display * (1 << 12)) / iscale_x)) 479 / 2); 480 DACW(FP_HVALID_S, diff); 481 DACW(FP_HVALID_E, ((si->ps.p1_timing.h_display - diff) - 1)); 482 } 483 /* correct for portrait panels... */ 484 /* NOTE: 485 * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */ 486 if ((iscale_y != (1 << 12)) && (si->ps.panel1_aspect < (dm_aspect - 0.10))) 487 { 488 LOG(2,("CRTC: (relative) portrait panel: should tune vertical scaling\n")); 489 /* fixme: implement if this kind of portrait panels exist on nVidia... */ 490 } 491 } 492 493 /* do some logging.. */ 494 LOG(2,("CRTC: FP_HVALID_S reg readback: $%08x\n", DACR(FP_HVALID_S))); 495 LOG(2,("CRTC: FP_HVALID_E reg readback: $%08x\n", DACR(FP_HVALID_E))); 496 LOG(2,("CRTC: FP_VVALID_S reg readback: $%08x\n", DACR(FP_VVALID_S))); 497 LOG(2,("CRTC: FP_VVALID_E reg readback: $%08x\n", DACR(FP_VVALID_E))); 498 LOG(2,("CRTC: FP_DEBUG0 reg readback: $%08x\n", DACR(FP_DEBUG0))); 499 LOG(2,("CRTC: FP_DEBUG1 reg readback: $%08x\n", DACR(FP_DEBUG1))); 500 LOG(2,("CRTC: FP_DEBUG2 reg readback: $%08x\n", DACR(FP_DEBUG2))); 501 LOG(2,("CRTC: FP_DEBUG3 reg readback: $%08x\n", DACR(FP_DEBUG3))); 502 LOG(2,("CRTC: FP_TG_CTRL reg readback: $%08x\n", DACR(FP_TG_CTRL))); 503 } 504 505 return B_OK; 506 } 507 508 status_t nv_crtc_depth(int mode) 509 { 510 uint8 viddelay = 0; 511 uint32 genctrl = 0; 512 513 /* set VCLK scaling */ 514 switch(mode) 515 { 516 case BPP8: 517 viddelay = 0x01; 518 /* genctrl b4 & b5 reset: 'direct mode' */ 519 genctrl = 0x00101100; 520 break; 521 case BPP15: 522 viddelay = 0x02; 523 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 524 genctrl = 0x00100130; 525 break; 526 case BPP16: 527 viddelay = 0x02; 528 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 529 genctrl = 0x00101130; 530 break; 531 case BPP24: 532 viddelay = 0x03; 533 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 534 genctrl = 0x00100130; 535 break; 536 case BPP32: 537 viddelay = 0x03; 538 /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ 539 genctrl = 0x00101130; 540 break; 541 } 542 /* enable access to primary head */ 543 set_crtc_owner(0); 544 545 CRTCW(PIXEL, ((CRTCR(PIXEL) & 0xfc) | viddelay)); 546 DACW(GENCTRL, genctrl); 547 548 return B_OK; 549 } 550 551 status_t nv_crtc_dpms(bool display, bool h, bool v, bool do_panel) 552 { 553 uint8 temp; 554 char msg[100]; 555 556 sprintf(msg, "CRTC: setting DPMS: "); 557 558 /* enable access to primary head */ 559 set_crtc_owner(0); 560 561 /* start synchronous reset: required before turning screen off! */ 562 SEQW(RESET, 0x01); 563 564 temp = SEQR(CLKMODE); 565 if (display) 566 { 567 /* turn screen on */ 568 SEQW(CLKMODE, (temp & ~0x20)); 569 570 /* end synchronous reset because display should be enabled */ 571 SEQW(RESET, 0x03); 572 573 if (do_panel && si->ps.tmds1_active && !si->ps.laptop) 574 { 575 /* restore original panelsync and panel-enable */ 576 uint32 panelsync = 0x00000000; 577 if(si->ps.p1_timing.flags & B_POSITIVE_VSYNC) panelsync |= 0x00000001; 578 if(si->ps.p1_timing.flags & B_POSITIVE_HSYNC) panelsync |= 0x00000010; 579 /* display enable polarity (not an official flag) */ 580 if(si->ps.p1_timing.flags & B_BLANK_PEDESTAL) panelsync |= 0x10000000; 581 DACW(FP_TG_CTRL, ((DACR(FP_TG_CTRL) & 0xcfffffcc) | panelsync)); 582 583 //fixme?: looks like we don't need this after all: 584 /* powerup both LVDS (laptop panellink) and TMDS (DVI panellink) 585 * internal transmitters... */ 586 /* note: 587 * the powerbits in this register are hardwired to the DVI connectors, 588 * instead of to the DACs! (confirmed NV34) */ 589 //fixme... 590 //DACW(FP_DEBUG0, (DACR(FP_DEBUG0) & 0xcfffffff)); 591 /* ... and powerup external TMDS transmitter if it exists */ 592 /* (confirmed OK on NV28 and NV34) */ 593 //CRTCW(0x59, (CRTCR(0x59) | 0x01)); 594 595 sprintf(msg, "%s(panel-)", msg); 596 } 597 598 sprintf(msg, "%sdisplay on, ", msg); 599 } 600 else 601 { 602 /* turn screen off */ 603 SEQW(CLKMODE, (temp | 0x20)); 604 605 if (do_panel && si->ps.tmds1_active && !si->ps.laptop) 606 { 607 /* shutoff panelsync and disable panel */ 608 DACW(FP_TG_CTRL, ((DACR(FP_TG_CTRL) & 0xcfffffcc) | 0x20000022)); 609 610 //fixme?: looks like we don't need this after all: 611 /* powerdown both LVDS (laptop panellink) and TMDS (DVI panellink) 612 * internal transmitters... */ 613 /* note: 614 * the powerbits in this register are hardwired to the DVI connectors, 615 * instead of to the DACs! (confirmed NV34) */ 616 //fixme... 617 //DACW(FP_DEBUG0, (DACR(FP_DEBUG0) | 0x30000000)); 618 /* ... and powerdown external TMDS transmitter if it exists */ 619 /* (confirmed OK on NV28 and NV34) */ 620 //CRTCW(0x59, (CRTCR(0x59) & 0xfe)); 621 622 sprintf(msg, "%s(panel-)", msg); 623 } 624 625 sprintf(msg, "%sdisplay off, ", msg); 626 } 627 628 if (h) 629 { 630 CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0x7f)); 631 sprintf(msg, "%shsync enabled, ", msg); 632 } 633 else 634 { 635 CRTCW(REPAINT1, (CRTCR(REPAINT1) | 0x80)); 636 sprintf(msg, "%shsync disabled, ", msg); 637 } 638 if (v) 639 { 640 CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0xbf)); 641 sprintf(msg, "%svsync enabled\n", msg); 642 } 643 else 644 { 645 CRTCW(REPAINT1, (CRTCR(REPAINT1) | 0x40)); 646 sprintf(msg, "%svsync disabled\n", msg); 647 } 648 649 LOG(4, (msg)); 650 651 return B_OK; 652 } 653 654 status_t nv_crtc_set_display_pitch() 655 { 656 uint32 offset; 657 658 LOG(4,("CRTC: setting card pitch (offset between lines)\n")); 659 660 /* figure out offset value hardware needs */ 661 offset = si->fbc.bytes_per_row / 8; 662 663 LOG(2,("CRTC: offset register set to: $%04x\n", offset)); 664 665 /* enable access to primary head */ 666 set_crtc_owner(0); 667 668 /* program the card */ 669 CRTCW(PITCHL, (offset & 0x00ff)); 670 CRTCW(REPAINT0, ((CRTCR(REPAINT0) & 0x1f) | ((offset & 0x0700) >> 3))); 671 672 return B_OK; 673 } 674 675 status_t nv_crtc_set_display_start(uint32 startadd,uint8 bpp) 676 { 677 uint8 temp; 678 uint32 timeout = 0; 679 680 LOG(4,("CRTC: setting card RAM to be displayed bpp %d\n", bpp)); 681 682 LOG(2,("CRTC: startadd: $%08x\n", startadd)); 683 LOG(2,("CRTC: frameRAM: $%08x\n", si->framebuffer)); 684 LOG(2,("CRTC: framebuffer: $%08x\n", si->fbc.frame_buffer)); 685 686 /* we might have no retraces during setmode! */ 687 /* wait 25mS max. for retrace to occur (refresh > 40Hz) */ 688 while (((NV_REG32(NV32_RASTER) & 0x000007ff) < si->dm.timing.v_display) && 689 (timeout < (25000/10))) 690 { 691 /* don't snooze much longer or retrace might get missed! */ 692 snooze(10); 693 timeout++; 694 } 695 696 /* enable access to primary head */ 697 set_crtc_owner(0); 698 699 if (si->ps.card_arch == NV04A) 700 { 701 /* upto 32Mb RAM adressing: must be used this way on pre-NV10! */ 702 703 /* set standard registers */ 704 /* (NVidia: startadress in 32bit words (b2 - b17) */ 705 CRTCW(FBSTADDL, ((startadd & 0x000003fc) >> 2)); 706 CRTCW(FBSTADDH, ((startadd & 0x0003fc00) >> 10)); 707 708 /* set extended registers */ 709 /* NV4 extended bits: (b18-22) */ 710 temp = (CRTCR(REPAINT0) & 0xe0); 711 CRTCW(REPAINT0, (temp | ((startadd & 0x007c0000) >> 18))); 712 /* NV4 extended bits: (b23-24) */ 713 temp = (CRTCR(HEB) & 0x9f); 714 CRTCW(HEB, (temp | ((startadd & 0x01800000) >> 18))); 715 } 716 else 717 { 718 /* upto 4Gb RAM adressing: must be used on NV10 and later! */ 719 /* NOTE: 720 * While this register also exists on pre-NV10 cards, it will 721 * wrap-around at 16Mb boundaries!! */ 722 723 /* 30bit adress in 32bit words */ 724 NV_REG32(NV32_NV10FBSTADD32) = (startadd & 0xfffffffc); 725 } 726 727 /* set NV4/NV10 byte adress: (b0 - 1) */ 728 ATBW(HORPIXPAN, ((startadd & 0x00000003) << 1)); 729 730 return B_OK; 731 } 732 733 status_t nv_crtc_cursor_init() 734 { 735 int i; 736 uint32 * fb; 737 /* cursor bitmap will be stored at the start of the framebuffer */ 738 const uint32 curadd = 0; 739 740 /* enable access to primary head */ 741 set_crtc_owner(0); 742 743 /* set cursor bitmap adress ... */ 744 if ((si->ps.card_arch == NV04A) || (si->ps.laptop)) 745 { 746 /* must be used this way on pre-NV10 and on all 'Go' cards! */ 747 748 /* cursorbitmap must start on 2Kbyte boundary: */ 749 /* set adress bit11-16, and set 'no doublescan' (registerbit 1 = 0) */ 750 CRTCW(CURCTL0, ((curadd & 0x0001f800) >> 9)); 751 /* set adress bit17-23, and set graphics mode cursor(?) (registerbit 7 = 1) */ 752 CRTCW(CURCTL1, (((curadd & 0x00fe0000) >> 17) | 0x80)); 753 /* set adress bit24-31 */ 754 CRTCW(CURCTL2, ((curadd & 0xff000000) >> 24)); 755 } 756 else 757 { 758 /* upto 4Gb RAM adressing: 759 * can be used on NV10 and later (except for 'Go' cards)! */ 760 /* NOTE: 761 * This register does not exist on pre-NV10 and 'Go' cards. */ 762 763 /* cursorbitmap must still start on 2Kbyte boundary: */ 764 NV_REG32(NV32_NV10CURADD32) = (curadd & 0xfffff800); 765 } 766 767 /* set cursor colour: not needed because of direct nature of cursor bitmap. */ 768 769 /*clear cursor*/ 770 fb = (uint32 *) si->framebuffer + curadd; 771 for (i=0;i<(2048/4);i++) 772 { 773 fb[i]=0; 774 } 775 776 /* select 32x32 pixel, 16bit color cursorbitmap, no doublescan */ 777 NV_REG32(NV32_CURCONF) = 0x02000100; 778 779 /* activate hardware-sync between cursor updates and vertical retrace where 780 * available */ 781 if (si->ps.card_arch >= NV10A) 782 DACW(NV10_CURSYNC, (DACR(NV10_CURSYNC) | 0x02000000)); 783 784 /* activate hardware cursor */ 785 nv_crtc_cursor_show(); 786 787 return B_OK; 788 } 789 790 status_t nv_crtc_cursor_show() 791 { 792 LOG(4,("CRTC: enabling cursor\n")); 793 794 /* enable access to CRTC1 on dualhead cards */ 795 set_crtc_owner(0); 796 797 /* b0 = 1 enables cursor */ 798 CRTCW(CURCTL0, (CRTCR(CURCTL0) | 0x01)); 799 800 /* workaround for hardware bug confirmed existing on NV43: 801 * Cursor visibility is not updated without a position update if its hardware 802 * retrace sync is enabled. */ 803 if (si->ps.card_arch == NV40A) DACW(CURPOS, (DACR(CURPOS))); 804 805 return B_OK; 806 } 807 808 status_t nv_crtc_cursor_hide() 809 { 810 LOG(4,("CRTC: disabling cursor\n")); 811 812 /* enable access to primary head */ 813 set_crtc_owner(0); 814 815 /* b0 = 0 disables cursor */ 816 CRTCW(CURCTL0, (CRTCR(CURCTL0) & 0xfe)); 817 818 /* workaround for hardware bug confirmed existing on NV43: 819 * Cursor visibility is not updated without a position update if its hardware 820 * retrace sync is enabled. */ 821 if (si->ps.card_arch == NV40A) DACW(CURPOS, (DACR(CURPOS))); 822 823 return B_OK; 824 } 825 826 /*set up cursor shape*/ 827 status_t nv_crtc_cursor_define(uint8* andMask,uint8* xorMask) 828 { 829 int x, y; 830 uint8 b; 831 uint16 *cursor; 832 uint16 pixel; 833 834 /* get a pointer to the cursor */ 835 cursor = (uint16*) si->framebuffer; 836 837 /* draw the cursor */ 838 /* (Nvidia cards have a RGB15 direct color cursor bitmap, bit #16 is transparancy) */ 839 for (y = 0; y < 16; y++) 840 { 841 b = 0x80; 842 for (x = 0; x < 8; x++) 843 { 844 /* preset transparant */ 845 pixel = 0x0000; 846 /* set white if requested */ 847 if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; 848 /* set black if requested */ 849 if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; 850 /* set invert if requested */ 851 if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; 852 /* place the pixel in the bitmap */ 853 cursor[x + (y * 32)] = pixel; 854 b >>= 1; 855 } 856 xorMask++; 857 andMask++; 858 b = 0x80; 859 for (; x < 16; x++) 860 { 861 /* preset transparant */ 862 pixel = 0x0000; 863 /* set white if requested */ 864 if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; 865 /* set black if requested */ 866 if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; 867 /* set invert if requested */ 868 if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; 869 /* place the pixel in the bitmap */ 870 cursor[x + (y * 32)] = pixel; 871 b >>= 1; 872 } 873 xorMask++; 874 andMask++; 875 } 876 877 return B_OK; 878 } 879 880 /* position the cursor */ 881 status_t nv_crtc_cursor_position(uint16 x, uint16 y) 882 { 883 /* the cursor position is updated during retrace by card hardware except for 884 * pre-GeForce cards */ 885 if (si->ps.card_arch < NV10A) 886 { 887 uint16 yhigh; 888 889 /* make sure we are beyond the first line of the cursorbitmap being drawn during 890 * updating the position to prevent distortions: no double buffering feature */ 891 /* Note: 892 * we need to return as quick as possible or some apps will exhibit lagging.. */ 893 894 /* read the old cursor Y position */ 895 yhigh = ((DACR(CURPOS) & 0x0fff0000) >> 16); 896 /* make sure we will wait until we are below both the old and new Y position: 897 * visible cursorbitmap drawing needs to be done at least... */ 898 if (y > yhigh) yhigh = y; 899 900 if (yhigh < (si->dm.timing.v_display - 16)) 901 { 902 /* we have vertical lines below old and new cursorposition to spare. So we 903 * update the cursor postion 'mid-screen', but below that area. */ 904 while (((uint16)(NV_REG32(NV32_RASTER) & 0x000007ff)) < (yhigh + 16)) 905 { 906 snooze(10); 907 } 908 } 909 else 910 { 911 /* no room to spare, just wait for retrace (is relatively slow) */ 912 while ((NV_REG32(NV32_RASTER) & 0x000007ff) < si->dm.timing.v_display) 913 { 914 /* don't snooze much longer or retrace might get missed! */ 915 snooze(10); 916 } 917 } 918 } 919 920 /* update cursorposition */ 921 DACW(CURPOS, ((x & 0x0fff) | ((y & 0x0fff) << 16))); 922 923 return B_OK; 924 } 925 926 status_t nv_crtc_stop_tvout(void) 927 { 928 LOG(4,("CRTC: stopping TV output\n")); 929 930 /* enable access to primary head */ 931 set_crtc_owner(0); 932 933 /* just to be sure Vsync is _really_ enabled */ 934 CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0xbf)); 935 936 /* wait for one image to be generated to make sure VGA has kicked in and is 937 * running OK before continuing... 938 * (Kicking in will fail often if we do not wait here) */ 939 /* Note: 940 * The used CRTC's Vsync is required to be enabled here. The DPMS state 941 * programming in the driver makes sure this is the case. 942 * (except for driver startup: see nv_general.c.) */ 943 944 /* make sure we are 'in' active VGA picture */ 945 while (NV_REG8(NV8_INSTAT1) & 0x08) snooze(1); 946 /* wait for next vertical retrace start on VGA */ 947 while (!(NV_REG8(NV8_INSTAT1) & 0x08)) snooze(1); 948 /* now wait until we are 'in' active VGA picture again */ 949 while (NV_REG8(NV8_INSTAT1) & 0x08) snooze(1); 950 951 952 /* set CRTC to master mode (b7 = 0) if it wasn't slaved for a panel before */ 953 if (!(si->ps.slaved_tmds1)) CRTCW(PIXEL, (CRTCR(PIXEL) & 0x03)); 954 955 /* CAUTION: 956 * On old cards, PLLSEL (and TV_SETUP?) cannot be read (sometimes?), but 957 * write actions do succeed ... 958 * This is confirmed for both ISA and PCI access, on NV04 and NV11. */ 959 960 /* setup TVencoder connection */ 961 /* b1-0 = %00: encoder type is SLAVE; 962 * b24 = 1: VIP datapos is b0-7 */ 963 //fixme if needed: setup completely instead of relying on pre-init by BIOS.. 964 //(it seems to work OK on NV04 and NV11 although read reg. doesn't seem to work) 965 DACW(TV_SETUP, ((DACR(TV_SETUP) & ~0x00000003) | 0x01000000)); 966 967 /* tell GPU to use pixelclock from internal source instead of using TVencoder */ 968 if (si->ps.secondary_head) 969 DACW(PLLSEL, 0x30000f00); 970 else 971 DACW(PLLSEL, 0x10000700); 972 973 /* HTOTAL, VTOTAL and OVERFLOW return their default CRTC use, instead of 974 * H, V-low and V-high 'shadow' counters(?)(b0, 4 and 6 = 0) (b7 use = unknown) */ 975 CRTCW(TREG, 0x00); 976 977 /* select panel encoder, not TV encoder if needed (b0 = 1). 978 * Note: 979 * Both are devices (often) using the CRTC in slaved mode. */ 980 if (si->ps.slaved_tmds1) CRTCW(LCD, (CRTCR(LCD) | 0x01)); 981 982 return B_OK; 983 } 984 985 status_t nv_crtc_start_tvout(void) 986 { 987 LOG(4,("CRTC: starting TV output\n")); 988 989 if (si->ps.secondary_head) 990 { 991 /* switch TV encoder to CRTC1 */ 992 NV_REG32(NV32_2FUNCSEL) &= ~0x00000100; 993 NV_REG32(NV32_FUNCSEL) |= 0x00000100; 994 } 995 996 /* enable access to primary head */ 997 set_crtc_owner(0); 998 999 /* CAUTION: 1000 * On old cards, PLLSEL (and TV_SETUP?) cannot be read (sometimes?), but 1001 * write actions do succeed ... 1002 * This is confirmed for both ISA and PCI access, on NV04 and NV11. */ 1003 1004 /* setup TVencoder connection */ 1005 /* b1-0 = %01: encoder type is MASTER; 1006 * b24 = 1: VIP datapos is b0-7 */ 1007 //fixme if needed: setup completely instead of relying on pre-init by BIOS.. 1008 //(it seems to work OK on NV04 and NV11 although read reg. doesn't seem to work) 1009 DACW(TV_SETUP, ((DACR(TV_SETUP) & ~0x00000002) | 0x01000001)); 1010 1011 /* tell GPU to use pixelclock from TVencoder instead of using internal source */ 1012 /* (nessecary or display will 'shiver' on both TV and VGA.) */ 1013 if (si->ps.secondary_head) 1014 DACW(PLLSEL, 0x20030f00); 1015 else 1016 DACW(PLLSEL, 0x00030700); 1017 1018 /* Set overscan color to 'black' */ 1019 /* note: 1020 * Change this instruction for a visible overscan color if you're trying to 1021 * center the output on TV. Use it as a guide-'line' then ;-) */ 1022 ATBW(OSCANCOLOR, 0x00); 1023 1024 /* set CRTC to slaved mode (b7 = 1) and clear TVadjust (b3-5 = %000) */ 1025 CRTCW(PIXEL, ((CRTCR(PIXEL) & 0xc7) | 0x80)); 1026 /* select TV encoder, not panel encoder (b0 = 0). 1027 * Note: 1028 * Both are devices (often) using the CRTC in slaved mode. */ 1029 CRTCW(LCD, (CRTCR(LCD) & 0xfe)); 1030 1031 /* HTOTAL, VTOTAL and OVERFLOW return their default CRTC use, instead of 1032 * H, V-low and V-high 'shadow' counters(?)(b0, 4 and 6 = 0) (b7 use = unknown) */ 1033 CRTCW(TREG, 0x80); 1034 1035 return B_OK; 1036 } 1037